CN1678127A - Large-capacity multicast strict blocking-free cross array structure - Google Patents
Large-capacity multicast strict blocking-free cross array structure Download PDFInfo
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Abstract
The structure of matrix comprises input stage, second stage and output stage. The input stage includes 16 modules of cross-interaction matrixes in type of one divided into two. Receiving one route input signal in 80Gb/s, each module outputs two routes of signal in 80Gb/s. second stage consists of 4 matrix modules in 640Gb/s. receiving 8*80Gb/s output from the input stage, each cross-interaction matrix module outputs 8*80Gb/s signal. The output stage is composed of 16 matrixes in 160Gb/s in type of one selected from two. Receiving 2*80Gb/s signal output from the second stage, each cross-interaction matrix module outputs 80Gb/s signal. Outputted each VC - 4 time slot signal carries out selection from only two inputted VC - 4 time slot signals. The cross-interaction matrixes are applicable to optical cross-connected device, SDH device and digital cross-connected device, possessing advantages of few cross-connected chips, high economical efficiency and strict nonblocking.
Description
Technical field
The present invention relates to the digital fiber communication technical field, particularly relate to a kind of large-capacity multicast strict blocking-free cross array structure.
Background technology
Along with being the arrival of the information age of representative with the Internet technology, people are increasing to the demand of communication bandwidth.The application of dense wave division multipurpose (DWDM) system has solved the bandwidth problem of message transmission, but the little problem of node cross-capacity does not still solve, thereby becomes the bottleneck problem in the network.
In the digital fiber communication system, a large amount of interconnection demands is arranged.Cross-connect matrix is the core of optical cross-connection equipment, synchronous digital hierarchy/Synchronous Optical Network equipment, digital cross connect equipment even switch device.
Mainly contain two kinds of cross matrix types commonly used at present, i.e. square matrix and CLOS matrix.Square matrix adopts N * N structure, can both realize that to any business 100% is clog-free, and the interconnection time is shorter, but along with capacity N increases, required cross matrix scale is by its quadratic growth, so a square matrix is not suitable for doing big capacity cross matrix.And that the CLOS matrix has a capacity is big, the advantage that required interconnection chip is few, economy is high, but be difficult to realize the multicast strictly non-blocking, and signal link relation and control algolithm unusual complexity all.
At present in SDH/SONET and DXC equipment, the scheduling of various granularity services and talk about by cross chips up and down and finish.The cross grain of cross chips can be VC-4/OC-1, VC-12 etc., and cross-capacity does not wait from 40Gb/s to 160Gb/s.With the 160Gb/s cross chips is example, if cross grain is VC-4, the VC-4 quantity of cross chips input port and output port is 1024 so.For the cross matrix of a 1.28Tb/s, the VC-4 quantity of its input port and output port is 8192, obviously, with present chip technology, can't realize the cross matrix of T (1Tb/s=1000Gb/s) bit-level capacity on a slice chip.
In order to seek to utilize the low capacity cross chips to make up the method for big capacity cross matrix, people have invented a kind of method: every byte 8 bits are divided into several bit groups, then the same bits group of different bytes being placed on same cross chips intersects, by the collaborative simultaneously more jumbo cross matrix of realization that intersects of several cross chips, the method is called bit and cuts apart (Bit Slice) technology.Some interface chip and cross chips have adopted this technology in SDH/SONET and DXC equipment at present, by each byte being divided into 24 bit groups (also can be divided into 42 bit groups or 81 bit groups), thereby can make up 2 times (also can be 4 or 8 times) in the cross matrix of single-chip cross-capacity with 2 (also can be 4 or 8) cross chips.Referring to shown in Figure 1, adopt the bit cutting techniques, the professional dish of 10Gb/s is divided into 42 bit groups to each byte, the same bits group of different bytes is placed on the bus of same 2.5Gb/s, 4 2.5Gb/s bus signals of same 10Gb/s business enter 4 cross chips respectively, and the data of coming out after intersecting through cross matrix enter the byte signal that will cut apart again behind the professional dish of 10Gb/s with the bus mode of 4 2.5Gb/s and revert back complete byte signal.Be made of the cross matrix of 640Gb/s capacity in Fig. 1 frame of broken lines 4 160Gb/s cross chips, for this matrix, as long as monolithic 160Gb/s cross chips is the multicast strictly non-blocking, the 640Gb/s cross matrix in the frame of broken lines also is the multicast strictly non-blocking.Fig. 1 has reflected the annexation of 640Gb/s cross matrix and 64 professional dishes of 10Gb/s in detail.
Under the given condition of monolithic chip cross-capacity, though the bit cutting techniques has enlarged the cross-capacity of monolithic cross chips to a certain extent, but since at present microelectric technique and chip cooling etc. all multifactor restrictions, obtain more jumbo cross matrix still will be by multistage intersection realization.Proposed capacity shown in Figure 2 is the multicast strict blocking-free cross array construction method of 1.28Tb/s for this reason, and the 2nd grade of 8 640Gb/s Cross modules with 3rd level are identical among Fig. 2, all adopts the method shown in Fig. 1 frame of broken lines to constitute.
Referring to Fig. 2, the cross matrix structure is divided into 3 grades, and the 1280Gb/s signal of importing is divided into SR1-SR4 totally 4 groups, every group of 320Gb/s.4 groups of 320Gb/s signals enter the 1st grade of F1-F4 module respectively and become two the 2nd grade of S1-S4 that give cross matrix behind the signal again that broadcast.Because S1-S4 all has any multicast strictly non-blocking of 640Gb/s crossing, therefore any one the 320Gb/s signal in 4 320Gb/s signals being sent by S1 and S2 can be all from SR1, also can be all from SR2, it also can be the combination in any of SR1 and SR2, in like manner, any one 320Gb/s signal in 4 320Gb/s signals being sent by S3 and S4 can also can be the combination in any of SR3 and SR4 all from SR4 also all from SR3; Receive 4 3rd level module T1-T4 from 8 320Gb/s signals that S1-S4 sends according to Fig. 2,2 320Gb/s input term signals for any one 640Gb/s module of 3rd level, one of them is from S1 or S2, another is from S3 or S4, because T1-T4 also has any multicast strictly non-blocking of 640Gb/s crossing, therefore conclude that any one 320Gb/s signal (any one among the ST1-ST4) by the output of 3rd level module can be the combination in any of full-scale input SR1-SR4, thereby can conclude that whole 1.28Tb/s cross matrix is the multicast strictly non-blocking.
Fig. 5 is the detailed annexations of T1 module and the 2nd grade of S1, S3 module and 32 professional dishes of 10Gb/s in the 3rd level of cross matrix of Fig. 2, and the annexation and the T1 of T2-T4 module are similar, are illustrated among Fig. 2.The T1 module is made up of the cross chips of 4 160Gb/s capacity, and S1 and S3 respectively export 32 * 10Gb/s signal to the T1 module among the figure, and T1 module selection wherein 32 * 10Gb/s signal outputs to the professional dish of 32 10Gb/s.Note, the identical output of numbering must be same 10Gb/s signal in 4 cross chips of S1 or S3, as seen from the figure, any one is by the 10Gb/s signal of S1 or S3 output, its 4 2.5Gb/s signals all are 4 cross chips A from the 2nd grade, B, C, D enters 4 cross chips A of T1 respectively, B, C, D, with the 1st 10Gb/s signal of S1 output is example (among the figure 4 dotted line shown in), can see that this 10Gb/s signal is respectively by 4 cross chips A of S1 module, B, C, No. 1 port output of D enters 4 cross chips A of T1 module respectively, B, C, No. 1 port of D; Can also see by figure, output to 4 2.5Gb/s signals of the professional dish of any 10Gb/s, must be from 4 cross chips A, B of T1 module, the same port of C, D, for example the input that the 1#10Gb/s business is coiled among the figure is from 4 cross chips A, B of T1 module, No. 1 port of C, D.As shown in Figure 5, be placed on respectively in 4 cross chips with 4 different bit groups after 3rd level all is that same 10Gb/s signal bit is cut apart at the 2nd grade of cross matrix and intersect, visible 10Gb/s signal arbitrarily all will pass 4 cross chips simultaneously in the 3rd level Cross module T1-T4 that intersects.
1.28Tb/s multicast strict blocking-free cross array from Fig. 2 and Fig. 5 as can be seen, because the T1-T4 of 3rd level realizes selecting the function of 320Gb/s signal output from the 640Gb/s signal by 4 160Gb/s cross chips collaborative works, its shortcoming has: as long as 1. there is 1 chip to break down, whole 320Gb/s signal output is all unavailable, causes reliability to reduce; 2. because 1.28Tb/s equipment is very huge, be placed in a plurality of machine frames after when reality realizes, need intersecting separately 3 grades, and these modules of F1-F4 and T1-T4 are put together owing to coiling with the polylith business, and the volume of its individual module is too huge, makes that entire equipment is difficult to manufacture; 3. the basic service unit is 320Gb/s, at the equipment construction initial stage, if only need 160Gb/s or 80Gb/s following less when professional, will form the wasting of resources.4. each VC-4 that the 3rd level that intersects is exported selects in a large amount of (4096) VC-4, intersects and controls relative complex.
Summary of the invention
The object of the invention provides a kind of large-capacity multicast strict blocking-free cross array structure, in order to solve the problem of above-mentioned existence, flexible Application bit cutting techniques utilizes the cross chips of low capacity or the multicast strict blocking-free cross array that matrix makes up more extensive capacity.
A kind of large-capacity multicast strict blocking-free cross array structure provided by the invention is made up of for three grades input stage, the 2nd grade and output stage, it is characterized in that:
Input stage is made of 16 1 fen crossing matrix modules of 2, and each crossing matrix modules receives one road 80Gb/s input signal, the two two-way 80Gb/s signals of broadcasting of output;
The 2nd grade, constitute by 4 640Gb/s crossing matrix modules, each 640Gb/s crossing matrix modules receives 8 road 80Gb/s signals of input stage output, exports 8 road 80Gb/s signals;
Output stage, the crossing matrix modules that is input to 80Gb/s output by 16 160Gb/s constitutes, the 1-8 crossing matrix modules respectively receives 1 road 80Gb/s signal from the output of the 2nd grade of crossing matrix modules 1 and 3 respectively, the 9-16 crossing matrix modules respectively receives 1 road 80Gb/s signal from the output of the 2nd grade of crossing matrix modules 2 and 4 respectively, each output stage crossing matrix modules is selected output 80Gb/s signal in the 160Gb/s input signal, and each VC-4 time slot signal of output only needs to select in the VC-4 of 2 inputs time slot signal.
According to above-mentioned large-capacity multicast strict blocking-free cross array structure of the present invention, it is characterized in that described 640Gb/s crossing matrix modules and 160Gb/s crossing matrix modules all are strict blocking-free cross arrays.
According to above-mentioned large-capacity multicast strict blocking-free cross array structure of the present invention, it is characterized in that:
The 2nd grade 640Gb/s crossing matrix modules 1 and 2 input are connected to the 1-8 road output of input stage, export 1-8 road 80Gb/s signal respectively;
The 2nd grade 640Gb/s crossing matrix modules 3 and 4 input are connected to the 9-16 road output of input stage, export 9-16 road 80Gb/s signal respectively.
According to above-mentioned large-capacity multicast strict blocking-free cross array structure of the present invention, it is characterized in that:
Described input stage is made of 16 crossing matrix modules;
Described 640Gb/s crossing matrix modules is made of 4 160Gb/s cross chips;
Described 160Gb/s crossing matrix modules is made of 1 160Gb/s cross chips.
According to above-mentioned large-capacity multicast strict blocking-free cross array structure of the present invention, it is characterized in that also comprising the professional dish of 10Gb/s, the output of each crossing matrix modules of 3rd level connects the professional dish of 8 10Gb/s respectively.
A kind of large-capacity multicast strict blocking-free cross array structure also is provided according to the present invention, also forms for three grades, it is characterized in that by input stage, the 2nd grade and output stage:
Input stage is made of 81 fen crossing matrix modules of 2, and each crossing matrix modules receives one road 160Gb/s input signal, the two two-way 160Gb/s signals of broadcasting of output;
The 2nd grade, constitute by 4 640Gb/s crossing matrix modules, each 640Gb/s crossing matrix modules receives 4 road 160Gb/s signals of input stage output, exports 4 road 160Gb/s signals;
Output stage, the crossing matrix modules that is input to 160Gb/s output by 8 320Gb/s constitutes, the 1-4 crossing matrix modules respectively receives 1 road 160Gb/s signal from the output of the 2nd grade of crossing matrix modules 1 and 3 respectively, the 5-8 crossing matrix modules respectively receives 1 road 160Gb/s signal from the output of the 2nd grade of crossing matrix modules 2 and 4 respectively, each output stage crossing matrix modules is selected output 160Gb/s signal in the 320Gb/s input signal, and each VC-4 time slot signal of output only needs to select in the VC-4 of 2 inputs time slot signal.
According to above-mentioned large-capacity multicast strict blocking-free cross array structure of the present invention, it is characterized in that described 640Gb/s crossing matrix modules and 320Gb/s crossing matrix modules all are strict blocking-free cross arrays.
According to above-mentioned large-capacity multicast strict blocking-free cross array structure of the present invention, it is characterized in that:
The 2nd grade 640Gb/s crossing matrix modules 1 and 2 input are connected to the 1-4 road output of input stage, export 1-4 road 160Gb/s signal respectively;
The 2nd grade 640Gb/s crossing matrix modules 3 and 4 input are connected to the 5-8 road output of input stage, export 5-8 road 160Gb/s signal respectively.
According to above-mentioned large-capacity multicast strict blocking-free cross array structure of the present invention, it is characterized in that:
Described input stage is made of 8 crossing matrix modules;
Described 640Gb/s crossing matrix modules is made of 4 160Gb/s cross chips;
Described 320Gb/s crossing matrix modules is made of 2 160Gb/s cross chips.
According to above-mentioned large-capacity multicast strict blocking-free cross array structure of the present invention, it is characterized in that also comprising the professional dish of 10Gb/s, the output of each crossing matrix modules of 3rd level connects the professional dish of 16 10Gb/s respectively.
The present invention adopts the bit cutting techniques, utilizes the cross chips of low capacity to be built into large-capacity multicast strict blocking-free cross array, and circuit is realized having more reliability, economy and productibility, and can make control algolithm simpler.
In the technical scheme of the present invention shown in Fig. 3 (the more details that also comprises Fig. 6 is showed), because the T1-T16 of 3rd level all only realizes selecting the function of 80Gb/s signal output from the 160Gb/s signal with 1 160Gb/s cross chips, when 1 chip breaks down, only can cause the output of 80Gb/s signal unavailable, outage capacity has only 1/4th of existing cross matrix, and reliability improves; Because the capacity of module T1-T16 and F1-F16 all is reduced to 1/4th of existing cross matrix, make that volume reduced when the professional dish of these modules and polylith was put together, be placed in the different machine frames after 3 grades of cross matrixes can being separated, be convenient to entire equipment and manufacture; The basic service unit is 80Gb/s, the equipment construction initial stage, if only need 160Gb/s or 80Gb/s following less when professional, can not form the wasting of resources, and economy improves; By the control to the 2nd grade of intersection, each VC-4 that the 3rd level that intersects is exported only needs select in the VC-4 of 2 inputs, and the control of whole intersection is simpler.
Cross matrix construction method of the present invention not only can have the advantage that the interconnection chip is few, economy is high of CLOS matrix, and can realize the multicast strictly non-blocking, and the signal link relation and the control algolithm of intersecting are simple, have very strong practicality.
Description of drawings
Fig. 1 is the schematic diagram with the 640Gb/s cross matrix of 4 160Gb/s cross chips structures.
Fig. 2 is the schematic diagram of existing 1.28Tb/s multicast strict blocking-free cross array.
Fig. 3 is the schematic diagram according to the 1.28Tb/s multicast strict blocking-free cross array of first case study on implementation of the present invention.
Fig. 4 is the schematic diagram according to the 1.28Tb/s multicast strict blocking-free cross array of second case study on implementation of the present invention.
The schematic diagram of the input and output annexation of T1 in the 3rd level of the existing 1.28Tb/s multicast strict blocking-free cross array of Fig. 5.
Fig. 6 is the schematic diagram according to the input and output annexation of T1 in the 3rd level of the 1.28Tb/s multicast strict blocking-free cross array of first case study on implementation of the present invention.
Fig. 7 is the schematic diagram according to the input and output annexation of T1 in the 3rd level of the 1.28Tb/s multicast strict blocking-free cross array of second case study on implementation of the present invention.
Embodiment
The clog-free cross matrix construction method of large-capacity multicast that the present invention proposes is to a kind of optimization of prior art scheme and improves.Large-capacity multicast strict blocking-free cross array structure of the present invention as shown in Figure 3.Technical scheme of the present invention and scheme shown in Figure 2 are all inequality at the 1st grade that intersects and 3rd level, and the difference of 3rd level just technical solution of the present invention improve the essence place.
The following describes the large-capacity multicast strict blocking-free cross array structure of first case study on implementation of the present invention shown in Figure 3.In Fig. 3, the cross matrix structure is divided into 3 grades, and first order F level is an input stage, and the 1280Gb/s signal of importing is divided into SR1-SR16 totally 16 groups, every group of 80Gb/s.16 groups of 80Gb/s signals enter the 1st grade crossing matrix modules 1-16 (hereinafter to be referred as module F1-F16) respectively and become and twoly broadcast signal, are promptly finished 1 minute 2 function of signal by module F1-F16.The signal that is come out by module F1-F16 is given the 2nd grade of cross matrix, i.e. S level, and the S level is made of 640Gb/s crossing matrix modules 1-4 (hereinafter to be referred as module S1-S4).Module S1 and S2 receive the output of input stage module F1-F8, module S3, and S4 receives the output of input stage module F9-F16.Module S1-S4 all has any multicast strictly non-blocking of 640Gb/s crossing, therefore can be the combination in any of input signal SR1-SR8 by any one the 80Gb/s signal in 16 80Gb/s signals of module S1 and S2 output, in like manner, can be the combination in any of SR9-SR16 by any one the 80Gb/s signal in 16 80Gb/s signals of module S3 and S4 output.According to shown in Figure 3, the third level is that output stage is made of 16 crossing matrix modules 1-16 (hereinafter to be referred as module T1-T16).Module T1-T8 respectively receives 1 road 80Gb/s signal from the output of the 2nd grade of S1 and S3 respectively, module T9-T16 respectively receives 1 road 80Gb/s signal from the output of module S2 and S4 respectively, therefore, receive 16 module T1-T16 of 3rd level from 32 80Gb/s signals of module S1-S4 output, in any one 160Gb/s Cross module of 3rd level or 2 the 80Gb/s input signals of 1 160Gb/s cross chips, a 80Gb/s input signal is from module S1 or S2, another 80Gb/s input signal is from module S3 or S4, because T1-T16 has any multicast strictly non-blocking of 160Gb/s crossing (monolithic cross chips assurance itself), therefore can conclude that any one the 80Gb/s signal (any one among the ST1-ST16) by the output of 3rd level module can be the combination in any of full-scale input SR1-SR16, thereby can conclude that whole 1.28Tb/s cross matrix is the multicast strictly non-blocking.
The essence of multicast strict blocking-free cross array structure of the present invention is flexible Application bit cutting techniques.In existing cross matrix structure shown in Figure 2, the 2nd grade all is that 4 different bit groups after bit is cut apart are placed on respectively in 4 cross chips and intersect with 3rd level, but in multicast strict blocking-free cross array structure shown in Figure 3, just 4 different bit groups after the 2nd grade of cross matrix cut apart bit are placed on 4 cross chips respectively and intersect, and the different bit groups after the 3rd level of cross matrix then is that bit is cut apart are placed in the same cross chips intersects.
In addition, in multicast strict blocking-free cross array structure shown in Figure 3, corresponding any one 80Gb/s output signal ST1-ST16, if with VC-4 is cross grain, its intersection granule number is 512, the VC-4 time slot signal of each output can be chosen from 1024 signal particles of 3rd level input in principle, but by the 2nd grade of intersection of control, make the VC-4 of any one 3rd level output only need in the VC-4 of 2 inputs time slot signal, to choose, promptly for any one 160Gb/s signal input (i.e. 2 80Gb/s signal inputs), the module T1-T16 of 80Gb/s signal output, 3 80Gb/s signals be multiply by the principle of every line timeslot number 64 according to inputing or outputing physical cord quantity 8, form 3 item numbers and be 512 formation, be respectively:
A
1，A
2，A
3，，…，A
i，…，A
511，A
512；
B
1，B
2，B
3，…，B
i，…，A
511，B
512；
X
1，X
2，X
3，…，X
i，…，A
511，X
512；
Formation A representative is from intersecting 512 VC-4 of 80Gb/s signal of the 2nd grade of S1 or S2 input, formation B representative is from intersecting 512 VC-4 of 80Gb/s signal of the 2nd grade of S3 or S4 input, 512 VC-4 of the 80Gb/s signal of output after the 160Gb/s module of formation X representative intersection 3rd level is intersected, for any positive integer i (1≤i≤512), X
iCan only be from the A of formation A
iOr the B of formation B
iSelect in the two.
Queue definitions above having had, 1.28Tb/s the control of cross matrix becomes simple and clear, it makes the control that 3rd level intersects become very simple, do not increase simultaneously the complexity of the 2nd grade of intersection control again, be crossed to the A of formation A because the multicast strictly non-blocking characteristic of the 2nd grade of intersection both can guarantee any one VC-4 by the SR1-SR8 input
i, can guarantee that also any one VC-4 by the SR9-SR16 input is crossed to the B of formation B
i
Fig. 4 is the schematic diagram of the 1.28Tb/s multicast strict blocking-free cross array of the present invention's second case study on implementation.In Fig. 4,1.28Tb/s cross matrix structure also is divided into 3 grades.The 1st grade is input stage, and F1-F8 constitutes by module.The 1280Gb/s signal of input is divided into SR1-SR8 totally 8 groups, every group of 160Gb/s.8 groups of 160Gb/s signals enter the 1st grade module F1-F8 respectively and become two signals of broadcasting.The 2nd grade is made of four module 1-4 (hereinafter to be referred as module S1-S4).Two broadcast the 2nd grade of module S1-S4 that signal is given cross matrix by what module F1-F8 came out.Module S1 and S2 receive the output of input stage module F1-F4, and module S3 and S4 receive the output of input stage module F5-F8.Module S1-S4 has any multicast strictly non-blocking of 640Gb/s crossing, therefore any one the 160Gb/s signal in 8 160Gb/s signals being sent by module S1 and S2 can be the combination in any of input signal SR1-SR4, in like manner, any one the 160Gb/s signal in 8 160Gb/s signals being sent by module S3 and S4 can be the combination in any of input signal SR5-SR8.16 160Gb/s signals sending from module S1-S4 are received 8 module 1-8 (hereinafter to be referred as module T1-T8) of 3rd level, promptly, module S1 and S3 output 160Gb/s signal are to the module T1 and the T2 of 3rd level, and module S2 and S4 output 160Gb/s signal are to the T3 and the T4 of 3rd level.Any one 320Gb/s Cross module of 3rd level is actually by 2 160Gb/s cross chips to be formed, for its 2 160Gb/s input term signals, one of them input signal is from module S1 or S2, another input signal is from module S3 or S4, because module T1-T8 has any multicast strictly non-blocking of 320Gb/s crossing, therefore can conclude that by any one the 160Gb/s signal among 8 160Gb/s signal ST1-ST8 of 3rd level module output can be the combination in any of full-scale input SR1-SR8, thereby can conclude that whole 1.28Tb/s cross matrix is the multicast strictly non-blocking.
The multicast strict blocking-free cross array of Fig. 4 is slightly different with the multicast strict blocking-free cross array of Fig. 3, the capacity (320Gb/s) of 3rd level Cross module T1-T8 among Fig. 4 relatively among Fig. 2 the capacity (640Gb/s) of 3rd level Cross module T1-T4 just be reduced to half rather than 1/4th, but it is identical to the substantial improvements of multicast strict blocking-free cross array among Fig. 2, that is to say, can obtain the technique effect of Fig. 3 according to the case study on implementation of Fig. 4 equally.
Multicast strict blocking-free cross array according to Fig. 4, whole 1.28Tb/s cross matrix and the whole professional dish that docks with it are placed on respectively in 9 machine frames, wherein cross matrix takies 1 machine frame for the 2nd grade, the 1st grade of cross matrix, 3rd level add that whole professional dishes are placed on respectively in the professional frame of 8 160Gb/s capacity, realized that the 1.28Tb/s cross matrix intersects to the multicast strictly non-blockings of whole professional dish signals.
Fig. 6 is the detailed input and output annexation schematic diagram of the 1st 160Gb/s crossing matrix modules T1 of the 1.28Tb/s multicast strict blocking-free cross array 3rd level of the present invention's first case study on implementation.As can be seen from FIG., the input of expressing the module T1 of 3rd level among the figure is connected with the 2nd grade module S1, the output of S3, and its output is connected with the professional dish of 8 10Gb/s, and annexation and the T1 of module T2-T16 are similar, are illustrated among Fig. 3.Different with multicast strict blocking-free cross array shown in Figure 2, the 3rd level Cross module T1-T4 among Fig. 2 all is made up of the cross chips of 4 160Gb/s capacity, and 3rd level Cross module T1 only is made up of the cross chips of 1 160Gb/s capacity among Fig. 6.Module S1 and S3 respectively export 8 * 10Gb/s signal to module T1 among Fig. 6, and module T1 selection wherein 8 * 10Gb/s signal outputs to the professional dish of 8 10Gb/s.Note, the identical output of numbering must be same 10Gb/s signal in 4 cross chips of module S1 or S3, as seen from the figure, any one 10Gb/s signal by module S1 or S3 output, its 4 2.5Gb/s signals all are 4 cross chips A from the 2nd grade, B, C, D enters the same cross chips A of module T1 simultaneously, with the 1st 10Gb/s signal of S1 output is example (among the figure 4 dotted line shown in), can see that this 10Gb/s signal is respectively by 4 cross chips A of module S1, B, C, No. 1 port output of D enters 1 of module T1 cross chips A respectively, 17,33, No. 49 ports; Can also see by figure, 4 2.5Gb/s signals that output to the professional dish of any 10Gb/s are all from the different port of the same cross chips A of T1 module, for example among the figure input of the professional dish of 1#10Gb/s from 1,9,17, No. 25 port of T1 module cross chips A.As seen from Figure 6, the 10Gb/s signal only passes 1 chip in T1 arbitrarily.
Fig. 7 is the detailed annexation schematic diagram of input and output of module T1 in the 1.28Tb/s multicast strict blocking-free cross array 3rd level of the present invention's second case study on implementation.The figure shows 3rd level module T1 and the 2nd grade of module S1, S3 and 16 professional detailed annexations of coiling of 10Gb/s of the multicast strict blocking-free cross array (Fig. 4) of the present invention's second case study on implementation, the annexation and the module T1 of module T2-T8 and the 2nd grade are similar, are illustrated among Fig. 4.Module T1 is made up of the cross chips of 2 160Gb/s capacity, and S1 and S3 respectively export 16 * 10Gb/s signal to module T1 among the figure, and module T1 selection wherein 16 * 10Gb/s signal outputs to the professional dish of 16 10Gb/s.As seen from the figure, the 10Gb/s signal only passes 2 chips in T1 arbitrarily.
Cross-connect matrix provided by the present invention can be applied to the occasion that optical cross connect (OXC) equipment, synchronous digital hierarchy/Synchronous Optical Network (SDH/SONET) equipment, digital crossover connection (DXC) equipment even switch device etc. have cross-connect matrix to use.
Multicast strict blocking-free cross array of the present invention describes by case study on implementation, but the invention is not restricted to these concrete case study on implementation, and those skilled in the art can change or conversion within the spirit and scope of the present invention.
Claims (10)
1. large-capacity multicast strict blocking-free cross array structure is made up of for three grades input stage, the 2nd grade and output stage, it is characterized in that:
Input stage is made of 16 1 fen crossing matrix modules of 2, and each crossing matrix modules receives one road 80Gb/s input signal, the two two-way 80Gb/s signals of broadcasting of output;
The 2nd grade, constitute by 4 640Gb/s crossing matrix modules, each 640Gb/s crossing matrix modules receives 8 road 80Gb/s signals of input stage output, exports 8 road 80Gb/s signals;
Output stage, the crossing matrix modules that is input to 80Gb/s output by 16 160Gb/s constitutes, the 1-8 crossing matrix modules respectively receives 1 road 80Gb/s signal from the output of the 2nd grade of crossing matrix modules 1 and 3 respectively, the 9-16 crossing matrix modules respectively receives 1 road 80Gb/s signal from the output of the 2nd grade of crossing matrix modules 2 and 4 respectively, each output stage crossing matrix modules is selected output 80Gb/s signal in the 160Gb/s input signal, and each VC-4 time slot signal of output only needs to select in the VC-4 of 2 inputs time slot signal.
2. according to the large-capacity multicast strict blocking-free cross array structure of claim 1, it is characterized in that: described 640Gb/s crossing matrix modules and 160Gb/s crossing matrix modules all are strict blocking-free cross arrays.
3. according to the large-capacity multicast strict blocking-free cross array structure of claim 1 or 2, it is characterized in that:
The 2nd grade 640Gb/s crossing matrix modules 1 and 2 input are connected to the 1-8 road output of input stage, export 1-8 road 80Gb/s signal respectively;
The 2nd grade 640Gb/s crossing matrix modules 3 and 4 input are connected to the 9-16 road output of input stage, export 9-16 road 80Gb/s signal respectively.
4. according to the large-capacity multicast strict blocking-free cross array structure of claim 3, it is characterized in that:
Described input stage is made of 16 crossing matrix modules;
Described 640Gb/s crossing matrix modules is made of 4 160Gb/s cross chips;
Described 160Gb/s crossing matrix modules is made of 1 160Gb/s cross chips.
5. according to the large-capacity multicast strict blocking-free cross array structure of claim 3, it is characterized in that also comprising the professional dish of 10Gb/s, the output of each crossing matrix modules of 3rd level connects the professional dish of 8 10Gb/s respectively.
6. large-capacity multicast strict blocking-free cross array structure is made up of for three grades input stage, the 2nd grade and output stage, it is characterized in that:
Input stage is made of 81 fen crossing matrix modules of 2, and each crossing matrix modules receives one road 160Gb/s input signal, the two two-way 160Gb/s signals of broadcasting of output;
The 2nd grade, constitute by 4 640Gb/s crossing matrix modules, each 640Gb/s crossing matrix modules receives 4 road 160Gb/s signals of input stage output, exports 4 road 160Gb/s signals;
Output stage, the crossing matrix modules that is input to 160Gb/s output by 8 320Gb/s constitutes, the 1-4 crossing matrix modules respectively receives 1 road 160Gb/s signal from the output of the 2nd grade of crossing matrix modules 1 and 3 respectively, the 5-8 crossing matrix modules respectively receives 1 road 160Gb/s signal from the output of the 2nd grade of crossing matrix modules 2 and 4 respectively, each output stage crossing matrix modules is selected output 160Gb/s signal in the 320Gb/s input signal, and each VC-4 time slot signal of output only needs to select in the VC-4 of 2 inputs time slot signal.
7. according to the large-capacity multicast strict blocking-free cross array structure of claim 6, it is characterized in that described 640Gb/s crossing matrix modules and 320Gb/s crossing matrix modules all are strict blocking-free cross arrays.
8. according to the large-capacity multicast strict blocking-free cross array structure of claim 6 or 7, it is characterized in that:
The 2nd grade 640Gb/s crossing matrix modules 1 and 2 input are connected to the 1-4 road output of input stage, export 1-4 road 160Gb/s signal respectively;
The 2nd grade 640Gb/s crossing matrix modules 3 and 4 input are connected to the 5-8 road output of input stage, export 5-8 road 160Gb/s signal respectively.
9. large-capacity multicast strict blocking-free cross array structure according to Claim 8 is characterized in that:
Described input stage is made of 8 crossing matrix modules;
Described 640Gb/s crossing matrix modules is made of 4 160Gb/s cross chips;
Described 320Gb/s crossing matrix modules is made of 2 160Gb/s cross chips.
10. large-capacity multicast strict blocking-free cross array structure according to Claim 8 is characterized in that also comprising the professional dish of 10Gb/s, and the output of each crossing matrix modules of 3rd level connects the professional dish of 16 10Gb/s respectively.
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| WO2009100575A1 (en) * | 2008-02-04 | 2009-08-20 | Zte Corporation | A method and apparatus for realizing source routing in the blocked cross network |
| CN101001122B (en) * | 2006-06-22 | 2011-01-19 | 华为技术有限公司 | Method and device of unblock high-order cross expansion in SDH system |
| CN106453089A (en) * | 2016-10-17 | 2017-02-22 | 天津光电通信技术有限公司 | Large-capacity SDH signal cross-convergence system and routing algorithm based on graph theory |
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| CN108828720B (en) * | 2018-05-30 | 2020-09-15 | 中国科学院半导体研究所 | Full-switching multimode signal optical switch architecture |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101001122B (en) * | 2006-06-22 | 2011-01-19 | 华为技术有限公司 | Method and device of unblock high-order cross expansion in SDH system |
| WO2009100575A1 (en) * | 2008-02-04 | 2009-08-20 | Zte Corporation | A method and apparatus for realizing source routing in the blocked cross network |
| US8665749B2 (en) | 2008-02-04 | 2014-03-04 | Zte Corporation | Method and apparatus for realizing source routing in a blocking cross network |
| CN106453089A (en) * | 2016-10-17 | 2017-02-22 | 天津光电通信技术有限公司 | Large-capacity SDH signal cross-convergence system and routing algorithm based on graph theory |
| CN106453089B (en) * | 2016-10-17 | 2019-05-24 | 天津光电通信技术有限公司 | Large capacity SDH signal cross collecting system and routing algorithm based on graph theory |
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