CN1677826A - Semi-bridge conrol signal generating circuit and method thereof - Google Patents
Semi-bridge conrol signal generating circuit and method thereof Download PDFInfo
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- CN1677826A CN1677826A CNA2004100299151A CN200410029915A CN1677826A CN 1677826 A CN1677826 A CN 1677826A CN A2004100299151 A CNA2004100299151 A CN A2004100299151A CN 200410029915 A CN200410029915 A CN 200410029915A CN 1677826 A CN1677826 A CN 1677826A
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Abstract
Connected to primary side of a transformer, two electronic switches in use for control of turning on or off two switches convert DC power supply to AC power supply for a load to use. The signal generation circuit includes following parts: a logic unit of AND gate, a NAND gate, a circuit protection unit, a waveform generator, clock generator, soft starting up unit, a sample hold unit, first and second comparators etc. the invention is able to direct control and drive operation of diverter switch in semi bridge type circuit architecture.
Description
Technical field
The present invention relates to a kind of semibridge system control signal generation circuit and method thereof, particularly relate to a kind of control signal control its switch of can exporting and move, reach the conversion of electric power and the circuit and the method thereof of transmission signal.
Background technology
In increasingly sophisticated electronics, the computer installation, supply unit becomes more important, supply unit can be divided into linear mode (linear type) and exchanged form (switching type) two big classes, because its shortcoming of linear mode (linear type) is more, therefore, the supply unit of industrial circle production at present all uses exchanged form (switching type) to reach.
The converter circuit (Inverter Circuit) that the supply of electric power of TFT panel backlight (Power Supply) mainly uses direct current (DC) to be converted into alternating current (AC) is reached the conversion of energy and is driven the luminous of cold cathode fluorescent lamp pipe (CCFL).Known converter circuit (Inverter Circuit) is because of the difference of circuit topology, and have general the branch such as semi bridge type inversion circuit, full-bridge current circuit and push-pull type converter circuit etc., and it is for converting direct current DC to the converter circuit of alternating current AC.
Please refer to Fig. 1, drive the circuit diagram of load for known semi bridge type inversion circuit.Transformer T2 is divided into the front stage circuits 201 of primary side and the back circuit 202 of secondary side with circuit region, primary side 201 includes: a direct current power Vcc, two electronic switch Q1, Q2, a semibridge system control chip TL494, two capacitor C1, C2 and isolating transformer Tr etc., secondary side 202 includes: a load (Load).Cooperate Fig. 2, be known semibridge system control chip output control signal and AC supply voltage waveform schematic diagram.Semibridge system control chip TL494 by two follower D1, D2 output control signal D1-D2 by isolating transformer Tr in order to control the change action of Q1, two electronic switches of Q2 respectively.Two electronic switch Q1, Q2 are N slot field-effect transistor or P-channel field-effect transistor (PEFT) transistor.By the change action of these two electronic switch Q1, Q2, the electric energy that is stored in capacitor C1, C2 is sent to the primary side end points T21 of transformer T2 respectively by a commissure capacitor C 3, in order to form an AC power ac.The voltage of capacitor C1, C2 is half voltage vcc/2 of DC power supply Vcc.This AC power ac is in order to providing energy to transformer T2, and by transformer T2 with the AC power boost conversion to secondary side 202, in order to drive load (Load).
In the above-mentioned explanation, known semi bridge type inversion circuit need use isolating transformer Tr to control the change action of electronic switch Q1, Q2, can't directly drive electronic switch Q1, Q2 by semibridge system control chip TL494.And electronic switch Q1, Q2 that known semi bridge type inversion circuit uses are all the N slot field-effect transistor or are all the P-channel field-effect transistor (PEFT) transistor, therefore, known semi bridge type inversion circuit can cause energy than lossy.
Please refer again to Fig. 1, because the operating principle of semi bridge type inversion circuit is that the first switch Q1 and second switch Q2 stagger a bit of time a little, and alternately (alternately) does ON/OFF action, therefore control signal D1-D2 shown in Figure 2 need a bit of when quiet the time (dead time) cause burning of transformer T2 in order to avoid the first switch Q1 and second switch Q2 conducting simultaneously.And control signal D1-D2 needs the electricity needs according to load (Load) end, and then the change action of control break first switch Q1 and second switch Q2, in order to provide load (Load) required electric power.In addition; the working temperature situation that control signal D1-D2 need produce circuit according to various situations and the present invention of load (Load) end; situations such as for example output voltage is low excessively, output voltage is too high, fluorescent tube open circuit or temperature overheating; and then stop the change action of the first switch Q1 and second switch Q2, to reach the function of circuit protection.
Summary of the invention
Technical problem to be solved by this invention provides a kind of semibridge system control signal generation circuit and method thereof, solves the problem that prior art can't directly be driven electronic switch by the semibridge system control chip.
For achieving the above object, the invention provides a kind of semibridge system control signal generation circuit, its characteristics are, be connected to a side of a transformer by two electronic switches, in order to control the keying of two electronic switches, with a direct current power source conversion is an AC power, uses so that a load to be provided, and includes:
One with the gate logic unit, in order to work and logical operation and export one first control signal;
One NAND gate logical block is in order to do the NAND Logic computing and to export one second control signal;
One circuit protection unit is connected in this and gate logic unit and this NAND gate logical block, and is connected to the secondary side of this transformer by a feedback circuit, in order to receive a feedback signal;
One waveform generator is in order to produce a sawtooth waveform signal;
One clock generator is connected in this waveform generator and is somebody's turn to do and the gate logic unit, and is connected to this NAND gate logical block by a not gate, and produces a clock signal according to this sawtooth waveform signal;
One soft start-up unit is connected in this clock generator, receives this clock signal, and exports a starting-up signal and a count signal, in order to carry out boot action;
One sampling keeping unit is connected to this feedback circuit by an error amplifier, obtains a voltage feedback signal, and exports a Voltage Feedback inhibit signal;
One first comparator is connected in this soft start-up unit and this waveform generator, and relatively this sawtooth waveform signal and this count signal are exported one first comparison signal;
One or the gate logic unit, be connected in this soft start-up unit, this first comparator, should and gate logic unit and this NAND gate logical block, with this starting-up signal and this first comparison signal work or logical operation;
One second comparator is connected in this sampling keeping unit, this waveform generator, is somebody's turn to do and gate logic unit and this NAND gate logical block, and relatively this sawtooth waveform signal and this Voltage Feedback inhibit signal are exported one second comparison signal; And
One control unit when quiet, be connected in this waveform generator, should and gate logic unit and this NAND gate logical block, receive this sawtooth waveform signal, export one and adjust signal when quiet.
Above-mentioned semibridge system control signal generation circuit, its characteristics are, also comprise a constant-current source, switch switch by one and are connected to this error amplifier, in order to a fixing electric current to be provided.
Above-mentioned semibridge system control signal generation circuit, its characteristics are, comprise that also a voltage-adjusting unit connects this DC power supply, and provide circuit working required electric power.
Above-mentioned semibridge system control signal generation circuit, its characteristics are that this soft start-up unit includes: a counter, in order to the counting available machine time; One digital/analog converter is exported the available machine time with analog form.
Above-mentioned semibridge system control signal generation circuit, its characteristics are that this circuit protection unit includes: a under-voltage protection circuit, according to this feedback signal, in order to do the under-voltage protection of circuit; One temperature protection circuit is according to this feedback signal, in order to do the overtemperature protection of circuit; One excess voltage protection is according to this feedback signal, in order to make the overvoltage protection of circuit; One fluorescent tube open loop protection circuit is according to this feedback signal, in order to do the protection of load open circuit.
Above-mentioned semibridge system control signal generation circuit, its characteristics are that this excess voltage protection is controlled the keying of this diverter switch.
Above-mentioned semibridge system control signal generation circuit, its characteristics are that this load is a cold cathode fluorescent lamp pipe.
In order better to realize purpose of the present invention, the present invention also provides a kind of semibridge system control signal production method, and its characteristics are, include:
Produce a sawtooth waveform signal, this sawtooth waveform signal is produced by a waveform generator;
Produce a clock signal, this clock signal is produced according to this sawtooth waveform signal by a clock generator;
Produce a reverse clock signal, this reverse clock signal produces by a not gate;
Produce one and adjust signal when quiet, adjust when this is quiet signal by one control unit when quiet, produce according to this sawtooth waveform signal;
Sampling also keeps a voltage feedback signal, and this voltage feedback signal is connected to a feedback circuit by an error amplifier and is produced by a sampling keeping unit;
Relatively this voltage feedback signal and this sawtooth waveform signal are compared by one second comparator, and export one second comparison signal;
Count this clock signal, and export a count signal and a starting-up signal, finish by a soft start-up unit;
Relatively this count signal and this sawtooth waveform signal are compared by one first comparator, and export one first comparison signal;
Generation one or gate signal are somebody's turn to do or gate signal is carried out by this starting-up signal and this first comparison signal or logical operation obtains;
Produce one first control signal, this first control signal adjust when quiet by this signal, this second comparison signal, this clock signal and should or gate signal carry out with logical operation and obtain; And
Produce one second control signal, this second control signal adjust when quiet by this signal, this second comparison signal, this reverse clock signal and should or gate signal carry out the NAND Logic computing and obtain.
Technique effect of the present invention is:
1) semibridge system control signal generation circuit provided by the invention, two control signals can be provided, and control the change action of two electronic switches of semi bridge type inversion circuit respectively, make DC power supply be converted into AC power, and provide electric power to use to load by transformer.
2) the present invention is connected to a side of a transformer by two electronic switches, in order to controlling the keying of two electronic switches, and a direct current power supply is switched to the side that an AC power is sent to transformer.Simultaneously, the leakage inductance and the electric capacity (C1, C2, C5) that utilize transformer to produce form resonant network, in order to produce a string ripple to provide the load action required electric power.In addition, utilize the load condition of feedback circuit acquisition transformer secondary side, and by after the processing of the present invention, output produces control signal, to reach the electric power adjustment and the protection of load end.
3) the present invention can utilize a power protection unit; obtain the various situations of transformer secondary lateral load (Load) end and the working temperature situation that the present invention produces circuit by feedback circuit; situations such as for example output voltage is low excessively, output voltage is too high, fluorescent tube open circuit or temperature overheating; and then stop the change action of two electronic switches, to reach the function of circuit protection.
4) the present invention utilizes control unit when quiet to obtain fixing time (dead time) when quiet, causes transformer short-circuit to burn in order to avoid the conducting simultaneously of two electronic switches.And the present invention can be according to the electricity needs of load (Load) end, and then the change action of control break two electronic switches, in order to provide load (Load) required electric power.Simultaneously, the switching that the present invention utilizes a soft start-up unit to carry out two electronic switches activates, excessive impulse current and voltage when activating in order to reduce, and cause burning of two electronic switches, and the life-span of prolonging lamp tube.
5) the present invention also passes through the voltage feedback signal of a sampling keeping unit in order to reception load (Load) end, and carries out the maintenance action of voltage feedback signal in each cycle clock signal, and then reduces the known energy imbalance that exports the signal of load to.
Further describe specific embodiments of the invention below in conjunction with accompanying drawing.
Description of drawings
Fig. 1 is the circuit diagram that known semi bridge type inversion circuit drives load;
Fig. 2 is known semibridge system control chip output control signal and load end output voltage waveforms schematic diagram;
Fig. 3 is the circuit diagram of the driving load of semibridge system control signal generation circuit of the present invention;
Fig. 4 is the circuit diagram of semibridge system control signal generation circuit of the present invention; And
Fig. 5 is the internal signal waveforms schematic diagram of semibridge system control signal generation circuit of the present invention;
Wherein, description of reference numerals is as follows:
201-front stage circuits 202-late-class circuit T2-transformer
1-semibridge system control signal generation circuit
The 2-feedback circuit
The 4-power-supply unit
The 5-load
The soft start-up unit of 102-
Control unit when 104-is quiet
The 106-clock generator
The 108-sampling keeping unit
The 110-waveform generator
112-and gate logic unit
114-NAND gate logical block
116-first comparator
118-second comparator
120-or gate logic unit
The 122-not gate
The 124-circuit protection unit
The 126-error amplifier
The 128-constant-current source
The 130-voltage-adjusting unit
DRV1-first output
DRV2-second output
The FB-pressure feedback port
The CLAMP-test side
Embodiment
Please refer to Fig. 3, drive the circuit diagram of load for semibridge system control signal generation circuit of the present invention.Wherein semibridge system control signal generation circuit 1 is connected to the side of a transformer T1 by two electronic switch Q3, Q4, in order to control the keying of two electronic switch Q3, Q4.Semibridge system control signal generation circuit 1 also is connected to the secondary side of transformer T1 by a feedback circuit 2, in order to obtain a feedback signal of load 5.Be connected in a power-supply unit 4 simultaneously in order to obtain a working power Vdd (not indicating).Semibridge system control signal generation circuit 1 is exported two control signals by the first output DRV1 and the second output DRV2, and control the keying of two electronic switch Q3, Q4 respectively, be used for the direct current power supply DC that power-supply unit 4 provides is converted into an AC power AC, use so that load to be provided.In the above-mentioned explanation, this load is a cold cathode fluorescent lamp pipe (CCFL).And, electronic switch Q3 is the P-channel field-effect transistor (PEFT) transistor, electronic switch Q4 is the N slot field-effect transistor, it can improve known semi bridge type inversion circuit, because electronic switch Q3, Q4 are all the N slot field-effect transistor or are all energy that the P-channel field-effect transistor (PEFT) transistor caused than lossy.
Cooperate Fig. 3, please refer to Fig. 4, be the circuit diagram of semibridge system control signal generation circuit of the present invention.Semibridge system control signal generation circuit 1 of the present invention, be connected to the control end of electronic switch Q3 by one first output DRV1, be connected to the control end of electronic switch Q4 by one second output DRV2, an one pressure feedback port FB and a test side CLAMP are connected to feedback circuit 2 simultaneously, include: one with gate logic unit 112, in order to do and logical operation; One NAND gate logical block 114 is in order to do the NAND Logic computing; One circuit protection unit 124 is connected in this and gate logic unit 112 NAND gate logical blocks 114, and it utilizes test side CLAMP to be connected to the feedback circuit 2 of Fig. 3, and is connected to the secondary side of this transformer T1 by feedback circuit 2; One waveform generator 110; One clock generator 106 is connected in waveform generator 110 and is somebody's turn to do and gate logic unit 112, and is connected to this NAND gate logical block 114 by a not gate 122; One soft start-up unit 102 is connected in this clock generator 106, in order to carry out boot action; One sampling keeping unit 108 is connected to this feedback circuit 2 via pressure feedback port FB again by an error amplifier 126; One first comparator 116 is connected in this soft start-up unit 102 and this waveform generator 110; One or gate logic unit 120, be connected in this soft start-up unit 102, this first comparator 116, should and gate logic unit 112 and this NAND gate logical block 114, be to carry out or logical operation (OR); One second comparator 118 is connected in this sampling keeping unit 108, this waveform generator 110, is somebody's turn to do and gate logic unit 112 and this NAND gate logical block 114; And a control unit 104 when quiet, be connected in this waveform generator 110, this first with gate logic unit 112 and this NAND gate logical block 114.
In the above-mentioned explanation, semibridge system control signal generation circuit 1 of the present invention also includes a constant-current source 128, switches switch SW by one and is connected to this error amplifier 126, in order to a fixing electric current to be provided.Simultaneously, also include a voltage-adjusting unit 130, be connected in power-supply unit 4, obtain a direct current power supply, in order to provide 1 work of semibridge system control signal generation circuit required electric power VCC by a working power end VDD.
In the above-mentioned explanation, the circuit protection unit 124 of semibridge system control signal generation circuit 1 of the present invention includes: a under-voltage protection circuit, a temperature protection circuit, an excess voltage protection and a fluorescent tube open loop protection circuit etc.Simultaneously, the soft start-up unit 102 of semibridge system control signal generation circuit 1 of the present invention includes: a counter and a digital/analog converter.
Please refer to Fig. 5, be the internal signal waveforms schematic diagram of semibridge system control signal generation circuit of the present invention.Wherein transverse axis is time (t) axle, and the longitudinal axis is a voltage (v) axle.As shown in Figure 5, the internal signal waveforms of semibridge system control signal generation circuit of the present invention includes: a voltage feedback signal a, a Voltage Feedback inhibit signal b, a sawtooth waveform signal c, one adjust signal d, one second comparison signal e, a count signal f, one or gate signal g, a clock signal h, one first control signal i, one second control note j, starting-up signal k and one first comparison signal m when quiet.
Cooperate Fig. 5, please refer to Fig. 4, semibridge system control signal generation circuit 1 of the present invention utilizes sampling keeping unit 108 by error amplifier 126, returns end FB via voltage again and is connected to feedback circuit shown in Figure 32, and then obtain feedback signal.This feedback signal is voltage feedback signal a.Sampling keeping unit 108 keeps operating stably with voltage feedback signal a, makes it no longer to float, and output voltage feedback inhibit signal b is to second comparator 118 simultaneously.Sampling keeping unit 108, according to the clock signal h in each cycle, in order to carrying out the maintenance operating stably of voltage feedback signal a, and then output voltage feedback inhibit signal b.Waveform generator 110 output sawtooth waveform signal c, and be sent to clock generator 106, get clock generator 106 output clocking h.Sawtooth waveform signal c is sent to control unit 104 when quiet simultaneously, makes when quiet control unit 104 outputs produce and adjusts clock d when quiet.Sawtooth waveform signal c also is sent to second comparator, 118, the second comparators 118 and compares sawtooth waveform signal c and Voltage Feedback inhibit signal b simultaneously, and then exports the second comparison signal e.
The composite Fig. 5 that closes please refer to Fig. 4, the soft start-up unit 102 receive clock signal h of semibridge system control signal generation circuit 1 of the present invention, and utilize inner counter according to clock signal h, in order to count the default circuit available machine time.Digital signal behind the counting is handled via the digital/analog converter of soft start-up unit 102 inside, makes digital signal convert analog signal output to, and this analog signal is count signal f.Simultaneously, when the soft 102 default circuit available machine times of start-up unit arrived, the starting-up signal k of soft start-up unit 102 outputs changed into high potential by electronegative potential.
The composite Fig. 5 that closes please refer to Fig. 4, and first comparator 116 of semibridge system control signal generation circuit 1 of the present invention receives and relatively this sawtooth waveform signal c and count signal f, and then exports the first comparison signal m and be sent to or gate logic unit 120.Or gate logic unit 120 receives the starting-up signal k and the first comparison signal m simultaneously, and output or gate signal g.
The composite Fig. 5 that closes; please refer to Fig. 4; first of semibridge system control signal generation circuit 1 of the present invention is adjusted the guard signal that signal d and circuit protection unit 124 transmit with gate logic unit 112 receive clock signal h or gate signal g, the second comparison signal e, when quiet; and with it work " with " (AND) logical operation, in order to export the first control signal i.Simultaneously, NAND gate logical block 114 receives or gate signal g, the second comparison signal e, adjust the guard signal that signal d and circuit protection unit 124 transmit when quiet, and by not gate 122 receive clock signal h.NAND gate logical block 114 is done NAND (NAND) logical operation with the signal of above-mentioned reception, in order to export the second control signal j.
Cooperate Fig. 4, please refer to Fig. 5, when time t0-t1, sawtooth waveform signal c respectively when quiet control unit 104 adjust signal d and clock signal h when quiet with clock generator 106 outputs, the time is td when adjusting signal d quiet when quiet, and at this moment, clock signal h is a high potential.Because Voltage Feedback inhibit signal b is greater than sawtooth waveform signal c, the second comparison signal e of second comparator, 118 outputs is a high potential.Also have, sawtooth waveform signal c is greater than count signal f, so the first comparison signal m of first comparator, 116 outputs is an electronegative potential.Simultaneously, because default available machine time no show still, so starting-up signal k is an electronegative potential.Because the starting-up signal k and the first comparison signal m are all electronegative potential, so gate logic unit 120 output or gate signal g be electronegative potential, therefore, when time t0-t1, the first control signal i of AND 112 outputs is an electronegative potential, and the second control signal j of NAND gate logical circuit 114 outputs is a high potential.
Cooperate Fig. 4, please refer to Fig. 5, in time t1-t2, at this moment, clock signal h is an electronegative potential, and to adjust signal d when quiet be electronegative potential.Identical when the control signal of circuit output and time t0-t1, that is, the first control note i of AND 112 outputs is an electronegative potential, and the second control signal j that NAND gate logical circuit 114 is exported is a high potential.
Cooperate Fig. 4, please refer to Fig. 5, in time t2-t3, clock signal h still be an electronegative potential, and adjustment signal d is a high potential when quiet.Because Voltage Feedback inhibit signal b is still greater than sawtooth waveform signal c, so the second comparator e is a high potential.And sawtooth waveform signal c is less than count signal f, so the first comparison signal m of first comparator, 116 outputs is a high potential.Simultaneously, because default available machine time no show still, so starting-up signal k is an electronegative potential.Because the starting-up signal k and the first comparison signal m are all high potential, thus gate logic unit 120 output or gate signal g be high potential.Therefore, when time t2-t3, the first control signal i of AND 112 outputs still is an electronegative potential, and the second control signal j of NAND gate logical circuit 114 outputs is an electronegative potential.
Cooperate Fig. 4, please refer to Fig. 5, in time t3-t4, identical when the control signal of circuit output this moment and time t0-t1, that is, the first control note i of AND 112 outputs is an electronegative potential, and the second control signal j of NAND gate logical circuit 114 outputs is a high potential.
Cooperate Fig. 4, please refer to Fig. 5, in time t4-t5, at this moment, clock signal h is a high potential, and to adjust signal d when quiet be high potential.Because Voltage Feedback inhibit signal b is still greater than sawtooth waveform signal c, the second comparison signal e of second comparator, 118 outputs is a high potential.And sawtooth waveform signal c is less than count signal f, so the first comparison signal m of first comparator, 116 outputs is a high potential.Simultaneously, because default available machine time no show still, so starting-up signal k is an electronegative potential.Because first remembers that relatively m is a high potential, thus gate logic unit 120 output or gate signal g be high potential.Therefore when time t4-t5, the second control signal j of first control signal I of AND 112 outputs and 114 outputs of NAND gate logical circuit is all high potential.
Cooperate Fig. 4, please refer to Fig. 5, in time t5-t6, identical when the control signal of circuit output this moment and time t0-t1, that is, the first control signal i of AND 112 outputs is an electronegative potential, and the second control signal j of NAND gate logical circuit 114 outputs is a high potential.
Cooperate Fig. 4, please refer to Fig. 5, in time t6-t7, clock signal h is an electronegative potential, and to adjust signal d when quiet be high potential.Because Voltage Feedback inhibit signal b is greater than sawtooth waveform signal c, the second comparison signal e of second comparator, 118 outputs is a high potential.And sawtooth waveform signal c is less than count signal f, so the first comparison signal m of first comparator, 116 outputs is a high potential.Simultaneously, because default available machine time no show still, so starting-up signal k is an electronegative potential.Because the first comparison signal m is a high potential, thus gate logic unit 120 output or gate signal g be high potential.Therefore, when time t6-t7, the first control signal i of AND 112 outputs is an electronegative potential, and the second control signal j of NAND gate logical circuit 114 outputs is an electronegative potential.
Cooperate Fig. 4, please refer to Fig. 5, in time t7-t8, identical when the control signal of circuit output this moment and time t0-t1, that is, the first control signal i of AND 112 outputs is an electronegative potential, and the second control signal j of NAND gate logical circuit 114 outputs is a high potential.
Cooperating Fig. 4, please refer to Fig. 5, is the available machine time of circuit in time t0-t8.After time t8, the first control signal i of AND 112 and NAND gate logical circuit 114 outputs and the second control signal j can be subjected to clock signal h, when quiet adjustment signal d and the second comparison signal e influence and change.
In the above-mentioned explanation, when time t8, circuit arrives the default available machine time, at this moment, starting-up signal k rises to high potential by electronegative potential, therefore, gate logic unit 120 output or gate signal g be high potential, so the first control signal i of circuit after start, adjust by clock signal h, when quiet the signal d and the second comparison signal e do " with " logical operation obtains.The second control signal j adjusts the signal d and the second comparison signal e and does NAND (NAND) logical operation and obtain after start by reverse clock signal h, when quiet.
Cooperate Fig. 4, please refer to Fig. 5, circuit protection unit 124 detects the working condition of load 5 by the circuit 2 of awarding shown in Figure 3, when brownout, overtension or the fluorescent tube of load 5 can't be lighted and when opening a way, circuit protection unit 124 can begin action.Circuit protection unit 124 includes: under-voltage protection circuit, temperature protection circuit, excess voltage protection and fluorescent tube open loop protection circuit; obtain a feedback signal by feedback circuit 2; and export a decapacitation signal and be sent to and gate logic unit 112 and NAND gate logical block 114; make the first control signal i and the second control signal j of circuit output be able to decapacitation, and stop action.
In the above-mentioned explanation, when load 5 overvoltage, excess voltage protection control its switch SW moves conducting (ON), makes constant-current source 128 fixing electric currents can flow into a resistance (indicating), and then obtains a voltage also higher than reference voltage Vr.At this moment, the voltage feedback signal a of error amplifier 126 outputs drops to electronegative potential.Therefore Voltage Feedback inhibit signal b is electronegative potential simultaneously; and the second comparison signal e of second comparator, 118 outputs is an electronegative potential; and then make that the first control signal i and the second control signal j that export with gate logic unit 112 and NAND gate logical block 114 are electronegative potential decapacitation state, and reach the overvoltage protection of load 5.
As described above, after having served as voltage failure and removing, excess voltage protection control its switch SW opens a way (OFF), and this moment, circuit recovered normal operating state.
Next a kind of semibridge system control signal production method provided by the invention is described; At first, produce a sawtooth waveform signal, it is obtained by a waveform generator; Then, export a clock signal,, obtain according to this sawtooth waveform signal by a clock generator; Then, produce a reverse clock signal, it is obtained by a not gate by a clock signal; Simultaneously, export one and adjust signal when quiet, it is control unit when quiet by one, obtains according to this sawtooth waveform signal; Moreover, to take a sample and keep a voltage feedback signal, it is connected to a feedback circuit by a sampling keeping unit by an error amplifier and obtains; Then, relatively this voltage feedback signal and this sawtooth waveform signal, it is finished by one second comparator, and exports one second comparison signal; Simultaneously, count this clock signal, and export a count signal and a starting-up signal, it is finished by a soft start-up unit; Then, relatively this count signal and this sawtooth waveform signal, it is carried out by one first comparator, and exports one first comparison signal, again after, produce one or gate signal, it is by this starting-up signal and execution of this first comparison signal or (OR) logical operation; At last, export one first control signal, its adjust when quiet by this signal, this second comparison signal, this clock signal and should or gate signal carry out and (AND) logical operation; At last, export one second control signal, its adjust when quiet by this signal, this second comparison signal, this reverse clock signal and should or gate signal carry out and non-(NAND) logical operation.
In sum, a kind of semibridge system control signal generation circuit provided by the invention, it can provide two control signals, and controls the change action of two electronic switches of semi bridge type inversion circuit respectively.Simultaneously; the present invention can utilize the power protection unit; obtain the various situations of Circuit Fault on Secondary Transformer load end and the working temperature situation of generation circuit of the present invention by feedback circuit; situations such as for example output voltage is low excessively, output voltage is too high, fluorescent tube open circuit or temperature overheating; and then stop the change action of two electronic switches, to reach the function of circuit protection.
In addition, the present invention utilizes control unit when quiet to obtain fixing time (dead time) when quiet, causes transformer short-circuit to burn in order to avoid the conducting simultaneously of two electronic switches.And the present invention can be according to the electricity needs of load end, and then the change action of control break two electronic switches, in order to provide load required electric power.Simultaneously, the present invention utilizes soft start-up unit to activate in order to the switching of carrying out two electronic switches, and then reduces impulse current and voltage excessive when activating, and causes burning of electronic switch, and the life-span of prolonging lamp tube.
Simultaneously, the voltage feedback signal that the present invention also holds in order to reception load (Load) by sampling keeping unit, and in the maintenance action of period 1 clock signal execution voltage feedback signal, and then improve the known signal energy imbalance that exports load to.And improve in the known semi bridge type inversion circuit, because two electronic switches are all the N slot field-effect transistor or are all energy that the P-channel field-effect transistor (PEFT) transistor the caused problem than lossy.
The above is preferred embodiment of the present invention only, is not to be used for limiting practical range of the present invention; Every according to equivalence variation and modification that the present invention did, all contained by claim of the present invention.
Claims (8)
1, a kind of semibridge system control signal generation circuit is characterized in that, is connected to a side of a transformer by two electronic switches, in order to control the keying of two electronic switches, is an AC power with a direct current power source conversion, uses so that a load to be provided, and includes:
One with the gate logic unit, in order to work and logical operation and export one first control signal;
One NAND gate logical block is in order to do the NAND Logic computing and to export one second control signal;
One circuit protection unit is connected in this and gate logic unit and this NAND gate logical block, and is connected to the secondary side of this transformer by a feedback circuit, in order to receive a feedback signal;
One waveform generator is in order to produce a sawtooth waveform signal;
One clock generator is connected in this waveform generator and is somebody's turn to do and the gate logic unit, and is connected to this NAND gate logical block by a not gate, and produces a clock signal according to this sawtooth waveform signal;
One soft start-up unit is connected in this clock generator, receives this clock signal, and exports a starting-up signal and a count signal, in order to carry out boot action;
One sampling keeping unit is connected to this feedback circuit by an error amplifier, obtains a voltage feedback signal, and exports a Voltage Feedback inhibit signal;
One first comparator is connected in this soft start-up unit and this waveform generator, and relatively this sawtooth waveform signal and this count signal are exported one first comparison signal;
One or the gate logic unit, be connected in this soft start-up unit, this first comparator, should and gate logic unit and this NAND gate logical block, with this starting-up signal and this first comparison signal work or logical operation;
One second comparator is connected in this sampling keeping unit, this waveform generator, is somebody's turn to do and gate logic unit and this NAND gate logical block, and relatively this sawtooth waveform signal and this Voltage Feedback inhibit signal are exported one second comparison signal; And
One control unit when quiet, be connected in this waveform generator, should and gate logic unit and this NAND gate logical block, receive this sawtooth waveform signal, export one and adjust signal when quiet.
2, semibridge system control signal generation circuit according to claim 1 is characterized in that, also comprises a constant-current source, switches switch by one and is connected to this error amplifier, in order to a fixing electric current to be provided.
3, semibridge system control signal generation circuit according to claim 1 is characterized in that, comprises that also a voltage-adjusting unit connects this DC power supply, and provides circuit working required electric power.
4, semibridge system control signal generation circuit according to claim 1 is characterized in that, this soft start-up unit includes:
One counter is in order to the counting available machine time; And
One digital/analog converter is exported the available machine time with analog form.
5, semibridge system control signal generation circuit according to claim 1 is characterized in that, this circuit protection unit includes:
One under-voltage protection circuit is according to this feedback signal, in order to do the under-voltage protection of circuit;
One temperature protection circuit is according to this feedback signal, in order to do the overtemperature protection of circuit;
One excess voltage protection is according to this feedback signal, in order to make the overvoltage protection of circuit; And
One fluorescent tube open loop protection circuit is according to this feedback signal, in order to do the protection of load open circuit.
6, semibridge system control signal generation circuit according to claim 5 is characterized in that, this excess voltage protection is controlled the keying of this diverter switch.
7, semibridge system control signal generation circuit according to claim 1 is characterized in that, this load is a cold cathode fluorescent lamp pipe.
8, a kind of semibridge system control signal production method is characterized in that, includes:
Produce a sawtooth waveform signal, this sawtooth waveform signal is produced by a waveform generator;
Produce a clock signal, this clock signal is produced according to this sawtooth waveform signal by a clock generator;
Produce a reverse clock signal, this reverse clock signal produces by a not gate;
Produce one and adjust signal when quiet, adjust when this is quiet signal by one control unit when quiet, produce according to this sawtooth waveform signal;
Sampling also keeps a voltage feedback signal, and this voltage feedback signal is connected to a feedback circuit by an error amplifier and is produced by a sampling keeping unit;
Relatively this voltage feedback signal and this sawtooth waveform signal are compared by one second comparator, and export one second comparison signal;
Count this clock signal, and export a count signal and a starting-up signal, finish by a soft start-up unit;
Relatively this count signal and this sawtooth waveform signal are compared by one first comparator, and export one first comparison signal;
Generation one or gate signal are somebody's turn to do or gate signal is carried out by this starting-up signal and this first comparison signal or logical operation obtains;
Produce one first control signal, this first control signal adjust when quiet by this signal, this second comparison signal, this clock signal and should or gate signal carry out with logical operation and obtain; And
Produce one second control signal, this second control signal adjust when quiet by this signal, this second comparison signal, this reverse clock signal and should or gate signal carry out the NAND Logic computing and obtain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100299151A CN100377488C (en) | 2004-03-29 | 2004-03-29 | Semi-bridge conrol signal generating circuit and method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100299151A CN100377488C (en) | 2004-03-29 | 2004-03-29 | Semi-bridge conrol signal generating circuit and method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1677826A true CN1677826A (en) | 2005-10-05 |
| CN100377488C CN100377488C (en) | 2008-03-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100299151A Expired - Fee Related CN100377488C (en) | 2004-03-29 | 2004-03-29 | Semi-bridge conrol signal generating circuit and method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100377488C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106877642A (en) * | 2017-03-09 | 2017-06-20 | 中国人民解放军海军航空工程学院 | A kind of full-bridge phase-shift type Switching Power Supply output control system and method |
| CN109935214A (en) * | 2019-04-24 | 2019-06-25 | 合肥惠科金扬科技有限公司 | A kind of backlight drive circuit and backlight drive device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3873903A (en) * | 1974-02-15 | 1975-03-25 | Ncr Co | Volt-second balancing means for a high frequency switching power supply |
| IT1074198B (en) * | 1976-12-23 | 1985-04-17 | Sits Soc It Telecom Siemens | TRANSISTORIZED CENTRAL SOCKET INVERTER |
| CN2691167Y (en) * | 2004-03-29 | 2005-04-06 | 尼克森微电子股份有限公司 | Semi-briage type control signal producing circuit |
-
2004
- 2004-03-29 CN CNB2004100299151A patent/CN100377488C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106877642A (en) * | 2017-03-09 | 2017-06-20 | 中国人民解放军海军航空工程学院 | A kind of full-bridge phase-shift type Switching Power Supply output control system and method |
| CN109935214A (en) * | 2019-04-24 | 2019-06-25 | 合肥惠科金扬科技有限公司 | A kind of backlight drive circuit and backlight drive device |
| CN109935214B (en) * | 2019-04-24 | 2023-10-20 | 合肥惠科金扬科技有限公司 | Backlight driving circuit and backlight driving device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100377488C (en) | 2008-03-26 |
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