CN1664802A - Large-scale parallel system oriented programmed interruption control method - Google Patents
Large-scale parallel system oriented programmed interruption control method Download PDFInfo
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- CN1664802A CN1664802A CN 200510031391 CN200510031391A CN1664802A CN 1664802 A CN1664802 A CN 1664802A CN 200510031391 CN200510031391 CN 200510031391 CN 200510031391 A CN200510031391 A CN 200510031391A CN 1664802 A CN1664802 A CN 1664802A
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Abstract
This invention discloses a program-controlled interrupt controlling method for large scale parallel system to solve the problem of interrupt route among nodes in large scale parallel system composed by several SMP nodes. The technology project is characterized by the followings: designing a NC and an interrupt control-manage module formed by interrupt gathering module, sending module and register block module, with the control-manage module remotely transferring interrupt of local node to other nodes, receiving remote node's interrupt and gathering the local one and remote one; extending content of RTE in IOAPIC to accomplish location of processor for sending interrupt; allocating interrupt register block and RTE to remotely send interrupt. It realizes the remote transfer of local interrupts and local and remote interrupts' gathering delivery.
Description
Technical field
The present invention relates to the interrupt control method of computer realm, the interrupt control method in the especially extensive multiprocessor computer system.
Background technology
At present, Advanced Programmable Interrupt Controllers APICs) and SAPIC (Streamlined Advanced Programmable Interrupt Controller: interrupt system structure streamlined Advanced Programmable Interrupt Controllers APICs) major transformation has taken place in the interrupt system structure of high-performance computer, interrupts developing into APIC (Advanced Programmable Interrupt Controller: by traditional 8259.
APIC structure and SAPIC similar are introduced SAPIC here.(Symmetric MultipleProcessor: symmetric multiprocessor) in the system, SAPIC interrupt system structure is made of processor local SAPIC, IO APIC, interrupts by these interruptable controller coordinated managements at SMP.Wherein, the local SAPIC in the processor is responsible for queuing and shielding is interrupted, sent and receives IPI (Interprocessor Interrupt: interrupt between processor) message, receives external unit interrupt message from IO APIC, manages local interrupt source.IO APIC provides some interrupt pin, and IO equipment reports to IOAPIC by these pins with interruption.A special interrupt redirection table is arranged among the IO APIC, and interrupt redirection table is made of a plurality of interrupt redirection list items (RTE), and the corresponding interrupt pin of each RTE is used to be provided with the interrupt vector, target processor of this interrupt pin correspondence etc.IO APIC accepts the look-at-me of interrupt pin, according to the RTE configuration, convert look-at-me to corresponding interruption message, IO APIC is by the IO bus then, to interrupt message with the form of the bus transaction form of memory write transaction (for example, with) and pass to bridge controller.Bridge controller will interrupt message and convert interruption affairs on the system front end bus to, send to processor.
Because traditional APIC structure and SAPIC structure is primarily aimed at smp system, it only supports I/O equipment hardware interrupts to be mail to one of a plurality of processors on the system front end bus.For the massively parallel system of forming by a plurality of SMP nodes (each SMP node is a smp system), this hardware interrupts route scope is confined to this SMP node: interruption can only be routed to the some processors in this node, can not be routed to the processor of other nodes.
Summary of the invention
The technical problem to be solved in the present invention is to interrupt the problem that the route scope is confined to local SMP inter-node at the IO APIC in the massively parallel system of being made up of a plurality of SMP nodes, proposes a kind of program-controlled interrupt control method towards massively parallel system.
Technical scheme of the present invention is: in the massively parallel system that is made of a plurality of SMP nodes, at each node, design a node controller NC, interrupt control administration module of design in node controller NC, realize that by the interrupt control administration module this node interrupts the long-range forwarding to other node, and this node is to from the interruption of Remote Node RN and the reception that gathers of local node interruption; The interrupt control administration module is formed by interrupting summarizing module, interruption sending module and interrupt register pack module; The content that expands IO APIC interrupt redirection list item RTE simultaneously realizes the program-controlled transmission of interruption to realize interrupting sending the location of purpose processor by interrupt register group in the configure interrupt control and management module and the RTE among the IO APIC.
Node controller NC is positioned at the center of SMP node, and processor connects main memory, IO equipment and system interconnection network by NC.NC realizes processor interface PI, memory interface MI, IO bus interface and network interface NI.PI realizes the system front end bus interface, and NC and processor are by the system front end bus exchanging data; NC uses MI interface and main memory to carry out bidirectional data exchange; NC uses IO bus interface and IO equipment to carry out bidirectional data exchange; NC uses NI interface and system interconnect network to communicate.
The interrupt control administration module is formed by interrupting summarizing module, interruption sending module and interrupt register pack module.
Interrupt summarizing module and interrupt producing logic by NMI, PI interrupts producing logic, MI interrupts producing logic, NI interrupts producing logic, descriptor is finished and is interrupted producing logic, the MP non-NULL interrupts producing logic, the local wrong logic of interrupting producing, the local message receive logic of interrupting, the local message that interrupts produces logic, long-range interruption message receive logic, long-range interruption message produces logic, interrupt request gathers the generation logic and forms, be responsible for receiving level look-at-me from each functional unit of NC inside, from the local interrupt request message of local node with from the long-range interrupt request message of Remote Node RN, through the corresponding generation logic of interrupting, they are gathered, convert internal system to and interrupt message format.Interrupt the look-at-me of the input of summarizing module from different interrupt sources generations in the total system, these interrupt sources comprise:
1) the local interruption: from the interruption of local IO equipment and the interruption of inner each functional module of NC.
A) NMI interrupts: maskable does not interrupt, and is level signal;
B) PI interrupts: from the interruption of NC processor interface, be level signal;
C) MI interrupts: from the interruption of NC memory module, be level signal;
D) NI interrupts: from the interruption of NC Network Interface Module, be level signal;
The message transmission), BLT (piece transmission) interrupts, and is level signal e) descriptor is finished interruption: MP (Message Passing:;
F) the MP non-NULL interrupts: message is transmitted non-NULL and is interrupted, and is level signal;
G) error interrupt signal of inner each functional unit generation of local error interrupt signal: NC is level signal;
H) local interrupt request message: interrupt from the interruption of this node IO equipment, local IPI;
2) long-range interruption message: from the interruption of long-range other nodes.
NMI interrupts being input to NMI and interrupts producing logic, is interrupted producing the interrupt request singal that logical transition becomes processor identification by NMI, is directly connected to the interrupt pin of processor;
PI interrupts being input to PI and interrupts producing logic, is interrupted producing the interrupt request singal that logical transition becomes processor identification by PI, is directly connected to the interrupt pin of processor;
MI interruption input is connected to MI and interrupts producing logic, outputs to interrupt request by MI interruption generation logic again and gathers the generation logic;
NI interrupts being input to NI and interrupts producing logic, outputs to interrupt request by NI interruption generation logic again and gathers the generation logic;
Descriptor is finished the interruption that interruption, MP non-NULL interrupt being connected respectively to separately and is produced logic, produces logic by separately interruption again and outputs to interrupt request and gather the generation logic;
Local error interrupt signal is input to local mistake interruption and produces logic, gathers the generation logic by outputing to interrupt request after the local wrong interruption generation logical transition again;
Local interrupt request message is input to the local message receive logic of interrupting, it is that I/O device interrupt or IPI interrupt that local message receive logic is analyzed this interrupt request, select output I/O device interrupt to produce logical OR IPI then and interrupt producing logic, output to interrupt request again and gather the generation logic;
Long-range interrupt request message is input to long-range interruption message receive logic, outputs to long-range interruption by long-range interruption message receive logic again and produces logic, outputs to interrupt request again and gathers the generation logic;
Interrupt request gathers and produces logic the output of each part mentioned above is gathered, and converts internal system to and interrupts message format, outputs to the interruption sending module then.
Interrupting sending module forms by interrupting forwarding logic, up IPQ and long-range IPQ.Interrupt forwarding logic and receive,, select interruption is transmitted to native processor or system interconnection network according to the setting of interrupt register group and IO APIC interrupt redirection list item RTE to every kind of interrupt type from interrupting the interruption message of summarizing module output.The output of interrupting forwarding logic is connected to up IPQ and long-range IPQ.Up IPQ and long-range IPQ are the buffer zone and the steering logics thereof of interrupting message.The output of up IPQ is connected to processor, and the output of long-range IPQ is connected to the system interconnection network.
The interrupt register pack module comprises one group of interrupt register, be used to dispose various purpose nodes that interrupt corresponding interrupt vector number, interrupt message and purpose processor, interrupt mask, control the purpose processor and the interrupt priority level of interruption by the content of revising these registers, thereby realize program-controlled what interrupt.Adopting the register relevant with interruption that is provided with among the NC of the present invention is 64 bit registers, can expand to 128 according to system scale.These registers comprise:
LERCFG (Local Error Interrupt Redirect Configuration Register: local wrong interrupt redirection configuration register): the local wrong overall behavior of interrupting producing logic of this register controlled, its meta 63 puts 7 in place for keeping the position; Position 6 is local wrong long-range forwarding enable bit, and this position is that wrong interruption the in 0 expression this locality handled by native processor, is that 1 expression is transmitted to the Remote Node RN processing; Position 5 puts in place and 0 be the logic node number territory of Remote Node RN, is used to indicate the logic node number of the purpose node that interrupts transmission.
(Interrupt Vector Number Configuration Register: the interrupt vector configuration register): this register is used to be provided with the target processor of various interruptions and pairing interrupt vector number to VCFG.
REINT (Remote Error Interrupt Node Register: remote error interrupts the node register): this register record sends all nodes that remote error interrupts to this node.Wherein, each corresponding node, 0, the 63 corresponding node 63 of the 0th corresponding node, by that analogy.A certain position is that the corresponding node of 0 expression does not send the remote error interruption, is that the corresponding node of 1 expression has sent the remote error interruption.Operating system is according to this content of registers, constructs a node tabulation, and oriented node of record institute sent the Remote Node RN of interruption.
LEINT (Local Error Interrupt Node Register): each parts that make a mistake in this register minute book node.
DIOINT0～DIOINT31 (Detail of I/O Interrupt Register0～31): these 32 registers are used to write down the particular type of the I/O device interrupt that sends to this node.N node arranged in the system, and each node can produce 32 kinds of I/O at most and interrupt.The corresponding a kind of equipment of each register, a respectively corresponding node (for example, 0, the 63 corresponding node 63 of the 0th corresponding node) of each register shows whether this node has sent this kind device interrupt.
(Local Functional Interrupt Mask Register: functional interrupt mask register), this register is the interrupt mask register of NC built-in function unit PI, MI, NI etc. to LFMASK.
REMASK (Remote Error Interrupt Node Mask Register: the remote error interrupt mask register).Corresponding with REINT, each corresponding node.
LEMASK (Local Error Interrupt Node Mask Register: local wrong interrupt mask register): with the corresponding interrupt mask register of LEINT.
IOMASK (I/O Interrupt Node Mask Register:I/O interrupts the node mask register).The interrupt mask register of same DIOINT0～DIOINT31 correspondence, each corresponding node.
IOEOI (I/O End of Interrupt Register:I/O End of Interrupt register): finish by this register notice interrupt control administration module respective interrupt processing, can send next the interruption to processor.This register-bit 63 puts 38 in place for keeping the position;
The position 37 put in place 6 the expression corresponding 32 kinds of I/O device interrupt whether finish;
The EOI position is interrupted for remote error in position 4;
The EOI position is interrupted for MI in position 3;
The EOI position is interrupted for NI in position 2;
The EOI position is interrupted for the MP non-NULL in position 0;
These positions are 0 without any effect, are that 1 expression respective interrupt is handled and finished.
The present invention has expanded the content of IO APIC interrupt redirection list item RTE, with original position among the RTE 63 put in place 57 these keep the position and be defined as and interrupt the Remote Node RN that sends number, position 56 0 meaning that puts in place remains unchanged.Interrupt sending target processors by put in place 57 purpose node numbers that indicate, the position 56 purpose processor co that indicate of position 63.
Suppose that node a, node b represent two different SMP nodes, node a sends wrong method of interrupting to node b and is:
1. node a a local interrupt source produces one or more local wrong interruptions;
2. the interruption summarizing module among the node a NC produces corresponding interrupt request message, checks the purpose processor number and the configuration register relevant with this interrupt type of this interrupt request message through interrupting sending module, selects the transmit path of this interruption.If this interruption purpose processor is the processor of Remote Node RN, then sends to the system interconnection network, thereby be transferred to destination node; If interrupting the purpose processor is local node processor, then send to native processor.
3. the interruption summarizing module of the NC of node b receives the interrupt request message from node a, converts the interruption affairs on the system bus to, passes to certain processor of node b;
After node b receives and interrupts affairs, carry out subsequent treatment by the wrong interrupt handling routine of operating system, processing procedure is as follows:
4. the processor of node b is received and is had no progeny in long-range, reads the REINT register of node b, obtains producing the node tabulation of interruption;
5. according to the node tabulation, visit each node that produces mistake one by one and (comprise node LEINT register a);
6. need visit further more that the corresponding interrupt status register of bottom could obtain if produce wrong concrete reason, then visit the more corresponding interrupt status register of bottom, obtain interruption source and handle.Repeating 6 is complete 0 until the LEINT of node a register;
7. carrying out 5,6 REINT until node b repeatedly is complete 0.Remote error in the IOEOI register of removing node b interrupts the EOI position, and Interrupt Process finishes;
If have new remote error to interrupt afterwards, then begin to restart from the first step.
The generation and the sending method of I/O device interrupt of the present invention are:
1.IO equipment is offered IO APIC by the interrupt pin of IO APIC with interruption;
2.IO APIC is converted into the interrupt request message (as: Mem of particular address writes message) of corresponding I bus protocol, sends to NC;
3.NC after receiving I/O device interrupt message, analyze the purpose node number that comprises in the interruption message:
◆ if the purpose node number is this node, then give processor with this interruption by the interruption affairs of system bus.
◆ if the purpose node number is other Remote Node RN, then forward it to the system interconnection network.
After processor is received an I/O device interrupt, enter the interrupt handling routine of relevant device in the operating system, the treatment scheme of interrupt handling routine is:
1) reads the interruption source register that local NC produces the equipment of this kind interruption down;
2) obtain interruption source and handling;
3) repeat 1)～2) step, until the interruption of this equipment of finishing dealing with;
4) operating system one-writing system EOI space, data are interrupt vector.The EOI space is a private space of system definition, and when processor was write toward this space, NC produced corresponding EOI broadcasting packet, wherein comprises interrupt vector information.
5) the EOI broadcasting packet propagates into each I/O equipment of being hung along the I/O bus.
6) after the IO APIC interruptable controller in the I/O equipment receives the EOI broadcasting packet, it is interrupted the vector field compares with the Vector territory among each interrupt redirection register RTE, coupling is then removed ISR (Interrupt State Reigister: corresponding positions interrupt status register), and resampling interrupts input pin accordingly, generates new interrupt request message.
Adopt the present invention can reach following technique effect:
1) the long-range forwarding of the local various interruptions that produce of support;
2) support long-range interruption and the local transmission of interrupting to native processor of converging.
3) the present invention adopts the long-range transmission technology of message based program-controlled hardware interrupts, interruption is transmitted in system with the form of message, realize the program-controlled transmission of interruption by the RTE content of interrupt register group among the configuration NC of operating system software and IOAPIC, be embodied as and different interrupt selecting different purpose processors to handle, thereby sharing to provide for the I/O distribution of resource provides powerful support for.
Description of drawings
Fig. 1 is traditional SAPIC interrupt system structured flowchart;
Fig. 2 is an interrupt system structured flowchart of the present invention;
Fig. 3 is a NC interrupt control administration module logic diagram of the present invention;
Fig. 4 is the long-range transmission and reception processing flow chart that node internal error of the present invention interrupts;
Fig. 5 is the expansion definition corresponding tables of the present invention to RTE list item among the IO APIC;
LERCFG among Fig. 6 the present invention (Local Error Interrupt Redirect Configuration Register) register definitions;
Fig. 7 is (the Interrupt Vector Number Configuration Register: the register definitions interrupt vector configuration register) of VCFG among the present invention;
Fig. 8 is REINT among the present invention (Remote Error Interrupt Node Register) register definitions;
Fig. 9 is LEINT among the present invention (Local Error Interrupt Node Register) register definitions;
Figure 10 is DIOINT0～DIOINT31 among the present invention (Detail of I/O Interrupt Register0～31) register definitions;
Figure 11 is LFMASK of the present invention (Local Functional Interrupt Mask Register) register definitions;
Figure 12 is REMASK of the present invention (Remote Error Interrupt Node Mask Register) register definitions;
Figure 13 is LEMASK of the present invention (Local Error Interrupt Node Mask Register) register definitions;
Figure 14 is IOMASK of the present invention (I/O Interrupt Node Mask Register) register definitions;
Figure 15 is IOEOI of the present invention (I/O End of Interrupt Register) register definitions.
Embodiment
Fig. 1 is traditional SAPIC interrupt system structural drawing.This interrupt system is made up of the local APIC in the processor, IO APIC and bridge controller.Local SAPIC in the processor is responsible for queuing and shielding is interrupted, sent and receive IPI (Interprocessor Interrupt: interrupt between processor) message, receive external unit interrupt message from IO APIC, manage local interrupt source.IO APIC provides some interrupt pin, and IO equipment reports to IO APIC by these pins with interruption.A special interrupt redirection table is arranged among the IO APIC, and interrupt redirection table is made of one or more interrupt redirection list items (RTE), and the corresponding interrupt pin of each RTE is used to be provided with the interrupt vector, target processor of this interrupt pin correspondence etc.IO APIC accepts the look-at-me of interrupt pin, according to RTE configuration, converts look-at-me to corresponding interruption message, and IO APIC will interrupt message by the IO bus form of memory write transaction (for example, with) and pass to bridge controller then.Bridge controller will interrupt message and convert interruption affairs on the system front end bus to, send to processor.
Fig. 2 is an interrupt system structured flowchart of the present invention.Computer system is made of a plurality of SMP nodes, and each SMP node comprises a plurality of processors, node controller NC, main memory, IO APIC and IO equipment.Node controller NC is positioned at the center of SMP node, and processor, main memory, IO equipment and network all are connected to NC by the corresponding communication path.Processor is connected to NC by the system front end bus, and storer is connected to NC by memory bus, and IO equipment is connected to NC by the IO bus, and the system interconnection network is connected to NC by network.NC has realized corresponding processor interface PI, memory interface MI, IO bus interface and network interface NI.NC realizes the intercommunication mutually between processor, main memory, IO equipment and the network.Processor is responsible for handling interrupt; Node controller NC is responsible for the interruption of control and management from NC inside, local IO equipment, Remote Node RN; The I/O device interrupt is passed to IOAPIC by the pin of IO APIC, convert the interruption message to by APIC again and pass to NC, according to the configuration of RTE among the IO APIC of interrupt register group, selection will be interrupted message and pass to that native processor is handled or pass to teleprocessing unit by the system interconnection network and handle.
Fig. 3 is an interrupt control administration module logic diagram among the NC among the present invention.The interrupt control administration module is formed by interrupting summarizing module, interruption sending module and interrupt register pack module.
Interrupt summarizing module be responsible for receiving level look-at-me from each functional unit of NC inside, from the local interrupt request message of local node with from the long-range interrupt request message of Remote Node RN, through the corresponding generation logic of interrupting, they are gathered, convert internal system to and interrupt message format.Interrupt the look-at-me that produces from the different interrupt sources of system that is input as of summarizing module, these interrupt sources comprise:
1) the local interruption: from the interruption of local IO equipment and the interruption of inner each functional module of NC.
A) NMI interrupts: maskable does not interrupt, and is level signal;
B) PI interrupts: from the interruption of NC processor interface, be level signal;
C) MI interrupts: from the interruption of NC memory module, be level signal;
D) NI interrupts: from the interruption of NC Network Interface Module, be level signal;
The message transmission), BLT (piece transmission) interrupts, and is level signal e) descriptor is finished interruption: MP (Message Passing:;
F) the MP non-NULL interrupts: message is transmitted non-NULL and is interrupted, and is level signal;
G) error interrupt signal of inner each functional unit generation of local error interrupt signal: NC is level signal;
H) local interrupt request message: interrupt from the interruption of this node IO equipment, local IPI;
2) long-range interruption message: from the interruption of long-range other nodes.
NMI interrupts being input to NMI and interrupts producing logic, is interrupted producing the interrupt request singal that logical transition becomes processor identification by NMI, is directly connected to the interrupt pin of processor.PI interrupts being input to PI and interrupts producing logic, is interrupted producing the interrupt request singal that logical transition becomes processor identification by PI, is directly connected to the interrupt pin of processor.
MI interruption input is connected to MI and interrupts producing logic, outputs to interrupt request by MI interruption generation logic again and gathers the generation logic;
NI interrupts being input to NI and interrupts producing logic, outputs to interrupt request by NI interruption generation logic again and gathers the generation logic;
Descriptor is finished the interruption that interruption, MP non-NULL interrupt being connected respectively to separately and is produced logic, produces logic by separately interruption again and outputs to interrupt request and gather the generation logic;
Local rub-out signal is input to local mistake interruption and produces logic, outputs to interrupt request by local wrong interruption generation logical transition again and gathers the generation logic;
Local interrupt request message is input to the local message receive logic of interrupting, it is that I/O device interrupt or IPI interrupt that local message is accepted the logic analysis interrupt request, export the I/O device interrupt then respectively and produce logic and IPI interruption generation logic, output to interrupt request again and gather the generation logic;
Long-range interrupt request message is input to long-range interruption message receive logic, outputs to long-range interruption by long-range interruption message receive logic again and produces logic, outputs to interrupt request after the conversion again and gathers the generation logic;
The interrupt request summarizing module gathers the output of each part mentioned above, converts internal system to and interrupts message format, outputs to the interruption sending module then.
Interrupting sending module forms by interrupting forwarding logic, up IPQ and long-range IPQ.The input of interrupting forwarding logic is the output of interrupting summarizing module, interrupt the setting to every kind interrupt type of forwarding logic, select interruption is transmitted to native processor or system interconnect network according to interrupt register group and IO APIC interrupt redirection list item RTE.The output of interrupting forwarding logic is connected to up IPQ and long-range IPQ.Up IPQ and long-range IPQ are buffer zones that interrupts message.The output that up IPQ incites somebody to action is connected to processor, and the output of long-range IPQ is connected to the system interconnection network.
The interrupt register pack module comprises one group of interrupt register, be used to dispose various purpose nodes that interrupt corresponding interrupt vector number, interrupt message and purpose processor, interrupt mask, control the purpose processor and the interrupt priority level of interruption by the content of revising these registers, thereby realize program-controlled what interrupt.Adopting the register relevant with interruption that is provided with among the NC of the present invention is 64 bit registers, can expand to 128 according to system scale.
Fig. 4 is long-range transmission and the processing flow chart that mistake of the present invention is interrupted.Flow process is as follows:
1. node a the wrong interrupt source in this locality produces local an interruption;
2. the local wrong corresponding interrupt request message of logic generation that interrupts producing among the NC of node a is selected long-range interruption transmit path through interrupting sending module, is transferred to destination node by interconnection network;
3. the long-range interruption receiver module in the long-range interruption generation logic of the NC of node b receives interrupt request, produces corresponding interrupt request message by long-range interruption generation module, passes to certain processor of node b;
The processor of node b is had no progeny in receiving, enters the respective interrupt handling procedure of operating system, and the processing procedure of interrupt handling routine is as follows:
4. the processor of node b is received and is had no progeny in long-range, reads the REINT register of node b, obtains producing the node tabulation of interruption;
5. according to tabulation, visit each node that produces mistake one by one and (have a plurality of nodes and produce interruption, comprise node LEINT register a);
6. the LENIT register of visit node a if desired, is visited the more corresponding interrupt status register of bottom, obtains interruption source and handles.Repeating 6 is complete 0 until the LEINT of node a register, the local wrong EOI of the interruption position of removing node a subsequently.
Carrying out 5,6 REINT until node b repeatedly is complete 0.The remote error of removing node b interrupts the EOI position, and Interrupt Process finishes
If have new remote error to interrupt afterwards, then begin to restart from the first step.
Fig. 5 is the expansion definition of the present invention to interrupt redirection list item RTE among the IO APIC.It is 0 identical with traditional RTE definition that RTE meta 56 puts in place, position 63 put in place 57 in traditional RTE for keeping the position, the present invention is defined as purpose node number territory with these positions, is used to indicate interrupt the purpose node that sends.
Fig. 6 is LERCFG among the present invention (Local Error Interrupt Redirect Configuration Register) register definitions.
Wherein, position 63 puts 7 in place for keeping the position;
Fig. 7 is that (Interrupt Vector Number Configuration Register: the register definitions interrupt vector configuration register): this register is used to be provided with the target processor of various interruptions and pairing interrupt vector number to VCFG among the present invention.
Wherein, position 63 puts 38 in place for keeping the position;
Position 36 LINT[1 that indicate by processor 0] interrupt type that pin triggers, 0 expression PI interrupts, and 1 expression NMI interrupts;
Position 35 LINT[0 that indicate by processor 1] interrupt type that pin triggers, 0 expression PI interrupts, and 1 expression NMI interrupts;
Position 34 LINT[1 that indicate by processor 1] interrupt type that pin triggers, 0 expression PI interrupts, and 1 expression NMI interrupts;
Position 33 puts in place and 28 indicates various interruptions and send on the bus which processor and handle.Each corresponding a kind of interrupt type, the concrete corresponding relation between them is as follows:
33 MI interrupt
32 NI interrupt
31 descriptors are finished interruption
30 MP non-NULLs interrupt
29 Local Error interrupt
28 Remote Error interrupt
Wherein, corresponding position is that 0 this kind of expression interruption sends to processor 0 (ID is made as 0 among this processor Local ID), and corresponding position is that 1 this kind of expression interruption sends to processor 1 (ID is made as 1 among this processor Local ID);
Position 27 puts in place and 24 indicates the high 4 of interrupt vector number;
Position 23 puts in place and 20 indicates low 4 of corresponding interrupt vector that MI interrupts number;
Position 19 puts in place and 16 indicates low 4 of corresponding interrupt vector that NI interrupts number;
Position 15 puts in place and 12 indicates low 4 of corresponding interrupt vector number that descriptor is finished interruption;
Fig. 8 is REINT among the present invention (Remote Error Interrupt Node Register) register definitions: this register is used to write down all nodes that send the remote error interruption to this node.Wherein, each corresponding node, position 0 corresponding node 0 for example, position 63 corresponding nodes 63.A certain position is that the corresponding node of 0 expression does not send the remote error interruption, is that the corresponding node of 1 expression has sent the remote error interruption.
Fig. 9 is LEINT among the present invention (Local Error Interrupt Node Register) register definitions: this register is used for each parts that the minute book node makes a mistake.
Wherein, position 63 puts 6 in place for keeping the position;
Figure 10 is that (register definitions of Detail of I/O Interrupt Register0～n): this n register is used to write down the particular type of the I/O device interrupt that sends to this node to DIOINT0～DIOINTn among the present invention.N node arranged in the system, and each node can produce 32 kinds of I/O at most and interrupt.Therefore be provided with n 64 bit register DIOINT0～DIOINTn.The corresponding a kind of equipment of each register, respectively corresponding node of each register shows whether this node has sent this kind device interrupt.
Figure 11 is LFMASK of the present invention (Local Functional Interrupt Mask Register) register definitions.
Wherein, position 63 puts 5 in place for keeping the position;
Interrupt mask bit is finished for descriptor in position 1;
These positions are the corresponding interruption of 1 expression conductively-closed, are that 0 expression can be fed to native processor.
Figure 12 is REMASK of the present invention (Remote Error Interrupt Node Mask Register) register definitions.This register is corresponding with REINT, each corresponding node.A certain position is that the remote error of the corresponding node of 0 expression interrupts giving processor, is that the remote error of the corresponding node of 1 expression interrupts conductively-closed.
Figure 13 is LEMASK of the present invention (Local Error Interrupt Node Mask Register) register definitions.This register is the interrupt mask register of LEINT correspondence.
Wherein, position 63 puts 6 in place for keeping the position;
2 expression PI error masking positions, position;
1 expression MI error masking position, position;
0 expression NI error masking position, position;
These positions are that 0 expression respective interrupt can be given processor (Local or Remote), are 1 expression respective interrupt conductively-closed.
Figure 14 is IOMASK of the present invention (I/O Interrupt Node Mask Register) register definitions.This register is the interrupt mask register of DIOINT0～DIOINT31 correspondence, each corresponding node.A certain position is that the I/O of the corresponding node of 0 expression interrupts giving processor, is that the I/O of the corresponding node of 1 expression interrupts conductively-closed.
Figure 15 is IOEOI of the present invention (I/O End of Interrupt Register) register definitions.
Wherein, position 63 puts 38 in place for keeping the position;
The position 37 put in place 6 the expression corresponding 32 kinds of I/O device interrupt whether finish;
The local wrong EOI that interrupts of position 5 expressions;
Above-mentioned these positions are 0 without any effect, are that 1 expression respective interrupt is handled and finished.
The present invention has been implemented in the extensive distribution that University of Science and Technology for National Defence develops voluntarily and has shared in parallel I/O system, NC and interrupt control administration module thereof have been realized by the fpga chip that uses Xilinix company, by test, realized the program-controlled transmission interrupted in the massively parallel system, by interrupt register group among the configuration NC and the RTE among the IO APIC, the interruption of any one node can be forwarded to the target processor of any one node fast and handle, and shares to provide providing powerful support for for the efficient I/O of realization distribution of resource.
Claims (8)
1. program-controlled interrupt control method towards massively parallel system, it is characterized in that in the massively parallel system that constitutes by a plurality of SMP nodes, at each node, design a node controller NC, interrupt control administration module of design in node controller NC, realize that by the interrupt control administration module this node interrupts the long-range forwarding to other node, and this node is to from the interruption of Remote Node RN and the reception that gathers of local node interruption; The interrupt control administration module is formed by interrupting summarizing module, interruption sending module and interrupt register pack module; The content that expands IO APIC interrupt redirection list item RTE simultaneously realizes the program-controlled transmission of interruption to realize interrupting sending the location of purpose processor by interrupt register group in the configure interrupt control and management module and the RTE among the IO APIC.
2. the program-controlled interrupt control method towards massively parallel system as claimed in claim 1 is characterized in that node controller NC is positioned at the center of SMP node, and processor connects main memory, IO equipment and system interconnection network by NC; NC realizes processor interface PI, memory interface MI, IO bus interface and network interface NI; PI realizes the system front end bus interface, and NC and processor are by the system front end bus exchanging data; NC uses MI interface and main memory to carry out bidirectional data exchange; NC uses IO bus interface and IO equipment to carry out bidirectional data exchange; NC uses NI interface and system interconnect network to communicate.
3. the program-controlled interrupt control method towards massively parallel system as claimed in claim 1, it is characterized in that interrupting summarizing module and interrupt producing logic by NMI, PI interrupts producing logic, MI interrupts producing logic, NI interrupts producing logic, descriptor is finished and is interrupted producing logic, the MP non-NULL interrupts producing logic, the local wrong logic of interrupting producing, the local message receive logic of interrupting, the local message that interrupts produces logic, long-range interruption message receive logic, long-range interruption message produces logic, interrupt request gathers the generation logic and forms, be responsible for receiving level look-at-me from each functional unit of NC inside, from the local interrupt request message of local node with from the long-range interrupt request message of Remote Node RN, through the corresponding generation logic of interrupting, they are gathered, convert internal system to and interrupt message format; Interrupt the look-at-me of the input of summarizing module from different interrupt sources generations in the total system, these interrupt sources comprise:
3.1 local interruption the:, comprising from the interruption of local IO equipment and the interruption of inner each functional module of NC:
A) NMI interrupts: maskable does not interrupt, and is level signal;
B) PI interrupts: from the interruption of NC processor interface, be level signal;
C) MI interrupts: from the interruption of NC memory module, be level signal;
D) NI interrupts: from the interruption of NC Network Interface Module, be level signal;
E) descriptor is finished interruption: MP, BLT interrupt, and are level signal;
F) the MP non-NULL interrupts: message is transmitted non-NULL and is interrupted, and is level signal;
G) error interrupt signal of inner each functional unit generation of local error interrupt signal: NC is level signal;
H) local interrupt request message: interrupt from the interruption of this node IO equipment, local IPI;
3.2 long-range interruption message: from the interruption of long-range other nodes;
3.3 NMI interrupts being input to NMI and interrupts producing logic, is interrupted producing the interrupt request singal that logical transition becomes processor identification by NMI, is directly connected to the interrupt pin of processor; PI interrupts being input to PI and interrupts producing logic, is interrupted producing the interrupt request singal that logical transition becomes processor identification by PI, is directly connected to the interrupt pin of processor; MI interruption input is connected to MI and interrupts producing logic, outputs to interrupt request by MI interruption generation logic again and gathers the generation logic; NI interrupts being input to NI and interrupts producing logic, outputs to interrupt request by NI interruption generation logic again and gathers the generation logic; Descriptor is finished the interruption that interruption, MP non-NULL interrupt being connected respectively to separately and is produced logic, produces logic by separately interruption again and outputs to interrupt request and gather the generation logic; Local error interrupt signal is input to local mistake interruption and produces logic, gathers the generation logic by outputing to interrupt request after the local wrong interruption generation logical transition again; Local interrupt request message is input to the local message receive logic of interrupting, it is that I/O device interrupt or IPI interrupt that local message receive logic is analyzed this interrupt request, select output I/O device interrupt to produce logical OR IPI then and interrupt producing logic, output to interrupt request again and gather the generation logic; Long-range interrupt request message is input to long-range interruption message receive logic, outputs to long-range interruption by long-range interruption message receive logic again and produces logic, outputs to interrupt request again and gathers the generation logic; Interrupt request gathers and produces logic the output of each part mentioned above is gathered, and converts internal system to and interrupts message format, outputs to the interruption sending module then.
4. the program-controlled interrupt control method towards massively parallel system as claimed in claim 1 is characterized in that interrupting sending module and forms by interrupting forwarding logic, up IPQ and long-range IPQ; Interrupting forwarding logic receives from interrupting the interruption message of summarizing module output, setting according to interrupt register group and IOAPIC interrupt redirection list item RTE to every kind of interrupt type, selection is transmitted to native processor or system interconnection network with interruption, the output of interrupting forwarding logic is connected to up IPQ and long-range IPQ, up IPQ and long-range IPQ are the buffer zone and the steering logics thereof of interrupting message, the output of up IPQ is connected to processor, and the output of long-range IPQ is connected to the system interconnection network.
5. the program-controlled interrupt control method towards massively parallel system as claimed in claim 1, it is characterized in that the interrupt register pack module comprises one group of interrupt register, be used to dispose various purpose nodes that interrupt corresponding interrupt vector number, interrupt message and purpose processor, interrupt mask, control the purpose processor and the interrupt priority level of interruption by the content of revising these registers, thereby realize program-controlled what interrupt; These register root can be expanded according to system scale, comprising:
LERCFG is local wrong interrupt redirection configuration register: the local wrong overall behavior of interrupting producing logic of this register controlled, and its meta 63 puts 7 in place for keeping the position; Position 6 is local wrong long-range forwarding enable bit, and this position is that wrong interruption the in 0 expression this locality handled by native processor, is that 1 expression is transmitted to the Remote Node RN processing; Position 5 puts in place and 0 be the logic node number territory of Remote Node RN, is used to indicate the logic node number of the purpose node that interrupts transmission;
VCFG is the interrupt vector configuration register: this register is used to be provided with the target processor of various interruptions and pairing interrupt vector number;
REINT is that remote error interrupts the node register: this register record sends all nodes that remote error interrupts to this node.Wherein, each corresponding node, 0, the 63 corresponding node 63 of the 0th corresponding node, by that analogy; A certain position is that the corresponding node of 0 expression does not send the remote error interruption, is that the corresponding node of 1 expression has sent the remote error interruption; Operating system is according to this content of registers, constructs a node tabulation, and oriented node of record institute sent the Remote Node RN of interruption;
LEINT: each parts that make a mistake in this register minute book node;
DIOINT0～DIOINT31: these 32 registers are used to write down the particular type of the I/O device interrupt that sends to this node.N node arranged in the system, and each node can produce 32 kinds of I/O at most and interrupt, the corresponding a kind of equipment of each register, and respectively corresponding node of each register shows whether this node has sent this kind device interrupt;
LFMASK is functional interrupt mask register, and this register is the interrupt mask register of NC built-in function unit PI, MI, NI etc.;
REMASK is the remote error interrupt mask register: corresponding with REINT, and each corresponding node;
LEMASK is local wrong interrupt mask register: with the corresponding interrupt mask register of LEINT;
IOMASK is that I/O interrupts the node mask register: the interrupt mask register of same DIOINT0～DIOINT31 correspondence, each corresponding node;
IOEOI is an I/O End of Interrupt register: handle by this register notice interrupt control administration module respective interrupt and finish, can send next interruption, this register to processor
Position 5 is the local wrong EOI of interruption position;
The EOI position is interrupted for remote error in position 4;
The EOI position is interrupted for MI in position 3;
The EOI position is interrupted for NI in position 2;
Position 1 is finished for descriptor and is interrupted the EOI position;
The EOI position is interrupted for the MP non-NULL in position 0;
These positions are 0 without any effect, are that 1 expression respective interrupt is handled and finished.
6. the program-controlled interrupt control method towards massively parallel system as claimed in claim 1, it is characterized in that the present invention has expanded the content of IO APIC interrupt redirection list item RTE, with original position among the RTE 63 put in place 57 these keep the position and be defined as and interrupt the Remote Node RN that sends number, position 56 0 meanings that put in place remain unchanged, and interrupt sending target processors by the position 63 purpose processor co that the 57 purpose node numbers that indicate, position 56 indicate that put in place.
7. the program-controlled interrupt control method towards massively parallel system as claimed in claim 1 is characterized in that node a of the present invention sends wrong method of interrupting to node b and is:
7.1 the local interrupt source of node a produces one or more local wrong interruptions;
7.2 the interruption summarizing module among the node a NC produces corresponding interrupt request message, checks the purpose processor number and the configuration register relevant with this interrupt type of this interrupt request message through interrupting sending module, selects the transmit path of this interruption; If this interruption purpose processor is the processor of Remote Node RN, then sends to the system interconnection network, thereby be transferred to destination node; If interrupting the purpose processor is local node processor, then send to native processor;
7.3 the interruption summarizing module of the NC of node b receives the interrupt request message from node a, converts the interruption affairs on the system bus to, passes to certain processor of node b;
7.4 after node b receives and interrupts affairs, carry out subsequent treatment by the wrong interrupt handling routine of operating system, processing procedure is as follows:
Have no progeny in long-range 7.4.1 the processor of node b is received, read the REINT register of node b, obtain producing the node tabulation of interruption;
7.4.2, visit each one by one and produce the LEINT register that wrong node comprises node a according to the node tabulation;
If need visit further more that the corresponding interrupt status register of bottom could obtain 7.4.3 produce wrong concrete reason, then visit the more corresponding interrupt status register of bottom, obtain interruption source and handle; Repeating 6 is complete 0 until the LEINT of node a register;
7.4.4 carry out 5,6 REINT until node b repeatedly and be complete 0, the remote error of removing in the IOEOI register of node b interrupts the EOI position, Interrupt Process finishes;
If, then begin to restart from the first step 7.5 there is new remote error to interrupt afterwards.
8. the program-controlled interrupt control method towards massively parallel system as claimed in claim 1 is characterized in that the generation of I/O device interrupt of the present invention and sending method are:
8.1 IO equipment is offered IO APIC by the interrupt pin of IO APIC with interruption
8.2 IO APIC is converted into the interrupt request message of corresponding I bus protocol, sends to NC;
8.3 after NC receives I/O device interrupt message, analyze the purpose node number that comprises in the interruption message:
◆ if the purpose node number is this node, then give processor with this interruption by the interruption affairs of system bus;
◆ if the purpose node number is other Remote Node RN, then forward it to the system interconnection network;
8.4 the program-controlled interrupt control method towards massively parallel system as claimed in claim 1, after it is characterized in that processor of the present invention is received an I/O device interrupt, enter the interrupt handling routine of relevant device in the operating system, the treatment scheme of interrupt handling routine is:
8.4.1 read the interruption source register that local NC produces the equipment of this kind interruption down;
8.4.2 the interruption source of obtaining is also handled;
8.4.3 repeat 1)～2) step, until the interruption of this equipment of finishing dealing with;
8.4.4 operating system one-writing system EOI space, data are interrupt vector; The EOI space is a private space of system definition, and when processor was write toward this space, NC produced corresponding EOI broadcasting packet, wherein comprises interrupt vector information;
8.4.5 the EOI broadcasting packet propagates into each I/O equipment of being hung along the I/O bus;
After 8.4.6 the IO APIC interruptable controller in the I/O equipment receives the EOI broadcasting packet, it is interrupted the vector field compares with the Vector territory among each interrupt redirection register RTE, coupling is then removed the corresponding positions of interrupt status register ISR, and resampling interrupts input pin accordingly, generates new interrupt request message.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103890744A (en) * | 2011-10-26 | 2014-06-25 | 英特尔公司 | Multi-touch interface schemes |
| CN108073451A (en) * | 2017-12-20 | 2018-05-25 | 北京东土科技股份有限公司 | Interruption processing method and device between heterogeneous operating system on a kind of multi-core CPU |
| CN111221755A (en) * | 2019-12-28 | 2020-06-02 | 重庆秦嵩科技有限公司 | Io interrupt control method for FPGA2 submodule |
| CN111723032A (en) * | 2019-03-21 | 2020-09-29 | 杭州宏杉科技股份有限公司 | Interrupt management and control method and electronic equipment |
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2005
- 2005-03-30 CN CN 200510031391 patent/CN1664802A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103890744A (en) * | 2011-10-26 | 2014-06-25 | 英特尔公司 | Multi-touch interface schemes |
| CN103890744B (en) * | 2011-10-26 | 2019-08-16 | 英特尔公司 | Multi-touch interface method, system and equipment |
| CN108073451A (en) * | 2017-12-20 | 2018-05-25 | 北京东土科技股份有限公司 | Interruption processing method and device between heterogeneous operating system on a kind of multi-core CPU |
| CN108073451B (en) * | 2017-12-20 | 2020-09-22 | 北京东土科技股份有限公司 | Interrupt processing method and device between heterogeneous operating systems on multi-core CPU |
| CN111723032A (en) * | 2019-03-21 | 2020-09-29 | 杭州宏杉科技股份有限公司 | Interrupt management and control method and electronic equipment |
| CN111723032B (en) * | 2019-03-21 | 2021-09-24 | 杭州宏杉科技股份有限公司 | Interrupt management and control method and electronic equipment |
| CN111221755A (en) * | 2019-12-28 | 2020-06-02 | 重庆秦嵩科技有限公司 | Io interrupt control method for FPGA2 submodule |
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