CN1662064A

CN1662064A - Multi-path paralleled method for decoding codes with variable lengths

Info

Publication number: CN1662064A
Application number: CN 200410016508
Authority: CN
Inventors: 孙军; 司马苗; 唐泽鹏; 胡广
Original assignee: Shanghai Jiaotong University
Current assignee: Shanghai Jiaotong University
Priority date: 2004-02-24
Filing date: 2004-02-24
Publication date: 2005-08-31
Anticipated expiration: 2024-02-24
Also published as: CN100340114C

Abstract

Mode in macroscopical parallel and microcosmic serial is adopted in the invention. That is to say in macroscopy, decoding is carried out for multiple code streams by using same kernel of decoder; but any module inside decoder (first stage pipeline) only serves one code stream at a clock cycle. Thus, decoder can be operated at full speed without need of waiting for feedback loop to carry out operation in turn. The invention raises work efficiency of decoding module for variable length code in digital video decoder. Based on magnitude of working load, the method can start any route or multiple routes, possessing configurable and adjustable advantages.

Description

The method of multidiameter delay variable length code decoding

Technical field

The invention belongs to the full I frame decoder of high definition digital television field, be specifically related to a kind of method of multidiameter delay variable length code decoding.

Background technology

Current, general digital tv encoder technology is the MPEG-2 technology, and it is by the ISO/IEC13818 file description, and this document has only been stipulated the code table of variable length code in the video code flow, but concrete coding/decoding method is not made restriction provision.Because the operand of high definition television video encoder is very huge, logical need the realization by hardware.Especially very high to the requirement of variable length decoder throughput in the decode procedure of full I frame, general DSP and special chip can't be realized.

Variable length decoder can be divided into fixing imported and fixing two kinds of output types.Fixing imported being meant: decoder is according to fixing speed, and for example each clock cycle 1 bit receives the code stream of importing, output result when decoder is finished the decoding of a code word, and result's output is not timing.Therefore usually can't guarantee the speed of decoding.Fixedly output type is meant: decoder is according to fixing speed output decoder result.Fixedly the output speed type can guarantee decode rate, but there are following two aspect problems, length accumulator, alignment buffering area and suffix analysis module constitute a feedback loop on the one hand, the alignment buffering area must be charged to after accumulator obtains bit position indication in the length of a last code word, just can begin to adjust the content in the alignment buffering area; The opposing party and, the displacement of alignment buffering area and upgrade the action need regular hour, after the alignment buffering area upgrades and finishes before analysis module just can work on.To suppose that this feedback loop needs 3 clock cycle, can to solve a code word in each system clock cycle in order making, decoder clocks must be 3 times of system clock cycle.Sample rate for the video of MPEG-2@HL 4:2:2 form reaches 74.25MHz, then requires decoder clocks to reach 300M, so this feedback loop becomes the key of restriction VLD decoder throughput and decode rate.

The length foot of each variable length code is different, generally is made up of prefix and suffix two parts, can judge the length of whole codeword by the prefix of determining code word.And the suffix part can further be distinguished the code word that same prefix is arranged, thus final decoding.The code word size difference that Variable Length Code obtains, but transmit among putting into code stream continuously, do not protect at interval or any sign between the code word.Could determine the starting position of next code word after in decoding, only solving current code word like this according to the length of current code word.This recursive nature of variable length code has limited decode rate.

Fig. 1 is the basic principle block diagram of existing variable length decoder, as shown in Figure 1, after the input code flow of many bits enters input latch, through shift unit, analyze the information such as length of current code word by the prefix analyzer, and length information is fed back to the length accumulator, the length accumulator adds up all length of having finished the code word of decoding, and the control shift unit removes the current code word of finishing decoding, and the length accumulator is also controlled input latch and obtained new input code flow in addition.Shift unit removes the code word of finishing decoding, makes next code word be positioned at the beginning of shift unit, i.e. the next code word of left-justify.The prefix analyzer determines that by several bits of the beginning of analysis code word it belongs to that set of code words, and address generator utilizes the output of prefix analyzer and the remainder of code word to determine the address of decodes codeword in code table, finally finishes decoding by tabling look-up.

Can find from top narration, shift unit, prefix analyzer and length accumulator constitute a feedback loop.Shift unit must be waited for the result who analyzes current code word length of prefix analyzer.Input latch is preserved bit streams to be decoded such as N bit at every turn.Shift unit does not also have the bit segment of decoding to flow to the prefix analyzer following of the control of length accumulator, the prefix analyzer is judged the length of current code word according to former positions of bit segment, the length accumulator has added up after the length of current code word, could control shift unit current code word is removed, for the decoding of next code word is prepared.If therefore the delay of this feedback is m clock cycle, the operating efficiency of this system is 1/m so.This shows its inefficiency.

Summary of the invention

The purpose of this invention is to provide a kind of method of supporting the decoding of multidiameter delay variable length code simultaneously, this method uses macroscopic view parallel, the mode of microcosmic serial, promptly macroscopical a plurality of code streams use same decoder kernel to decode, and only be a code stream service in some clock cycle of any one module (i.e. a level production line) of decoder inside, make that decoder can full speed operation and needn't wait for feedback loop complete operation successively, thereby improve the operating efficiency of decoder.

For reaching above-mentioned purpose, the present invention is achieved in that

A kind of method of multidiameter delay variable length code decoding, may further comprise the steps: n road input code flow enters the bit stream buffer device corresponding with code stream quantity, and cushions in buffer; After input code flow in the described bit stream buffer device was selected by multiplexer, to the prefix analyzer, described prefix analyzer was sent length information into the m level and is delayed the length accumulator according to former the length of judging current code word of bit segment through shift unit; Select but the input code flow that do not enter shift unit is exported after described m level delays preserving m clock cycle in the input latch through described multiplexer; Described m level is delayed the length accumulator and according to the length information of the current code word that obtains all length of having finished the code word of decoding is added up, and control described shift unit and remove the current code word of finishing decoding, described m level is delayed the length accumulator current addition result is preserved and the input addition afterwards of m clock cycle; Address generator utilizes the remainder of the output of described prefix analyzer and code word to determine address in the code table of decodes codeword through after tabling look-up, to distribute to corresponding decoded result by demultiplexer, finishes decoding; M wherein, the feedback loop that the length accumulator constitutes is delayed in n 〉=2, and m 〉=n, described multiplexer, shift unit, prefix analyzer, part m level, this feedback loop is divided into the m level production line, and each level production line only is a code stream service in some clock cycle.

Preferable, described feedback is divided into 4 to 6 level production lines.

The invention has the beneficial effects as follows: improve the operating efficiency of variable-length decoding module in the digital video decoder, and can start any one tunnel or multichannel in the multiplexer, have configurable adjustable advantage according to the size of live load.

Description of drawings

Fig. 1 is the basic principle block diagram of existing variable length decoder

Fig. 2 is for supporting the flow chart of multichannel code stream variable length code decoding

Fig. 3 is that a plurality of programs are shared a multidiameter delay variable length decoder

Fig. 4 is that a program is divided into macro block bar parallel decoding

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, below with reference to accompanying drawing and enumerate case study on implementation, the present invention is described in more detail.

Embodiment one: as shown in Figure 2, and the common system block diagram that uses a decoding kernel of many input code flows.Suppose 3 code streams that have from same program or different programs.These 3 code streams at first cushion in buffering area separately.Select the code stream of a certain Lu Youxin to enter subsequent step by multiplexer then, perhaps the code stream that is kept at 6 grades of bit stream buffer devices on a certain road is as the input of subsequent module for processing.Shift unit wherein, the prefix analyzer, address generator, the operation principle of corresponding module is identical in the existing variable length decoder of the operation principle of modules such as code table and Fig. 1.

Multiplexer, shift unit, prefix analyzer, and the feedback that constitutes of 6 grades of parts of delaying the length accumulator to delay be 6 clock cycle, multiplexer in other words, shift unit, the prefix analyzer, and the formation of the part of 6 grades of accumulators 6 level production lines.Be under 3 tunnel the situation at input code flow, the decoding work of 3 code streams can not be distributed in successively in at the same level in 6 level production lines of feedback loop and carried out this moment, and or did not disturb.When finish table look-up after, decoded results belongs to different code streams, also needs to distribute to different code streams and be further processed through demultiplexer.Decoder can full speed operation and needn't be waited complete operation successively to be feedback like this.Compare with existing variable length decoder, its decoding efficiency has improved three times.

Embodiment two: as shown in Figure 3, when a plurality of programs are shared a multidiameter delay variable length decoder, can be through after the program pre-treatment, become the multichannel input code flow, enter the multidiameter delay variable length decoder, through decoding, decoded results is passed through after the program reprocessing again, obtains decoded picture.Sometimes because the code check of one road video code flow is excessive, and original variable length decoder can't reach the requirement of speed, can adopt the mode of Fig. 4 that a program is divided into the several macro blocks bar this moment, and the mode by the macro block bar being carried out parallel decoding is to improve the decode rate of variable length code.

Claims

1. the method for multidiameter delay variable length code decoding may further comprise the steps:

1) n road input code flow enters the bit stream buffer device corresponding with code stream quantity, and cushions in buffer;

2) after the input code flow in the described bit stream buffer device was selected by multiplexer, to the prefix analyzer, described prefix analyzer was sent length information into the m level and is delayed the length accumulator according to former the length of judging current code word of bit segment through shift unit; Select but the input code flow that do not enter shift unit is exported after the m level delays preserving m clock cycle in the input latch through described multiplexer;

3) described m level is delayed the length accumulator and according to the length information of the current code word that obtains all length of having finished the code word of decoding is added up, and control described shift unit and remove the current code word of finishing decoding, described m level is delayed the length accumulator current addition result is preserved and the input addition afterwards of m clock cycle;

4) address generator utilizes the remainder of the output of described prefix analyzer and code word to determine address in the code table of decodes codeword through after tabling look-up, to distribute to corresponding decoded result by demultiplexer, finishes decoding; In above-mentioned steps, m, n 〉=2, and m 〉=n, described multiplexer, shift unit, prefix analyzer, part m level are delayed the feedback loop that the length accumulator constitutes, and this feedback loop is divided into the m level production line, and each level production line only is a code stream service in some clock cycle.

2. the method for multidiameter delay variable length code decoding according to claim 1 is characterized in that: described feedback is divided into 4 to 6 level production lines.