CN1658597A - High speed routing table learning and lookup - Google Patents
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Abstract
A switch includes multiple ports, a switching fabric, and a routing table module. The routing table module includes a multi-bank memory structure for maintaining routing information. The routing information enables the switching fabric to route packets between the ports based upon addresses within the packets. Particular implementations include overflow buffers to increase storage locations beyond those provided within the multi-bank memory structure.
Description
The cross reference of related application
The application is the continuity for the part of the u.s. patent application serial number 10/360,004 of " starting the address learning (learn) of (enable) high speed routing table lookup " of the title submitted on February 7th, 2003 by Sridhar Pathi and Takeshi Shimizu.
Technical field
The present invention relates generally to communication system, particularly start the address learning of high speed routing table lookup.
Background technology
Technological progress has not promoted improving the demand of data signaling rate with allowing to change.In order to satisfy this demand, networking component must be designed to carry out high speed operation day by day.For example, in order to solve the growth rate on the transmission line, switch (switch) must be able to carry out the expressway by (routing) decision-making, so that in these linear speeds (wire speed) work down.
Summary of the invention
According to the present invention, be provided for starting the address learning technology of high speed routing table lookup.According to specific embodiment, switch comprises the router table means that is formed by a plurality of memory blocks (memory bank), and this router table means can be carried out the high speed routing table lookup.
According to an embodiment, switch comprises: a plurality of ports that are used for communications packets; Be used between these ports, transmitting the switching fabric of bag; And logical partitioning is a plurality of memory blocks of multirow, and wherein, every row comprises the memory location from each memory block, and route inlet (entry) can be safeguarded in each memory location.This switch also comprises and overflows buffer, and it has a plurality of memory locations of overflowing, and each overflows the memory location can safeguard the route inlet.This switch also comprises memory control module, it based on the indicated address of this memory access requests, determines the particular row of these row from one of port reception memorizer access request, access is indicated goes and overflows buffer, to carry out memory access operations.
Embodiments of the invention provide various technological merits.By utilizing a plurality of memory blocks to implement router table means, switch can provide router table means relatively little and cheap but that be exceedingly fast.This router table means sometimes victim-way by information integrity, but these sacrifices can bring quicker, more cheap enforcement.For example, specific embodiment provides the confined space, is used to safeguard the port that leads to map addresses information.This confined space can not support to lead to the storage of all potential ports of map addresses.In these environment, switch can be taked bag diffusion (flooding), replaces " intellectuality " route.Yet specific embodiment attempts to limit such generation.And these embodiment still can be designed to meet such as standards such as ANSI/IEEE802 standards.
From following accompanying drawing, specification and claims, those skilled in the art will easily understand other technologies advantage of the present invention.And, although toply enumerated concrete advantage, various embodiment can comprise all, part or do not comprise cited advantage.
Description of drawings
In order to understand the present invention and advantage thereof more fully, with reference to the following description that combines with accompanying drawing, wherein:
Fig. 1 has illustrated the multi port switch with router table means according to specific embodiment of the present invention;
Fig. 2 is the block component diagram of explanation from the exemplary router table means of this switch;
Fig. 3 is the block diagram that explanation is used for the exemplary selection logic device (logic) of selection between potential route inlet;
Fig. 4 illustrates that utilization has the polylith router table means of overflowing buffer and handles routing table method of operating flow chart; And
Fig. 5 is the method flow diagram that the explanation access has the multibank memory structure of overflowing buffer.
Embodiment
Fig. 1 illustrates switch 10, comprises a plurality of port ones 2 that interconnect by switching fabric 14.Switch 10 also comprises router table means 16, and it comprises a plurality of memory blocks 18 that are used to store routing iinformation.Usually, router table means 16 maintaining routing informations are with the packet switch between the control port 12.Particularly, router table means 16 provides the multibank memory structure, to provide the expressway by table handling.
Each port one 2 representative contains the hardware that is useful on transmission and receives any suitable control logic device of bag.For example, each port one 2 can comprise input module and the output module that is used to receive and send bag.Used term " bag " in this specification is meant to comprise Datagram any message segment.For example, bag can comprise ethernet frame, Internet protocol (IP) bag, ATM(Asynchronous Transfer Mode) unit and/or any other appropriate information section.Within switch 10, switching fabric 14 provides the transmission of the bag from arbitrary port one 2 within the switch 10 to any or all of the port 12.Although be illustrated as the individual module within the switch 10, can be contemplated that switching fabric 14 comprises any appropriate combination and the arrangement of unit (element), these unit are configured be enough to provide packet switch under the speed of supporting port one 2 to communicate by letter with being designed to.
Within switch 10, router table means 16 maintaining routing informations are with the packet switch between the control port 12.In order to control switching fabric 14, routing iinformation comprises any amount of with the inlet of map addresses to port.Switch 10 is indicated the bag between the port 12 based on this routing iinformation.For example, the inlet in the routing iinformation can be mapped to address XYZ port A.When another port 12 received the bag of going to address XYZ, switching fabric 14 can be indicated to this bag port A.Given so suitable routing iinformation within routing module 16, switching fabric 14 can be between port one 2 " intelligently " exchange packets.And although this example illustrates the single port that is mapped to the address, switch 10 can be contemplated that the inlet mapping address that leads to any amount port one 2.
In specific environment, router table means 16 is not the bag mapping address of all receptions.For example, one of port one 2 can receive bag, this bag have with router table means 16 within the unmatched destination address of inlet.According to specific embodiment, if router table means 16 does not provide mapping, then switch 10 should wrap " diffusion " to every other port one 2.Just, switch 10 sends this bag from all of the port except that receiving port 12 12.
As the example of routing table operation, consider port one 2, this port receives the bag that contains destination address.If router table means 16 is provided for the port mapping of this destination address, then switching fabric 14 offers this bag all of the port 12 of indicating within the routing iinformation.Yet if router table means 16 for indicated destination address, does not provide mapping, switching fabric 14 is diffused into this bag the every other port one 2 of switch 10.The bag diffusion causes Internet traffic to increase, but guarantees that this bag will transmit from correct port one 2.
Within router table means 16, the road has information can contain static and dynamically enters the mouth.Static route entry comprises by firmware to be set, is disposed and/or the static inlet of setting up within router table means 16 by the system manager.For example, the system manager can be based on known network topology, configuring static route inlet.Other examples of static inlet comprise the routing iinformation that is used for private network address (such as broadcasting, multicast or other specific addresses).
The dynamic routing inlet is created automatically, is safeguarded and deletion at the duration of work of switch 10.According to specific embodiment, switch 10 utilizes the study scheme, and the dynamic routing inlet is distributed (populate) in router table means 16.According to this scheme, the source address that switch 10 utilizes in the bag that is received is distributed in inlet within the router table means 16.For example, consider that switch 10 receives bag at port A, this bag has source address XYZ.Do not reflect this mapping if router table means 16 is current, then router table means 16 can be added the route inlet that address XYZ is mapped to port A.When reception had the subsequent packet of destination address XYZ, switch 10 can transmit these bags from port A based on the mapping within the router table means 16.
Router table means 16 also can provide and remove the route inlet from routing iinformation.For example, router table means 16 can periodically be deleted expired inlet.Router table means 16 can be utilized other suitable mechanism of being safeguarded within timestamp and/or the routing iinformation, carries out expired inlet this " wearing out ".
According to specific embodiment, each inlet in the router table means 16 comprises address, routing iinformation and management information.This address maintenance is such as medium access control information such as (MAC), with the bag that is received in the address be complementary.Routing iinformation is indicated one or more ports, should or these ports should receive have with this inlet within the destination address that is complementary of address.According to specific embodiment, this road has information can be embodied as bit vector, and whether the corresponding port of each bit representation is mapped to particular address.For example, given 12 port arrangement, 12 bit vectors can indicate which port one 2 to be mapped to indicated address.
This management information comprises any proper data that is used for maintenance access.According to specific embodiment, this management information comprises timestamp, static indicating device, effective indicating device and check code." age " of timestamp reflection inlet, can be by switch 10 operation that is used for wearing out.Static indicating device indicates whether this inlet is static.According to specific embodiment, if static indicating device is set, switch 10 will can dynamically not deleted this inlet.Effectively indicating device illustrates whether mapping indicated in this inlet is correct.Thus, for example for " deletion " inlet, it is invalid that router table means 16 can simply be provided with effective indicating device.The check code territory can be contained within the management information, so that reliability to be provided.
During operation, router table means 16 can provide three kinds of basic operations: learn, delete and search.As discussed above, switch 10 is handled dynamically and static study.Dynamic learning adds inlet to router table means 16 based on the source address in the bag that is received.Static study comprises routing iinformation during making, setting up or the concrete configuration of other opportune moments.For learning manipulation, router table means 16 at first determines whether to have the suitable mapping that is used to address to be learnt, and then, if there is not this mapping to exist, then creates inlet within routing iinformation.Thus, learning manipulation needs two cycles, and one-period is used to read, and one-period is used to write.
Similar to learning manipulation, deletion action can be handled the static state of inlet and dynamically remove.Dynamically deletion can take place based on aging or other suitable environment.Static deletion can and take place based on configuration or other suitable indications, to change the static state inlet within the router table means 16.Similar to learning manipulation, router table means 16 can determine at first whether inlet is fully aging, if then router table means 16 can be deleted this inlet.Thus, deletion action can take two cycles and finishes.
Search operation as previously mentioned, the mapping of the destination address that is used for the bag that received of trying to find out.According to specific embodiment, switch 10 handles multicast and single-point is broadcast searching of address.For multicast address, router table means 16 generally disposes static route entry.This can carry out the intelligent route of multicast bag.Broadcast bag for single-point, router table means 16 is handled routing decision usually based on dynamic learning.Thus, switch 10 can be broadcast bag with the diffusion single-point usually, till learning the proper address mapping.According to specific embodiment, switch 10 can be distinguished between multicast and single-point broadcasting address based on the information in the address.For example, according to 802.1 standards,, from single-point broadcasting address, distinguish multicast address based on the numerical value of dedicated bit.Router table means 16 can be utilized single read operation, carries out search operation.Thus, search operation can only take the single cycle and finishes.
In the embodiment shown, router table means 16 comprises a plurality of memory blocks 18 and overflows buffer 26.These memory cells provide the storage of routing iinformation, are discussed in more detail with reference to Fig. 2.
Fig. 2 is the block diagram of the exemplary functional components of explanation router table means 16, and it comprises a plurality of memory blocks 18, arbitration modules 20, access module 22 and a plurality of buffer 26 that overflows.In the embodiment shown, arbitration modules 20 is connected to each port one 2 within the switch 10, to receive study (LRN) and to search (LUP) request.Similarly, access module 22 is connected to each port one 2 within the switch 10, with in response to search request, provides routing iinformation (RI).During operation, memory block 18 and overflow the routing iinformation that buffer 26 is safeguarded switch 10.Usually, a plurality of memory block structures make router table means 16 can provide the expressway by table handling with relevant access plan.
Any appropriate hardware (comprising suitable control logic device) that each memory block 18 representative is used to store the route inlet.Each memory block 18 can be by independent access, to carry out read or write.Thus, for example during specific period, access module 22 can carry out read operation from some or all of memory blocks 18.Similarly, during the cycle, access module 22 can carry out write operation on some or all of memory blocks 18.Access module 22 can further mix these operations, and for example access module 22 is written to a memory block 18 and reads from every other memory block 18.
Similar to memory block 18, each overflows any appropriate hardware (comprising suitable control logic device) that buffer 26 representatives are used to store the route inlet.Overflowing buffer 26 can be by independent access, to carry out read or write.In addition, each overflows buffer 26 and is connected to access module 22.This allow access module 22 for overflow buffer 26 provide to about memory block 18 described similar controls.
In the embodiment shown, each memory block 18 is a plurality of positions 24 by logical partitioning.For example, each memory block 18 can be divided into 1024 positions, and the route inlet can be safeguarded in each position.In addition, router table means 16 can further be logically divided into multirow with storage stack piece 18, and every row comprises the correspondence position 24 of crossing a plurality of memory blocks 18.For example, first row is (as R
0Shown in) can comprise primary importance 24 from each memory block 18.Similarly, n is capable (as R
nShown in) can comprise n position 24 from each memory block 18.Thus, for example, if each memory block 18 is logically divided into 1k position 24, then can be logically divided into 1k capable for 18 groups of memory blocks.
Access module 22 utilizes read and/or write access memory piece 18.According to specific embodiment, access module 22 carries out read operation through a full line.Thus, for example access module 22 reads the content of each position 24 within the particular row simultaneously.For write operation, access module 22 can aim at (target) particular memory block 18.For example, access module 22 can be written to the ad-hoc location 24 within the selected memory block 18.
According to specific embodiment, single memory piece 18 can not supported read-write operation simultaneously.Thus, if access module 22 is selected to be written to particular memory block 18, then do not allow access module 22 to read simultaneously from this particular memory block 18.Yet this does not influence the ability that access module 22 reads from other memory blocks 18.Therefore in the single cycle, access module 22 can be written to a memory block 18, reads from every other memory block 18 simultaneously.In this example, if access module 22 is just attempting to read a full line content, access module 22 position 24 in the access memory piece 18 only then, and do not carry out write operation.Thus, the write operation in one or more memory blocks 18 can influence the ability of access module 22 from reading simultaneously through all positions 24 of delegation.
For example, consider to have the router table means 16 of four memory blocks 18.During the cycle, access module 22 arranges (schedule) write operation to be used for first memory piece 18 and read operation is used for particular row.In this cycle, access module 22 will be only position 24 reception information within second, third and the 4th memory block 18.Thus, the access module 22 of given this environment can't the access particular row within information in one of the position 24.This may influence router table means 16 and detect the ability of mating in the routing iinformation, and is following specifically described.
According to specific embodiment, access module 22 utilizes hash (hashing) technology to be used for access memory piece 18.According to these embodiment, access module 22 can be from the source or destination address produce hash key.Then, access module 22 utilizes this hash key, indicated row within the access memory piece 18.For example, consider to be logically divided into the capable memory block of 1k 18.Be used to ten information from the address, access module 22 can produce the hash key with one of described row of unique identification.Thus, utilize this hash key, access module 22 can be identified for searching or the suitable row of learned addresses.
For search request, access module 22 receiving target addresses produce hash key from this address, read from the indicated row of this hash key then.If the inlet in destination address and this row in one of position 24 is complementary, then access module 22 can return this routing iinformation from this coupling inlet.If any inlet within the position 24 of destination address and indication row does not match, then access module 22 can be indicated " failure (miss) ", and this will cause the diffusion of wrapping.
Yet in the embodiment shown, router table means 16 also comprises overflows buffer 26.In particular instance, these overflow buffer also can safeguard to memory block 18 within the similar routing table inlet of storing.For example, overflowing buffer can provide and overflow storage, safeguards route inlet that overflows from " being full of " row.Thus, in containing the embodiment that overflows module 26, access module 22 can determine further whether this destination address is complementary with arbitrary inlet that overflows in the buffer 26.In these examples, access module 22 can be selected routing iinformation based within the row of being discerned or overflow hitting within one of buffer 26 (hit).Only within routing iinformation does not appear at identification row or when overflowing within the buffer 26, access module 22 can be indicated failure thus.Below with reference to Fig. 3, describe and discuss specific selection logic device in detail, it is used to discern from memory block 18 and the suitable routing iinformation that overflows within the buffer 26.And on the whole about learning manipulation, following discussion is used to overflow the learning manipulation of buffer 26.
For learning manipulation, access module 22 can carry out read-write operation.The source address that provides in the learning manipulation is provided, and access module 22 produces hash keys, reads from the indicated row of this hash key.Do not contain coupling with source address if this is capable, then router table means 16 can attempt learning routing iinformation.Next or in some subsequent cycles, access module 22 carries out write operation thus,, inlet is inserted in any position 24 within the row that hash key discerned.According to specific embodiment, router table means 16 is attempted the room 24 within the indicated row of selection.For example routing table can be selected first memory piece 18 (it has the room 24 in the indicated row), uses at random or pseudo-random algorithm, selects the room 24 within the indicated row.If there is not room 24 in indicated row, then router table means 16 can select to ignore this study request, perhaps allows this request queue wait, and can use until room 24.
Because study depends on room 24 availabilities within the indicated row of hash key, router table means 16 can't be learnt some map addresses information sometimes.For example, consider to have the router table means 16 of eight memory blocks 18, all eight memory locations 24 are current effective in the particular row.As previously mentioned, router table means 16 can simply be ignored any study request that receives, and these requests produce the hash key that is applicable to particular row.This can cause the diffusion of subsequent communications amount to increase, but allows router table means 16 to use relatively little high-speed memory structure.
For the diffusion that the full row that reduces within the memory block 18 produces, router table means 16 can comprise overflows buffer 26.As previously mentioned, router table means 16 comprises overflows buffer 26, to help to alleviate the routing iinformation storage problem that produces from full row.Overflowing buffer 26 provides the additional lanes within the router table means 16 to be stored by inlet.When the row in the memory block 18 was expired, access module 12 can send to the accretion learning request that is used for these row and overflow buffer 26.
For example, consider to specify the study request of particular row, wherein each memory block 18 is current has effective inlet.In this embodiment, access module 22 can be chosen in storage routing table inlet in selected that overflows buffer 26.Access module 22 can utilize any suitable selection technology, these is overflowed the study request store in the available position that overflows within the buffer 26.For example, be provided for 16 routing table inlets if overflow buffer 26, then access module 22 can use two byte vectors, and the available memory position within the buffer 26 is overflowed in indication.Utilize this vector, access module 22 can determine to overflow the room within the buffer 26, arranges the study request to write in the room.Therefore, router table means 16 can spill in the room of overflowing within the buffer 26 by the request of will learning, and handles these study requests that are used for full row.As an example, if only delegation spills into continuously and overflows in the buffer 26, then this row can effectively extend to the degree that buffer 26 sizes are allowed of overflowing.Yet, overflow buffer 26 sharing between a plurality of overflow lines and can limit the quantity that every row may expand to.
According to specific embodiment, access module 22 can allow to spill into the arbitrary available inlet that overflows within the buffer 26 from arbitrary row.Alternatively, access module 22 can only allow particular row to spill into to overflow in the specific inlet within the buffer 26.For example, consider to have two overflow buffer 26 shown in router table means 16.Access module 22 can distribute from these the row first half to the first overflow overflowing the buffer 26, and from these the row latter halfs to the second overflow overflowing the buffer 26.Yet, although describe and illustrate specific embodiment, switch 10 can be contemplated that comprise any suitable quantity overflow buffer 26, access module 22 provides any proper technology, is used for handling route and enters the mouth to and overflow overflowing of buffer 26.In addition, single " overflowing buffer " can comprise any amount of memory cell, and these unit provide the memory location for the route inlet of right quantity.
According to specific embodiment, the unified scheme that switch 10 is provided for access memory piece 18 and overflows buffer 26.This scheme is used aforementioned hash key together with the index (index) among the indicated row of hash key.Do not dispose at switch 10 and to overflow under the situation of buffer 26, but specific of this index instruction memory piece 18.For disposing the switch 10 that overflows buffer 26, this index is one of instruction memory piece 18 similarly, perhaps can indicate the ad-hoc location that overflows within the buffer 26.For example, utilize N memory block 18 and overflow M position in the buffer 26, index can be indicated to N from zero, and with the position in the recognition memory piece 18, perhaps this index can be indicated to M-1 from N, overflows position in the buffer 26 with indication.Yet because the uniformity of hash key access, switch 10 need have the senior access logic device that is used to handle the interpolation of overflowing buffer 26.
As previously mentioned, access module 22 can arrange the read and write operation to be used for different memory piece 18 within same period.Thus, for example access module 22 can arrange to be written to one of memory block 18 during the same period that access module 22 is attempted to read from delegation.As previously mentioned, this causes access module 22 only to read inlet from the memory block 18 that those are not arranged write operation.When carrying out the searching of destination address, this situation can cause " false (false) " failure.False failure occurs when memory block 18 comprises the coupling of destination address, but the memory block 18 of safeguarding this coupling inlet carries out write operation, and simultaneously, all the other memory blocks 18 carry out read operation.Under the situation of falseness failure, access module 22 will be indicated failure, even in fact this row comprises coupling.The possibility of false failure is limited by memory block 18 limited in number within the table module 16.For example, if write operation is subject to single memory piece 18, router table means 16 comprises four memory blocks 18, and the possibility of then false failure during read/write cycles is 25%.Yet when considering write operation generally at the most only when (because this study and deletion action take two cycles) appears in one-period, the possibility that falseness is failed reduces by half.
According to specific embodiment, router table means 16 prevents that false failure from taking place during the search operation of multicast address or during the read operation of study.For example, owing to be applied to the strict standard of multicast address, router table means 16 can prevent any write operation during the multicast search operation.Similarly, for learning manipulation, router table means 16 can learning manipulation read part during, prevent write operation simultaneously.This has prevented that router table means 16 from detecting the needs of the new inlet of study undeservedly based on the falseness failure.
In order to handle the read-write operation arrangement of access module 22, router table means 16 comprises arbitration modules 20.During operation, arbitration modules 20 receives from port one 2 and searches and learning manipulation, determines the suitable read and write operation of access module 22.Arbitration modules 20 is searched these with learning manipulation and is distinguished order of priority together with any other proper handling (such as memory block 18 and overflow the aging of inlet in the buffer 26).According to specific embodiment, 20 pairs of any uncompleted (outstanding) search request of arbitration modules are set limit priority.Behind the given limit priority of search request, even arbitration modules 20 will provide timely service to these requests when the traffic of worst case.
For example, consider to have the switch 10 of 12 port ones 2, each port one 2 receives the ethernet frame of minimum dimension simultaneously.According to ethernet standard, the ethernet frame of minimum dimension is near 64 bytes.In a particular embodiment, switch 10 receives the ethernet frame of minimum dimension in about 20 cycles.Therefore,, then do not have port one 2 will begin to receive another frame, (receive present frame) till after 20 cycles because each port one 2 will take 20 cycles at least if each port one 2 receives the ethernet frame of minimum dimension simultaneously.Even when this worst case, still can within 12 cycles, obtain arbitration modules 20 services from the search request of each port one 2.This stayed about eight back-up period before any new search request arrives.
In this example, when bag was received, each port one 2 also can produce the study request.Thus, in the example of worst case, arbitration modules 20 also can receive 12 study requests together with 12 search request.Given only eight back-up period, arbitration modules 20 can select only to serve the selected request in these requests.Thus, search request is distributed priority, the study request can be paid in back-up period.When additional study request arrived, arbitration modules 20 can select to allow the study request queue, perhaps abandons the not study request of service simply.For example, arbitration modules 20 can be safeguarded the study request of each port one 2 that receives recently simply.This guarantees to learn to ask to reflect the port mapping that receives recently.
Although illustrated embodiment and formerly describe the specific embodiment focus on router table means 16, switch 10 can be contemplated that, router table means 16 has any appropriate combination and the arrangement of the unit that is used to support hybrid, synchronous access memory construction.Thus, shown in the discrete cell function of carrying out can suitably be separated or be made up, these unit of some or all can be realized by the logic device that is encoded in the media.For example, the function of arbitration modules 20 and access module 22 can suitably be separated and/or be made up, and their any operation can be implemented by suitable store control logic device.In addition, although memory block 18 and overflow buffer 26 and all be shown as the separate type assembly, router table means can be used any suitable memory construction that identity function is provided.Simultaneously, although be depicted as individual module, the function of assembly shown in some or all of router table means 16 can be distributed between other unit of switch 10.
Fig. 3 is the block diagram that selection logic device 30 used when router table means 16 is selected between the memory location of access is described.Usually, select the logic device determine in the router table means 16 the route inlet whether with search request in indicated address be complementary.Determine based on this, select logic device 30 can indicate routing iinformation, this information Recognition port mapping or mistake.
Except that search request information, selection logic device 30 is from memory block 18 and overflow buffer 26 reception inputs.In the embodiment shown, select logic device 30 receive shown in 32 search request information thus, shown in 34 from the output of delegation's memory block 18, shown in 36 from first overflow the output of buffer 26, shown in 38 from second output of overflowing buffer 26.Search request information 32 comprises the information in order to the required particular address of identification port mapping.For example, search request information 32 can comprise the MAC and the VID value of indicated address.Line output 34 is included in the route inlet in the indication row of each memory block 18.Thus, line output 34 comprises the routing iinformation of this row that search request information 32 is discerned.
In the aforementioned embodiment, router table means 16 comprises that two overflow buffer 26.Thus, in this example, select logic device 30 to overflow buffer 26 receptions and overflow output from first and second.First overflows output 36 is provided at first and overflows within the buffer 26 the route inlet of safeguarding.Similarly, second overflows output 38 and is provided at second and overflows within the buffer 26 the route inlet of safeguarding.
As previously mentioned, what router table means 16 can comprise any suitable quantity overflows buffer 26, has any suitable scheme, is used for that inlet is spilt into these from full row and overflows the buffer 26.Thus, if for example two each of overflowing buffer 26 only are mapped to capable particular group, then select logic device 30 can only receive such output, this output is to be provided by the buffer 26 that suitably overflows that is mapped to indicated row.During given this mapping, one or more buffers 26 that overflow can be allocated for capable selected group, do not add the complexity of selecting logic device 30 and heighten very much.For example, consider to have eight specific embodiments that overflow the router table means 16 of buffer 26, overflow each group that buffer is assigned to 26 1 groups by a group row within the memory block 18 two.In this configuration, select logic device 30 still can operate as mentioned above, receive line output mutually concurrently with the output of overflowing buffer 26 from two.This has showed one or more buffers 26 that overflow are how to be contained within the router table means, and not serious speed, size and the complexity of influencing.
Select logic device 30 to receive potential route inlet from indicated row with from each suitable buffer 26 that overflows thus.Whether the input that utilization receives selects logic device 30 to determine, from memory block 18 or overflow one of route inlet that buffer 26 receives and be complementary with search request information 32.For example, select logic device 30 can comprise many comparators in parallel, these comparators allow to select logic devices 30 simultaneously with each line output 34, each overflows output 36,38 and compares with search request information 32, with definite potential hitting.Based on these relatively, select logic device 30 to determine suitable routing iinformation.For example, if selection logic device 30 is discerned the coupling between one of these search request information 32 and potential route inlet, then select the indicated routing iinformation of route inlet of exportable this identification of logic device.Yet, if select logic device 30 to determine that potential route inlet does not all match with routing iinformation 32, selects router three 0 can indicate failure.
Fig. 4 be explanation router table means 16 in response to search and learn to ask, to memory block 18 with overflow the method flow diagram that the routing iinformation of being safeguarded within the buffer 26 carries out periodicmaintenance.Unit with reference to above-mentioned router table means 16 provides the following description of flow chart.Yet as previously mentioned, Lu Youbiao module 16 can comprise any appropriate combination and the arrangement of unit.
Arbitration modules 20 has determined whether that in step 50 any search request is a current effective.For example, arbitration modules 20 can determine, arbitrary port one 2 is current is asking search operation.If not, then arbitration modules 20 has determined whether that in step 52 any aging request is effective.For example, arbitration modules can be periodically, sporadicly or at any other appropriate time produce aging request, removes expired inlet to provide from memory block 18 and to overflow temporarily the buffer 26.If not aging request is that effectively then arbitration modules 20 has determined whether that in step 54 any study request is effective.For example, arbitration modules 20 can determine whether that arbitrary port one 2 asked learning manipulation.If not, then flow process turns back to step 50.Thus, in step 50,52 and 54, arbitration modules 20 provides service for searching, wear out and learning to ask, simultaneously to the search request assigned highest priority.
If arbitration modules 20 detects search request in step 50, then arbitration modules 20 arranges one to search read operation in step 56.Arbitration modules 20 searches whether be used for multicast address what step 58 was determined to be arranged.For example, by checking the certain bits within this destination address, arbitration modules 20 can determine whether this address indicates the multicast operation.If then arbitration modules 20 is at any write operation of having arranged of step 60 cancellation.For example, interim in the last week, arbitration modules 20 may be arranged write operation, is used for study or delete command.If like this, arbitration modules 20 can be cancelled this write operation, fails to prevent the falseness during the read operation.In step 62, access module 22 carries out the operation arranged.At this moment, access module 22 has been arranged searches read operation, presets the write operation of then having arranged if any write operation keeps.
If do not detect search operation, then arbitration modules 20 is checked aging request in step 52.In case detect aging request, arbitration modules 22 is arranged an aging read operation in step 64.At this moment, the operation that access module 22 has been arranged in step 62, it comprises the aging read operation of having arranged.
Suppose effectively not search or aging request, then arbitration modules 20 can detect effectively study request in step 54.In case detect effective study request, arbitration modules 20 is determined the current write operation of whether having arranged in step 66.For example, interim in the last week, arbitration modules 20 may have been arranged write operation.Since router table means 16 attempt to prevent simultaneously write and learn read operation, arbitration modules 20 is checked write operation in step 66.If arranged write operation, then arbitration modules 20 turns back to step 50.Yet if do not arrange write operation, arbitration modules 20 is arranged a study read operation in step 68.The operation arranged in step 62 of access module 22 then, it comprises the study read operation of having arranged (not having write operation simultaneously).
After the operation of having arranged in step 62, arbitration modules 20 determines whether to detect the demand of writing in step 70.For example, after having carried out the study read operation, arbitration modules 20 need can determine a study write operation.If like this, arbitration modules 20 is arranged this write operation in step 72.In order to arrange write operation, arbitration modules 20 can be determined the suitable row within the memory block 18, is used to receive this routing iinformation.In specific environment, the row of being discerned may be full of current routing iinformation.Under such environment, if comprising, switch 10 overflows buffer 26, then arbitration modules 20 can be arranged write operation, is used for suitably overflowing the available position within the buffer 26.Thus, arbitration modules 20 can be arranged write operation, within the row that is used for being discerned or suitable overflow any available position (spot) within the buffer 26.Similarly, arbitration modules 20 can detect a deletion demand in step 70, arranges a write operation to carry out this deletion in step 72.
Aforementioned flowchart text router table means 16 example operation of routing table operation is provided based on the access of multibank memory structure.Yet aforementioned flow chart and associated description only illustrate the exemplary method of this operation, and switch 10 can be contemplated that router table means 16 utilizes any appropriate technology to support the multibank memory scheme.Thus, the many steps in this flow chart can take place simultaneously and/or with shown in different order take place.In addition, router table means 16 can use have additional step, the method for step and/or different step still less, as long as these methods are suitable.
Fig. 5 is the operational flowchart of explanation access module 22 when the service read request.In each cycle, access module 22 determines whether to receive read request in step 80.If not, then access module 22 does not carry out operation about read request during this cycle.If access module 22 detects read request in step 80, then access module 22 is determined hash key the address of step 82 within this read request.For example as previously mentioned, access module 22 can be determined hash key based on the selected bits within this address.
Utilize this hash key, access module 22 reads from corresponding row in step 84.As previously mentioned, this read operation is accessed in all positions 24 within the corresponding row, unless the current write operation simultaneously of having arranged.Access module 22 determines whether to be complementary with the address that receives from any inlet of this row in step 86.No matter whether exist synchronous write operation, access module 22 can determine all whether this address produces hits or fails.Yet during given synchronous write operation, access module 22 can detect false failure as previously mentioned.
During given coupling, access module 22 returns this coupling routing iinformation in step 88.For example, for searching read operation, access module 22 can provide routing iinformation to arrive proper port 12.Similarly, for the study read operation, access module 22 can this hits to arbitration modules 20 circulars.During given failure, access module 22 is in this failure of step 90 indication.For example, for searching read operation, access module 22 can be indicated this proper port 12 of failing.Similarly, for the study read operation, access module 22 can be indicated this arbitration modules 20 of failing.
Thus, aforementioned flowchart text access module 22 handle relative simple techniques from the read request of arbitration modules 20.Yet the same with first flow chart, this flow chart and associated description have only illustrated the exemplary method of operation, and switch 10 can be contemplated that access module 22 and/or other suitable assemblies utilize any suitable technique to come the access routing iinformation.Thus, the many steps in this flow chart can take place simultaneously and/or with shown in different order take place.In addition, switch 10 can use have additional step, still less step and/or different step ground method, as long as these methods are suitable.
Although the present invention is described in a plurality of embodiment, can advise various variations and remodeling to those skilled in the art, the present invention is intended to comprise these variations and the remodeling that falls within the claims scope.
Claims (22)
1. switch comprises:
A plurality of ports can be operated in order to transmit bag;
Switching fabric can be operated in order to transmit the bag that is received between described port;
A plurality of memory blocks are logically divided into a plurality of row, and wherein, each described row comprises the memory location from each described memory block, and the route inlet can be safeguarded in each described memory location;
Overflow buffer, comprise a plurality of memory locations of overflowing, the route inlet can be safeguarded in each described memory location of overflowing; And
Memory control module, can operate in order to from one of described port reception memorizer access request,, determine the particular row of described row with based on the indicated address of this memory access requests, and the indicated row of access and this overflow buffer, to carry out memory access operations.
2. switch as claimed in claim 1, wherein: this memory access requests request search operation, this memory control module can further be operated, in order to carry out this memory access operations as follows:
Overflow the potential route inlet of buffer reception from indicated row with from this;
This address and each described potential route inlet are compared; And
If one of this address and described potential route inlet are complementary, then return the indicated routing iinformation of this coupling inlet in the described potential route inlet.
3. switch as claimed in claim 1, wherein: the learning manipulation of routing iinformation is specified in this memory access requests request, and this memory control module can further be operated, in order to as follows to carry out this memory access operations:
Determine to have in the described memory location of indicated row each in indicated row effective route inlet;
Determine a described available memory location of overflowing of overflowing the memory location; And
This address and this routing iinformation are write this available overflowing in the storage device.
4. switch as claimed in claim 1, wherein this memory control module comprises:
Arbitration modules can be operated in order to receive search request and study request from described port, based on described search request and described study request, arranges a series of memory access operations; And
The storage access module, can operate in order to: for each described a series of memory access operations, determine hash key from the indicated address of each described a series of memory access operations, wherein, this hash key is indicated the particular row of described row; And access this overflow buffer and by the indicated described particular row of this hash key.
5. switch as claimed in claim 4, wherein: this arbitration modules is arranged memory access operations, with arranging memory access operations with before serving any uncompleted study request, serves any uncompleted search request.
6. switch as claimed in claim 4, wherein: in order to serve study request, this arbitration modules can operate in order to:
Arrange the first memory accessing operation, this first memory accessing operation comprises read operation, and this read operation indication is from the source address of this study request;
Determine whether this read operation detects failure at described memory block and described overflowing in the buffer; And
If detect this failure, then arrange the second memory accessing operation, this second memory accessing operation comprises write operation, this write operation indication is from the source address and the port mapping of this study request.
7. switch as claimed in claim 6, wherein: this arbitration modules can further be operated in order to guarantee that this first memory accessing operation does not contain any write operation.
8. switch as claimed in claim 1, wherein: this overflows buffer and comprises a plurality of memory cells.
9. interchanger as claimed in claim 8, wherein: each described memory cell is corresponding to described a plurality of row, this memory control module can further be operated in order to the indicated row of access and this and be overflowed buffer, with by the indicated row of access and with the corresponding one or more described memory cells of indicated row, carry out this memory access operations.
10. one kind is used to carry out the routing table method of operating, comprising:
Supervision is from the search request and the study request of any reception of a plurality of ports;
Detection contains the search request of destination address;
Determine hash key based on this destination address;
Utilize this hash key to come the access memory module, wherein, this memory module comprises a plurality of memory blocks that are logically divided into a plurality of row, wherein, each described row comprises the memory location from each described memory block, the route inlet can be safeguarded in each described memory location, and wherein, this hash key is indicated one of described row;
Buffer is overflowed in access, and this overflows buffer and comprises a plurality of memory locations of overflowing, and the route inlet can be safeguarded in each described memory location of overflowing;
Definite address information of mating that whether comprises from indicated row or from one of this described inlet that overflows buffer with this destination address;
If maybe this overflows buffer and comprises coupling inlet indicated row, then enter the mouth and return routing iinformation from this coupling, this routing iinformation is discerned one or more described ports.
11. method as claimed in claim 10 also comprises:
Detect the study request, this study request identification source address and routing iinformation;
Determine second hash key based on this source address;
Utilize this second hash key to come this memory module of access, wherein, this second hash key is indicated second row of described row.
12. method as claimed in claim 11 also comprises: guarantee that when utilizing this second hash key to come this memory module of access, described memory block does not carry out write operation.
13. method as claimed in claim 11 also comprises:
Determine whether one of the described inlet from the second indicated row comprises the address information that is complementary with this source address;
If described inlet does not all match, determine then whether the second indicated row comprises available memory location; And
If the second indicated row comprises available memory location, then this source address and this routing iinformation are written to this available storage location.
14. method as claimed in claim 11 also comprises:
Determine whether one of the described inlet from the second indicated row comprises the address information that is complementary with this source address;
If described inlet does not all match, determine then whether the second indicated row comprises available memory location; And
If indicated second does not capablely contain available memory location, then determine the available memory location of overflowing, this source address and this routing iinformation are written to this available memory location of overflowing.
15. method as claimed in claim 10 also comprises: any uncompleted search request of service before any uncompleted study request of service.
16. method as claimed in claim 10 also comprises: determine that this destination address is a multicast address, guarantee that correspondingly when utilizing this this memory module of hash key access, described memory block does not carry out write operation.
17. method as claimed in claim 10, also comprise: when utilizing this this memory module of hash key access, carry out write operation, this write operation is indicated specific of described memory location within the selected memory block of described memory block, wherein, by utilizing this this memory module of hash key access, read described inlet in the indicated row in all memory blocks from memory block indicated except this write operation.
18. a switch comprises:
Be used to monitor search request and the device of learning to ask from any reception of a plurality of ports;
Be used to detect the device of the search request that comprises destination address;
Be used for determining the device of hash key based on this destination address;
Be used to utilize the device of this hash key access memory module, wherein, this memory module comprises a plurality of memory blocks that are logically divided into a plurality of row, wherein, each described row comprises the memory location from each described memory block, the route inlet can be safeguarded in each described memory location, and wherein, this hash key is indicated one of described row;
Be used for access and overflow the device of buffer, this overflows buffer and comprises a plurality of memory locations of overflowing, and the route inlet can be safeguarded in each described memory location of overflowing;
Be used for determining from indicated row or whether comprise the device of the address information that is complementary with this destination address from one of this described inlet that overflows buffer;
Be used for that maybe this overflows buffer and comprises that when inlet coupling enters the mouth from this coupling and return the device of routing iinformation that this match information is discerned one or more described ports at indicated row.
19. switch as claimed in claim 18 also comprises:
Be used to detect the device of study request, this study request identification source address and routing iinformation;
Be used for determining the device of second hash key based on this source address;
Be used to utilize the device of this this memory module of second hash key access, wherein, this second hash key is indicated second row of described row.
20. switch as claimed in claim 19 also comprises: be used to guarantee that when utilizing this this memory module of second hash key access described memory block does not carry out the device of write operation.
21. switch as claimed in claim 19 also comprises:
Be used for determining whether one of described inlet from the second indicated row comprises the device with the address information of this source address matches;
Be used for when described inlet does not all match, determining whether the second indicated row comprises the device of available storage location; And
Be used for when the second indicated row comprises available storage location, this source address and this routing iinformation being written to the device of this available storage location.
22. switch as claimed in claim 19 also comprises:
Be used for determining whether one of described inlet from the second indicated row comprises the device with the address information of this source address matches;
Be used for when described inlet does not all match, determining whether the second indicated row comprises the device of available storage location; And
Be used for capablely determining when not containing available storage location available to overflow the memory location, this source address and this routing iinformation are written to this available device that overflows the memory location indicated second.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/783,065 | 2004-02-20 | ||
| US10/783,065 US7477639B2 (en) | 2003-02-07 | 2004-02-20 | High speed routing table learning and lookup |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1658597A true CN1658597A (en) | 2005-08-24 |
| CN100555985C CN100555985C (en) | 2009-10-28 |
Family
ID=35007850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100080882A Expired - Fee Related CN100555985C (en) | 2004-02-20 | 2005-02-16 | A kind of switch and routing table method of operating |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP4557745B2 (en) |
| CN (1) | CN100555985C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1794673B (en) * | 2005-12-27 | 2011-11-30 | 王卫亚 | Method of constructing local network using IP protocol |
| CN102273141A (en) * | 2009-01-12 | 2011-12-07 | 惠普开发有限公司 | Reducing propagation of message floods in computer networks |
| CN103098431A (en) * | 2010-09-14 | 2013-05-08 | 惠普发展公司，有限责任合伙企业 | Computer system fabric switch |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7873041B2 (en) | 2006-12-01 | 2011-01-18 | Electronics And Telecommunications Research Institute | Method and apparatus for searching forwarding table |
| JP4800415B2 (en) | 2009-08-17 | 2011-10-26 | 富士通株式会社 | Relay device and MAC address search method |
| US8856420B2 (en) * | 2011-12-27 | 2014-10-07 | Intel Corporation | Multi-protocol I/O interconnect flow control |
| JP6991446B2 (en) * | 2018-05-18 | 2022-01-12 | 日本電信電話株式会社 | Packet processing device and its memory access control method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3371006B2 (en) * | 1993-03-03 | 2003-01-27 | 株式会社日立製作所 | Table search method and router device |
| JP2002334114A (en) * | 2001-05-10 | 2002-11-22 | Allied Tereshisu Kk | Table management method and device |
-
2005
- 2005-02-16 CN CNB2005100080882A patent/CN100555985C/en not_active Expired - Fee Related
- 2005-02-17 JP JP2005040467A patent/JP4557745B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1794673B (en) * | 2005-12-27 | 2011-11-30 | 王卫亚 | Method of constructing local network using IP protocol |
| CN102273141A (en) * | 2009-01-12 | 2011-12-07 | 惠普开发有限公司 | Reducing propagation of message floods in computer networks |
| CN102273141B (en) * | 2009-01-12 | 2015-09-02 | 惠普开发有限公司 | Reduce the propagation of the message flooding in computer network |
| CN103098431A (en) * | 2010-09-14 | 2013-05-08 | 惠普发展公司，有限责任合伙企业 | Computer system fabric switch |
| CN103098431B (en) * | 2010-09-14 | 2016-03-23 | 惠普发展公司，有限责任合伙企业 | Computer Systems Organization switch |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4557745B2 (en) | 2010-10-06 |
| CN100555985C (en) | 2009-10-28 |
| JP2005236997A (en) | 2005-09-02 |
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