CN1655465A - Receiver gain balance compensation circuit and method therefor - Google Patents
Receiver gain balance compensation circuit and method therefor Download PDFInfo
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- CN1655465A CN1655465A CN 200410005349 CN200410005349A CN1655465A CN 1655465 A CN1655465 A CN 1655465A CN 200410005349 CN200410005349 CN 200410005349 CN 200410005349 A CN200410005349 A CN 200410005349A CN 1655465 A CN1655465 A CN 1655465A
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Abstract
This invention relates to receiver gain balance compensation circuit and its method, wherein, the receiver comprises one in-phase frequency circuit; one crossing frequency circuit; one gains balance compensation circuit, which comprises the following: one first circuit connected to the in-phase frequency circuit and the crossing frequency circuit modulation output end to provide one test signal to the in-phase frequency circuit and its crossing frequency circuit; one second circuit to receive the test result signals output by the in-phase frequency circuit and the crossing frequency circuit; adjusting the in-phase frequency circuit and the crossing frequency circuit amplifier gains according to the two test result signals errors of the in-phase circuit and the crossing frequency circuit.
Description
Technical field
The present invention is particularly to a kind of receiver gain balance compensating circuit and method thereof that is applied in the quadrature receiver relevant for a kind of receiver gain balance compensating circuit and method thereof.
Background technology
Fig. 1 represents a traditional quadrature receiver 10, it receives a transmission signals 101 (complexcommunication signal), through a pair of mixer 103,104, two groups of sine wave signals that differ 90 degree that itself and local oscillator (Localoscillator) produce coordinate respectively, form an in-phase signal 111 (in phase signal, claim I-channel again) and orthogonal signalling 112 (quadraturesignal, claim Q-channel again), this in-phase signal 111 and this orthogonal signalling 112 are again through the path filter 105 of correspondence, after 106 filtering, through fundamental frequency amplifier 107,108 in exporting 109 generation fundamental frequency in-phase signals and exporting after output 110 produces the fundamental frequency orthogonal signalling.
Under the ideal state, because path filter 105, fundamental frequency amplifier 107 and path filter 106, fundamental frequency amplifier 108 is the identical circuit of two covers, when so its I/Q gain (I/Q gain) is identical, fundamental frequency in-phase signal and its amplitude of fundamental frequency orthogonal signalling of corresponding output should be identical, yet because technology or the factor of temperature or the error of the endophyte signal of telecommunication that electric capacity causes in the integrated circuit fabrication process, can cause unbalance (imbalance) of homophase and quadrature (I/Q) gain, and so the unbalance meeting of I/Q gain increases bit error rate (bit error rate; BER) and reduce the usefulness of its receiving terminal of transmission system (for example GSM or WLAN).
Summary of the invention
In view of this, main purpose of the present invention is to provide one can provide automatic gain balanced compensated gain balance compensating circuit and method thereof.
For reaching aforementioned purpose, the invention provides a kind of receiver, it comprises: phase channel circuit together; One quadrature channel circuit; One gain balance compensating circuit comprises: one first circuit is connected to the demodulation output of this homophase channel circuit and this quadrature channel circuit, to provide a test signal to this homophase channel circuit and this quadrature channel circuit; And a second circuit, receive the test result signal of being exported by this homophase channel circuit and this quadrature channel circuit; Adjust amplifier gain in this homophase channel circuit and this quadrature channel circuit via an error calculation unit according to this two test results signal errors of this homophase channel circuit and this quadrature channel circuit, so that the test result signal of this homophase channel circuit is equal to the test result signal of this quadrature channel circuit.
The present invention also proposes a gain balance compensating circuit, be applicable to that tool is together on the receiver of phase channel circuit and a quadrature channel circuit, this gain balance compensating circuit comprises: one first circuit, be connected to the demodulation output of this homophase channel circuit and this quadrature channel circuit, to provide a test signal to this homophase channel circuit and this quadrature channel circuit; And a second circuit, receive the test result signal of being exported by this homophase channel circuit and this quadrature channel circuit; Adjust amplifier gain in this homophase channel circuit and this quadrature channel circuit via an error calculation unit according to this two test results signal errors of this homophase channel circuit and this quadrature channel circuit, so that the test result signal of this homophase channel circuit is equal to the test result signal of this quadrature channel circuit.
At last, the present invention provides a gain balance compensation method via above-mentioned gain balance compensating circuit, be applicable to that tool is together on the receiver of phase channel circuit and a quadrature channel circuit, this receiver comprises a gain balance compensating circuit, and this gain balance compensating circuit comprises one first circuit and a second circuit, this gain balance compensation method comprise (a) certainly this first circuit one test signal is provided, when an align mode, input in this homophase channel circuit and this quadrature channel circuit; (b) export a test result signal through this homophase channel circuit and this quadrature channel circuit; And (c) this second circuit receives the test result signal that this homophase channel circuit and this quadrature channel circuit are exported, adjust the amplifier gain of this homophase channel circuit and this quadrature channel circuit via an error calculation unit, so that the test result signal of this homophase channel circuit is equal to the test result signal of this quadrature channel circuit.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 represents the circuit block diagram of a conventional orthogonal receiver;
Fig. 2 represents the circuit box schematic diagram of a preferred embodiment of the present invention;
Fig. 3 represents the circuit box schematic diagram of another preferred embodiment of the present invention;
Fig. 4 represents the detailed circuit calcspar of a fundamental frequency amplifier.
Fig. 5 represents the gain error compensation method schematic flow sheet that carried out via above-mentioned test gain compensation circuit.
Fig. 6 represents the detailed step flow chart of step S3.
The related symbol explanation:
Quadrature receiver～100; Transmission signals～101; Mixer～103,104; In-phase signal～111; Orthogonal signalling～112; Path filter～105,106; Fundamental frequency amplifier～107,108; Output～109; Output～110; Receiver～2; Quadrature channel circuit～11; Homophase channel circuit～10; First circuit～20; Second circuit～21; Switch～S1; Switch～S2; Error calculation unit～22; Digital signal generator～200; First digital analog converter～201; Second digital analog converter～202; First analog/digital converter～210; Second analog/digital converter～211; Error calculation unit～22; Controller～212; The table of comparisons～213 are adjusted in gain; Coarse adjustment amplifying stage～30; Fine setting amplifying stage～31; Amplifier～300; Amplifier～310.
Embodiment
Fig. 2 represents the circuit box schematic diagram of a preferred embodiment of the present invention, and it represents a receiver 2, and this receiver 2 comprises together phase channel circuit 10, a quadrature channel circuit 11, one first circuit 20 and a second circuit 21.
This homophase channel circuit 10 has a mixer 103, have that an input can receive a transmission signals 101 when an accepting state and the in-phase signal smear that in addition produced with local oscillator 102 after export, one path filter 105 optionally is coupled to the output of this mixer 103 through a switch S 1 (first switch); One fundamental frequency amplifier 107 is connected to the output of this passage mixer 105.This quadrature channel circuit 11 also have a mixer 104 in order to the orthogonal signalling smear that is produced with local oscillator 102 after output, mixer 104 have an input and can receive a transmission signals 101, one path filter 106 optionally is coupled to the output of this mixer 106 through a switch S 2 (second switch); One fundamental frequency amplifier 108 is connected to the output of this passage mixer 106.
This first circuit 20 is connected to the demodulation output (being switch S 1 and S2) of this homophase channel circuit 10 and this quadrature channel circuit 11, to provide a test signal to this homophase channel circuit 10 and this quadrature channel circuit 11.
This second circuit 21 has an error calculation unit 22, and it receives the test result signal of being exported by this homophase channel circuit 10 and this quadrature channel circuit 11; The amplifier of adjusting in this homophase channel circuit 10 and this quadrature channel circuit 11 according to the error of this two test results signal of this homophase channel circuit 10 and this quadrature channel circuit 11 via error calculation unit 22 107,108 gains, so that the test result signal of this homophase channel circuit 10 is equal to the test result signal of this quadrature channel circuit 11.
During real work, in the time will carrying out gain compensation, switch S 1, S2 switch to the output of first circuit 20, and at first, this first circuit 20 provides test signal output to reach in this homophase channel circuit 10 and this quadrature channel circuit 11; Then, amplify in back output one test result signal and this quadrature channel circuit 11 path filter 106 filtering and after fundamental frequency amplifier 108 amplifies, export another test result signal via path filter 105 filtering of this homophase channel circuit 10 and through fundamental frequency amplifier 107.Two test result signals input in second circuit 21 conversion inputs one error calculation unit 22, this error calculation unit 22 is promptly calculated the error of two test result signals and is adjusted amplifier gain 107,108 in this homophase channel circuit 10 and this quadrature channel circuit 11 according to this error, so that the test result signal of this homophase channel circuit 10 is equal to the test result signal of this quadrature channel circuit 11.Program to be corrected finishes, and homophase channel circuit 10 and quadrature channel circuit 11 begin to carry out the function of its receiver, and make receiver operation in preferable usefulness according to the gain of the previous compensated amplifier of proofreading and correct as a result 107,108 this moment.
In addition, present embodiment has more a switch S 3 (the 3rd switch) and a switch S 4 (the 4th switch) is located at fundamental frequency amplifier output 107,108 and this second circuit is imported 21, alternative switching makes the input of this second circuit 21 be connected with this fundamental frequency amplifier 107,108 or is connected with these first circuit, 20 outputs, can carrying out calibrating for error of digital/analog converter, its detailed step in after repeat.
Fig. 3 represents the circuit box schematic diagram of another preferred embodiment of the present invention, its homophase channel circuit 10 and this quadrature channel circuit 11 internal circuits are all identical with last preferred embodiment, do not repeat them here, it mainly further introduces the detailed circuit in this first circuit 20 and the second circuit 21.
During real work, at first, digital signal generator 200 produces the test signal of set of numbers to this first digital analog converter 201 and this second digital analog converter 202, through converting the corresponding simulating signal to after switch S 1, S2 input in homophase channel circuit 10 and this quadrature channel circuit 11; Then, amplify path filter 106 filtering in back output one test result signal and this quadrature channel circuit 11 and after fundamental frequency amplifier 108 amplifies, export another test result signal via path filter 105 filtering of this homophase channel circuit 10 and through fundamental frequency amplifier 107, via controller 212 calculates corresponding error signal value form the first corresponding digital signal and second digital signal after changing after, the table of comparisons 213 is adjusted in gain can find corresponding yield value via this error signal value, error calculation unit 22 is promptly according to the fundamental frequency amplifier 107 of this yield value correspondence, 108 carry out gain controlling, make the test result signal of this homophase channel circuit 10 be equal to the test result signal of this quadrature channel circuit 11.
Being described in detail of gain controlling is for example shown in Figure 4, with single fundamental frequency amplifier 107 or 108 is example, it comprises a coarse adjustment amplifying stage 30 and a fine setting amplifying stage 31, this coarse adjustment amplifying stage 30 comprises a plurality of amplifiers 300, and respectively this amplifier 300 receives control bit (1bit) signal and is a job or an off state; Fine setting amplifying stage 31 comprises an amplifier 310, and this amplifier 310 receives n control bit signals (n-bit) and controls the gain of this amplifier 310.
During real work, when error calculation unit 22 one group of gain controlling word of output (word), these amplifiers 30,31 can promptly be exported after the overall gain value according to these series connection amplifiers 300,310 at last according to the state that is work or shutoff of the signal correspondence that receives.
Fig. 5 represents to comprise the gain error compensation method carried out via above-mentioned test gain compensation circuit:
Step S
1, carry out the analog/digital converter calibration steps; First analog-digital converter and second analog-digital converter be connected to (for example: ground connection) first analog-digital converter and one second analog-digital converter that a direct current signal (for example 0 volt voltage signal) is inputed in this second circuit exported corresponding digital signals after changing on the reference potential, error calculation unit is calculated according to this two digital signal to be exported in the error calculation unit after the first corresponding error amount makes and convert to corresponding digital signals, then, controller is calculated this error amount of error amount (first error amount) back record of A/D converter.
Then enter step S
2, carry out the digital/analog converter calibration steps; First digital analog converter and the output of this second digital analog converter are connected directly on the input of first analog-digital converter and second analog-digital converter switch S 3 and S4 switching, export by digital signal generator then and export in the error calculation unit this second error amount of record after this controller deducts this first error amount respectively promptly to calculate one second error amount a test signal converts corresponding digital signals to behind first digital analog converter and this second digital analog converter and this first analog-digital converter and this second analog-digital converter after to.
At last, step S
3Carry out the gain compensation step of homophase channel circuit and quadrature channel circuit, being about to this first digital analog converter and this second digital analog converter is coupled on the output of two mixers, and the test signal that produces set of number by number generator is to reaching behind the filter of homophase channel circuit and quadrature channel circuit and fundamental frequency amplifier through two digital analog converters in the controller that two analog-digital converters input to error calculation unit again, controller is calculated and is deducted the correct error amount (the 4th error amount) that first error amount and this second error amount can obtain homophase channel circuit and quadrature channel circuit behind the error amount (the 3rd error amount) again, use the amplifier gain of adjusting this homophase channel circuit and this quadrature channel circuit, so that the test result signal of this homophase channel circuit is equal to the test result signal of this quadrature channel circuit.
Fig. 6 represents step S
3Detailed step, comprising:
Step S
3.1In, enter align mode, switch S 1 and switch S 2 switchings are connected to the output of first circuit, make this first circuit that one group of test signal is provided, and input in this homophase channel circuit and this quadrature channel circuit.
Then, enter step S
3.2, through the filtering of this homophase channel circuit and this quadrature channel circuit and amplify the back and export a test result signal.
At last, enter step S
3.3, this second circuit receives the test result signal that this homophase channel circuit and this quadrature channel circuit are exported, and calculates above-mentioned the 3rd error amount via an error calculation unit.
In sum; though the present invention with a preferred embodiment openly as above; right its is not in order to limit the present invention; any those skilled in the art; under the situation that does not break away from the spirit and scope of the present invention; can carry out various changes and modification, so protection scope of the present invention is as the criterion when looking the claim restricted portion that is proposed.
Claims (24)
1. a receiver comprises:
Phase channel circuit together;
One quadrature channel circuit;
One gain balance compensating circuit comprises:
One first circuit is connected to the demodulation output of this homophase channel circuit and this quadrature channel circuit, to provide a test signal to this homophase channel circuit and this quadrature channel circuit; And
One second circuit receives the test result signal of being exported by this homophase channel circuit and this quadrature channel circuit; Adjust amplifier gain in this homophase channel circuit and this quadrature channel circuit via an error calculation unit according to this two test results signal errors of this homophase channel circuit and this quadrature channel circuit, so that the test result signal of this homophase channel circuit is equal to the test result signal of this quadrature channel circuit.
2. receiver as claimed in claim 1, wherein:
This homophase channel circuit comprises:
One mixer;
One path filter is connected to the output of this mixer; And
One fundamental frequency amplifier is coupled to the output of this path filter;
This quadrature channel circuit comprises:
One mixer;
One path filter is connected to the output of this mixer; And
One fundamental frequency amplifier is coupled to the output of this path filter.
3. receiver as claimed in claim 2, wherein this first circuit comprises a digital signal generator, in order to produce this test signal.
4. receiver as claimed in claim 3, wherein this first circuit also comprises:
One first digital/analog converter is coupled to this digital signal generator, and output is coupled to the output of this mixer of this homophase channel circuit; And
One second digital/analog converter is coupled on this digital signal generator, and output is coupled to the output of this mixer of this quadrature channel circuit.
5. receiver as claimed in claim 4, it also comprises:
One first switch is located between the mixer and path filter of this homophase channel circuit, and alternative the switching makes the input of this path filter be connected with this mixer or be connected with this first digital/analog converter; And
One second switch is located between the mixer and path filter of this quadrature channel circuit, and alternative the switching makes the input of this path filter be connected with this mixer or be connected with this first digital/analog converter.
6. receiver as claimed in claim 2, wherein this second circuit comprises:
The fundamental frequency amplifier out that one first analog/digital converter is coupled to this homophase channel circuit is with the test result signal that receives this homophase channel circuit and exported and first digital signal of conversion output one correspondence; And
The fundamental frequency amplifier out that one second analog/digital converter is coupled to this quadrature channel circuit is with the test result signal that receives this quadrature channel circuit and exported and export one second digital signal.
7. receiver as claimed in claim 6, wherein this error calculation unit comprises:
One controller is exported an error signal value in the back as calculated in order to receive by this first digital signal and this second digital signal;
The one gain table of comparisons receives this error signal value and points to the yield value of a correspondence and carry out gain controlling with the amplifying unit to correspondence.
8. receiver as claimed in claim 2, wherein respectively this fundamental frequency amplifier also comprises a coarse adjustment amplifying stage and a fine setting amplifying stage.
9. receiver as claimed in claim 8, wherein this coarse adjustment amplifying stage comprises a plurality of amplifiers, respectively this amplifier receives a control bit signal and is a job or an off state.
10. receiver as claimed in claim 8, wherein this fine setting amplifying stage comprises an amplifier, this amplifier receives n control bit signal and controls this Amplifier Gain.
11. receiver as claimed in claim 8 wherein more comprises the input that the output of this first digital/analog converter is coupled to this first analog digital generator; And the output of this second digital/analog converter is coupled to the input of this second analog digital generator.
12. receiver as claimed in claim 11 wherein more comprises:
One the 3rd switch, be located between the output of fundamental frequency amplifier and this first analog digital generator of this homophase channel circuit, the alternative switching makes the input of this first analog digital generator be connected with this fundamental frequency amplifier or be connected with this first digital analog converter;
One the 4th switch, be located between the output of fundamental frequency amplifier and this second analog digital generator of this quadrature channel circuit, the alternative switching makes the input of this second analog digital generator be connected with this fundamental frequency amplifier or be connected with this second digital analog converter.
13. a gain balance compensating circuit is applicable to that on the receiver of a tool homophase channel circuit and a quadrature channel circuit, this gain balance compensating circuit comprises:
One first circuit is connected to the demodulation output of this homophase channel circuit and this quadrature channel circuit, to provide a test signal to this homophase channel circuit and this quadrature channel circuit; And
One second circuit receives the test result signal of being exported by this homophase channel circuit and this quadrature channel circuit; Adjust amplifier gain in this homophase channel circuit and this quadrature channel circuit via an error calculation unit according to this two test results signal errors of this homophase channel circuit and this quadrature channel circuit, so that the test result signal of this homophase channel circuit is equal to the test result signal of this quadrature channel circuit.
14. gain balance compensating circuit as claimed in claim 13, wherein:
This homophase channel circuit comprises:
One mixer;
One path filter is connected to the output of this mixer; And
One fundamental frequency amplifier is coupled to the output of this path filter;
This quadrature channel circuit comprises:
One mixer;
One path filter is connected to the output of this mixer; And
One fundamental frequency amplifier is coupled to the output of this path filter.
15. gain balance compensating circuit as claimed in claim 14, wherein this first circuit comprises a digital signal generator, in order to produce this test signal.
16. gain balance compensating circuit as claimed in claim 15, wherein this first circuit also comprises:
One first digital/analog converter is coupled to this digital signal generator, and output is coupled to the output of this mixer of this homophase channel circuit; And
One second digital/analog converter is coupled on this digital signal generator, and output is coupled to the output of this mixer of this quadrature channel circuit.
17. gain balance compensating circuit as claimed in claim 16, it also comprises:
One first switch is located between the mixer and path filter of this homophase channel circuit, and alternative the switching makes the input of this path filter be connected with this mixer or be connected with this first digital/analog converter; And
One second switch is located between the mixer and path filter of this quadrature channel circuit, and alternative the switching makes the input of this path filter be connected with this mixer or be connected with this first digital/analog converter.
18. gain balance compensating circuit as claimed in claim 13, wherein this error calculation unit comprises:
One controller is exported an error signal value in the back as calculated in order to receive by this first digital signal and this second digital signal;
The one gain table of comparisons receives this error signal value and points to the yield value of a correspondence and carry out gain controlling with the amplifying unit to correspondence.
19. gain balance compensation method, be applicable on the receiver of a tool homophase channel circuit and a quadrature channel circuit, this receiver comprises a gain balance compensating circuit, and this gain balance compensating circuit comprises one first circuit and a second circuit, and this gain balance compensation method comprises:
(a) this first circuit provides a test signal certainly, inputs to when an align mode in this homophase channel circuit and this quadrature channel circuit;
(b) export a test result signal through this homophase channel circuit and this quadrature channel circuit; And
(c) this second circuit receives the test result signal that this homophase channel circuit and this quadrature channel circuit are exported, adjust the amplifier gain of this homophase channel circuit and this quadrature channel circuit via an error calculation unit, so that the test result signal of this homophase channel circuit is equal to the test result signal of this quadrature channel circuit.
20. gain balance compensation method as claimed in claim 19 is wherein being carried out this step (a) before, also comprises:
(a.1) carry out analog-digital converter and calibrate for error, calculate the error of first analog/digital converter and second analog/digital converter in the second circuit, produce one first error amount; And
(a.2) carry out digital analog converter and calibrate for error, calculate the error of first digital/analog converter and second digital/analog converter in first circuit, produce one second error amount.
21. gain balance compensation method as claimed in claim 20 also comprises in step (c):
This second circuit receives test result signal that this homophase channel circuit and this quadrature channel circuit exported and measures after the aggregated error value of this receiver behind this first error amount of deduction and this second error amount, obtains the correct error amount of this homophase channel circuit and this quadrature channel circuit.
22. gain balance compensation method as claimed in claim 20 wherein in this step (a.1), comprising:
Provide a direct current signal to first analog-digital converter and one second analog-digital converter in this second circuit after changing, to export corresponding digital signals, make error calculation unit calculate this corresponding first error amount according to this two digital signal.
23. gain balance compensation method as claimed in claim 20 wherein in this step (a.2), comprising:
Produce first digital analog converter and this second digital analog converter of a test signal in first circuit and change, after this error module calculates, export this second error amount after first analog-digital converter in this second circuit and one second analog-digital converter are changed the corresponding digital signal of output.
24. gain balance compensation method as claimed in claim 21, wherein in this step (c), wherein this aggregated error value is one the 3rd error amount, and this correct error amount is one the 4th error amount, and this step (c) comprising:
Producing first digital analog converter and this second digital analog converter of a test signal in first circuit changes after this homophase channel circuit and this quadrature channel circuit export in the second circuit, after exporting the 3rd error amount of calculating correspondence after the digital signal of correspondence, deduct this first error amount and this second error amount again, this first analog-digital converter and the conversion of one second analog-digital converter produce the 4th error amount.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410005349 CN1655465A (en) | 2004-02-11 | 2004-02-11 | Receiver gain balance compensation circuit and method therefor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410005349 CN1655465A (en) | 2004-02-11 | 2004-02-11 | Receiver gain balance compensation circuit and method therefor |
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| CN1655465A true CN1655465A (en) | 2005-08-17 |
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| CN 200410005349 Pending CN1655465A (en) | 2004-02-11 | 2004-02-11 | Receiver gain balance compensation circuit and method therefor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101989862B (en) * | 2009-08-05 | 2014-08-06 | 立积电子股份有限公司 | Receiver and method for receiving wireless signal |
| CN105471779A (en) * | 2015-12-08 | 2016-04-06 | 扬智科技股份有限公司 | Correction method and correction circuit |
| CN105471780A (en) * | 2015-12-08 | 2016-04-06 | 扬智科技股份有限公司 | Correction method and correction circuit |
-
2004
- 2004-02-11 CN CN 200410005349 patent/CN1655465A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101989862B (en) * | 2009-08-05 | 2014-08-06 | 立积电子股份有限公司 | Receiver and method for receiving wireless signal |
| CN105471779A (en) * | 2015-12-08 | 2016-04-06 | 扬智科技股份有限公司 | Correction method and correction circuit |
| CN105471780A (en) * | 2015-12-08 | 2016-04-06 | 扬智科技股份有限公司 | Correction method and correction circuit |
| CN105471779B (en) * | 2015-12-08 | 2018-08-31 | 扬智科技股份有限公司 | Bearing calibration and correcting circuit |
| CN105471780B (en) * | 2015-12-08 | 2018-08-31 | 扬智科技股份有限公司 | Bearing calibration and correcting circuit |
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