CN1645338A - Single-chip analog system with multi-processor structure - Google Patents
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Abstract
An analog system of single chip-multiple processor structure is featured as connecting general control module separately to preprocessing module, core generating module and test verification module; connecting the preprocessing module simultaneously to core generating module and test verification module; connecting the core generating module to frame structure of CMP system on output module and connecting the test verification module to test verification report of output module.
Description
Technical field
The invention belongs to computer simulation and simulation technical field, the simulation and the evaluation and test of particularly extendible chip multiprocessors system.
Background technology
The key index of weighing a microprocessor performance index comprises dominant frequency, power consumption and communication speed.In order to make processor reach the new high degree of power consumption and performance Perfect Matchings, one of method is to adopt multithreading, promptly carries out the method for a plurality of independently instruction sequences in processor simultaneously, increases the resource utilization of unit interval inner treater.Chip multiprocessors (CMP-Chip Multi-Processor) structure just is being based on this thought and is proposing, promptly chip internal integrated a plurality of processor cores, each thread is assigned to each smoothly handles in the kernel, thus the handling capacity of raising microprocessor task in the unit interval.Because CMP system architecture microprocessor has steering logic simple, work dominant frequency height and the very low characteristics of inter-processor communication delay, this makes it become the effective way of current raising microprocessor performance, will be widely used in embedded processing systems and high-performance computing sector.At present, external how tame scientific research institution and company all study the chip multiprocessors project widely, and this type of research is the focus of system architecture research.But, at present for how existing processor cores being cut out (content comprises the improvement of instruction set, the adjustment of cache structure, the processing of global abnormal treatment mechanism etc.), make it to become autonomous, keep collaborative mutually multiple processor cores again, to adapt to the practical application function, thereby on to greatest extent, improve on the performance of processor system, also lack corresponding research.
The basic reason of the problems referred to above is to fail to estimate from the angle of system the performance index of CMP.The CMP system architecture itself has very strong singularity: the current Standard test programme that is used to estimate microprocessor performance, owing to can't correctly assess the performance of a plurality of processor cores and can't be applicable to the performance index of evaluating and testing CMP; Similar reason, based on the evaluating mechanism of multi-processor structure because and system bottleneck---the communication delay difference (the former is between the processor, and the latter is between processor and the external unit) of CMP, also can't correctly weigh its performance index.Therefore, must formulate the benchmark evaluating standard, set up corresponding evaluating mechanism, can correctly estimate the advantage and the scope of application of CMP system architecture.
In the design and realization technology of micro-processor architecture, the software simulation method is address the above problem main, also is effective method.Design high configurable, a reusable software simulation system, can shorten the time of hardware design and corresponding debugging software exploitation greatly, and provide quick checking and evaluation for the decision-making of architecture.In the technology of simulation system design, require transplantability good on the one hand, can provide united frame for different instruction set, different pipeline organizations; Require to have high simulated performance and efficient on the other hand.For the chip multiprocessors system---the coarse grain parallelism system of this employing Thread-Level Parallelism, extensibility need the problem of consideration emphatically.
Because chip multiprocessors requires to have the characteristics that good, the automatic generative capacity of extensibility is strong and dirigibility is good, also more or less there is defective in the simulation system of most of chip multiprocessors to this, such as the simplemp of Wei Sikang star university research and development, the simsmt of branch school, Santiago, University of California research and development, the simulation mechanism that does not all have the accurate simulation mechanism of parts signal level and accurately interrupt; The reusable mechanism that does not also have component-level, thus when streamline changed, the dirigibility of total system was relatively poor.For another example for general microprocessor Design, the design of high-speed cache is vital, and for the different configuration of different application needs could The Gift of Being the Best You Can Be the ratio of performance to price, so under which kind of situation how configuring high speed caching be chip multiprocessors the problem that will directly face; In addition, different application also has big gap for the requirement of microprocessor computing power, but because chip multiprocessors transaction module difference is little, therefore selecting which kind of processor cores for use in the chip multiprocessors and adopting how many kernels is rationally and effectively, just one of needs can generate fast different processor type and number thereof, flexibly, configurable simulation system tests and weighs.
Summary of the invention
The present invention is directed to the Behavior modeling and the performance evaluating problem of chip multiprocessors, a kind of single-chip analog system with multi-processor structure (the English SimCMP of abbreviation) is proposed, it is with various types of signal in the microprocessor, parts are mapped among the object and method in the software systems one by one, simultaneously in design process, in order to adapt to portability, the design requirement of multi-person synergy exploitation debugging, defined and had conformity specification, implementation method towards parts, have high configurability and portable good characteristics, make the whole software system have good modularization, readability and transplantability.The present invention can shorten the time of hardware design and software development greatly, and provides quick checking and evaluation for the decision-making of architecture.
A kind of single-chip analog system with multi-processor structure that the present invention proposes is characterized in that, mainly comprises:
Top control module; Be used to make up the CMP system structural framework;
Pretreatment module: be used for generating the user and wish various signals of the CMP that generates and definition;
Kernel generation module: the micro-processor kernel that is used for generating the CMP system framework;
Testing authentication module: be used for the setting of various test modes;
The output module of forming by CMP system structural framework and testing authentication report: be used for the system structural framework that according to user definition customization generates chip multiprocessors, and according to user's test case generation test report;
The annexation of each module is: this top control module links to each other with pretreatment module, kernel generation module, testing authentication module respectively, this pretreatment module links to each other with the testing authentication module with the kernel generation module simultaneously, this kernel generation module links to each other with the CMP system structural framework of output module, and this testing authentication module links to each other with the testing authentication report of output module.
Characteristics of the present invention and technique effect:
A kind of single-chip analog system with multi-processor structure that the present invention proposes (is a single-chip analog system with multi-processor structure, the English SimCMP that is called for short), it is mapped to various types of signal, parts in the microprocessor among the object and method in the software systems one by one, simultaneously in design process, in order to adapt to the design requirement of portability, multi-person synergy exploitation debugging, defined have conformity specification, towards the implementation method of parts, have high configurability and portable good characteristics, make total system have good modularization, readability and transplantability.Having adopted in its realization can be from expansion, configurable, reusable Design Mode.Simultaneously, in order to realize the parallel running of analog hardware parts, also proposed simulation system define method and component update method respectively and guaranteed that analog hardware carries out under the prerequisite of correctness, acquisition is than higher execution efficient, wherein, the simulation system define method is irrelevant towards parts, system architecture, and the component update method has then adopted the incident method of driving.
Utilize this phantom frame can write, realize and expand the system structural framework of chip multiprocessors easily and it is carried out performance evaluating.
System of the present invention adopts on the microcomputer of Windows operating system or workstation in the Visual C++ environment and develops, and makes full use of OO software design approach and realizes.Its main innovative point is as follows:
1) adopt the good framework structure, very convenient to the definition of micro-processor kernel, extensibility is good;
2) use event driven component update method, guarantee the efficient and the reliability of system;
3) to each inner core in the system, same or analogous place only need define once, and program frame can generate other core component and signal automatically by configuration;
4) communication mechanism between microprocessor can define and revise flexibly, can pass through storage organization (storage organization of different stage is shared) or interrupt mechanism and realize.Can realize the expansion of system easily and to the support of operating system or general watchdog routine.
Description of drawings
Fig. 1 is a system global structure block diagram of the present invention.
Fig. 2 is a system works flow process block diagram of the present invention.
The parts group technology that Fig. 3 proposes for the present invention.
The periodic signal update method that Fig. 4 proposes for the present invention.
Fig. 5 is testing authentication operation interface figure of the present invention.
Fig. 6 is the system construction drawing that utilizes the chip multiprocessors with two processor cores that the present invention generates.
Embodiment
The single-chip analog system with multi-processor structure that the present invention proposes reaches embodiment in conjunction with the accompanying drawings and further specifies as follows:
Simulation system of the present invention mainly comprises top control module, pretreatment module, the kernel generation module, testing authentication module and five parts of output module of forming by CMP system structural framework and testing authentication report, as shown in Figure 1, the annexation of each module is: this top control module respectively with pretreatment module, the kernel generation module, the testing authentication module links to each other, this pretreatment module links to each other with the testing authentication module with the kernel generation module simultaneously, this kernel generation module links to each other with the CMP system structural framework of output module, and this testing authentication module links to each other with the testing authentication report of output module.
The workflow of simulation system of the present invention as shown in Figure 2.May further comprise the steps:
(1) load instructions and program block are set up virtual interface and peripheral components, to make up basic microprocessor system structure;
(2) little processing kernel and the annexation thereof among definition and the generation CMP;
(3) system state is carried out initialization: comprise the initialization of program, the initialization of parts and CPU original state assignment;
(4) pre-service defines and realizes each parts and coherent signal;
(5) judge whether to carry out testing authentication, if, then load test and verify program, obtain the testing authentication report, and judge whether to satisfy user's designing requirement;
(6) if do not need testing authentication, then directly judge whether to satisfy user's designing requirement, then revise if not to return after system architecture defines and carry out (2) step;
(7) if meet the demands, the CMP system structural framework description that has defined is write file and preservation, finish the definition of CMP system structural framework.
The function and the specific implementation embodiment that realize each module in the simulation system of above-mentioned workflow are described in detail as follows:
Top control module: top control module among workflow of the present invention, is responsible for making up the CMP system structural framework from start to finish.The function that specifically comprises has:
(1) instruction sequence or the program block that load of control system, the realization of this function comprises instruction sequence and the program block file is finished by opening;
(2) finish the initialization of above-mentioned whole working routine, this function is so long as by the initialization that each parts are carried out and the assignment of CPU original state, and parameter value is fixing default default value;
(3) virtual interface is set up and peripheral components simulation realization, and this function realizes that by calling default routine interface routine interface leaves in the database and can directly call;
(4) be responsible for finishing the loading procedure of proving program or instruction sequence, this function implementation procedure is to utilize visualization interface, comprises by opening that instruction sequence and program block file finish;
(5) generation and the testing authentication process of control chip multiprocessors structure, this function realize finishing by insert breakpoint in program.
Pretreatment module: be responsible for the parts and the signal of single-chip processor inside are separated definition with the outside parts of single-chip processor nuclear with signal, the user only need define at visual Subscriber Interface Module SIM, just can generate various signals and definition among the CMP that the user wishes to generate by pretreatment module, this provides dirigibility to greatest extent when being avoided the duplication of labour.
When the different micro-processor architecture of design flow line structure, comprise when instruction set changed, the framework of software simulation system does not need to do change, and the parts definition, the signal definition that need change to be correlated with can be by moving the definition that preprocessor will be revised.
In pretreatment module, as follows to the specific embodiment of the definition mode of each parts:
The parts in the single-chip microprocessor core, so long as the same parts that all processors contain, definition adopts the .DEF file to carry out, and generates each micro-processor kernel by precompiler before compiling, and its main purpose is the form of convenient modification and unified Definition.And the form and the hardware description language of definition are similar, thereby can realize the transplanting from the software simulation system to hardware description language easily.The definition of parts comprises component, variable and three territories of Execute, and the form of definition is as follows:
[component] territory:
Comprise five subdomains, NAME, TYPE, INPUT, OUTPUT, CORETYPE:
The NAME subdomain is represented the title of these parts;
The TYPE subdomain is represented the type of these parts, comprises combinational logic (combination), sequential logic (sequence);
Input is indicated with INPUT and OUTPUT, all signals or input signal, or output signal;
All input signals are to indicate that form is with INPUT:
The INPUT=signal name
All output signals are to indicate that form is with OUTPUT:
The OUTPUT=signal name
The kernel attribute of all parts defines with CORETYPE, and form is:
CORETYPE=kernel attribute
The kernel attribute of having represented parts---belong to the same parts that a specific processor still belongs to all processors.
[Variable] territory:
The employed variable of main these parts of definition, the grammer of definition is with the grammer of programming language C++.
[Execute] territory:
Be defined in CPU operation time, the logic behavior when parts are performed, i.e. these parts of each cycle task of need finishing.
With the simplest CLZO parts of definition is example: the CLZO functions of components is to calculate 0 or 1 number of the beginning part among the word, and the name of parts i.e. " CLZO ".The input/output signal of parts has three, and one is operand, and one is control signal, and one is the output result.The type of parts is the combinational logic type.The work that these parts are finished in one-period is the indication (indicate calculate leading 1 or leading 0) according to the control model, and leading 1/0 number of calculating operation number is put the output result then.
The kernel generation module: be responsible for generating the micro-processor kernel in the CMP system framework, the user can select to generate the micro-processor kernel of appointment, also can generate the little processing kernel with specific function by customization.The kernel generation module comprises two subdata bases: micro-processor kernel storehouse and particular component storehouse.Utilize the present invention will generate the processor cores that chip multiprocessors comprises like this according to user's demand customization.
This kernel generation module is in the different single-chip micro-kernel number of simulation during with different pipeline organization, customizable following six the aspect contents of user:
(1) number of single-chip micro-processor kernel;
(2) the kernel attribute of parts in the micro-processor kernel;
(3) the peculiar parts of special micro-processor kernel;
(4) result of the control section of streamline and instruction decode;
(5) outer parts and the signal message of chip multiprocessors kernel;
(6) connection, the communication mode between each kernel of chip multiprocessors.
After the user has determined needed micro-processor kernel, kernel generation module of the present invention is realized the parallel running of analog hardware parts by simulation system define method and component update method, simultaneously, also guarantee to obtain than higher execution efficient under the prerequisite of analog hardware execution correctness.Wherein, the simulation system define method is irrelevant towards parts, system architecture, and the component update method has then adopted the incident method of driving.The principle of this method is: only upgrade a series of parts that the existence input changes, the parts that input did not have to change in a clock period are not then carried out the computing renewal, and this makes efficient of carrying out improve greatly.Simultaneously the execution precedence relationship of parts is sorted automatically by this method, need artificially not specify when the definition of architecture, thereby reduce the workload of simulation system logical design, and this has also accomplished can not produce the verification that " circulation " influences circuit simultaneously.
The simulation system define method of employing of the present invention and component update method, their embodiment is respectively parts group technology and periodic signal update method.
Each streamline beat component update method, parts group technology embodiment such as the flow process of promptly simulating a beat of CPU operation are shown in Figure 3, may further comprise the steps:
(1) generates an abort signal tabulation ListEnd;
(2) check that the output of all parts is whether in tabulation;
(3) if in tabulation, check next parts, otherwise, will lose to join and organize 0, its signal adds ends tabulation;
(4) if traveled through all parts, enter into next step, otherwise, changed for second step over to;
(5) check whether also have remainder;
(6), then finish if there is not remainder; Otherwise increase is organized, and the output signal of all parts is added ListEnd, and output signal is current group of preceding group of adding that loses input signal, finishes.
Periodic signal update method embodiment such as flow process are shown in Figure 4, and workflow is as follows:
(1) signal that finds all in beat, to change;
(2) find the parts that signal influenced that change in the beat, and join the execution tabulation;
(3) according to the order of group number handle successively each the group in parts;
(4) judge whether all latchs have stop or clear signal effective;
(5) if effectively, keep initial value or empty signal, otherwise, upgrade latch, finish.
Testing authentication module: be responsible for the setting of various test modes: information such as the type of the parts (high-speed cache, register, TLB) that need follow the tracks of, content.The operation interface of testing authentication comprises two micro-processor kernels as shown in Figure 5 in the interface, each functions of components following (following according to the description of number in the figure order) in the interface:
1. open a CMP system structural framework;
2. show CMP system structural framework running state information according to user's request;
3. online help file system, the information of offering help;
4. test single micro-processor kernel;
5. micro-processor kernel once moves the instruction stream that comprises many instructions;
6. test the CMP system structural framework;
7. test the shortcut button of single micro-processor kernel;
8. the shortcut button that single step is followed the tracks of is set;
9. setting program moves the shortcut button of breakpoint;
10. the register current information that shows a micro-processor kernel in the CMP system structural framework;
11. show the signal condition information of a micro-processor kernel in the CMP system structural framework;
12. show the segment register information of a micro-processor kernel in the CMP system structural framework;
13. display memory status information;
14. show the segment register information of another micro-processor kernel in the CMP system structural framework;
15. show the signal condition information of another micro-processor kernel in the CMP system structural framework;
16. show the register current information of another micro-processor kernel in the CMP system structural framework;
17. open the shortcut button of a CMP system structural framework.
By close friend's visualization interface, provide an automatic configurable user interface to the user.In the process of operation, can see the state of all parts, signal in each cycle that microprocessor carries out by this interface easily, can by breakpoint be set, revise internal memory, register or other data, control signal is debugged program.After program is finished, can obtain the trace file of corresponding performance parameter and register, Cache, main memory, TLB.The concrete workflow of testing authentication module embodiment is as follows:
(1) calls in a CMP system structural framework;
(2) call in a test procedure;
The step-length of (3) debugging is set, following the tracks of, default step-length is 1;
(4) program brings into operation, debugging, tracking CMP system running state information;
(5) by the visualization interface setting, revise the information of internal memory, Cache, register, TLB, the observing system running status;
(6) Debugging message of the automatic recording user of system;
(7) program run finishes.
The realization of testing authentication module is finished by true-time operation, after the user is provided with order, under the control of total control module, when system structural framework runs to the position of satisfying user's setting, the testing authentication module is by being provided with breakpoint in framework, calling program can be suspended, and corresponding intermediate result is reflected in the operation interface, debug use for the user.
Output module
Comprise CMP system structural framework and testing authentication report.Wherein, the CMP system structural framework is the system structural framework of the chip multiprocessors that customization generates according to user definition, in the generative process of system structural framework, simulation system basis of the present invention is mutual with the user's, the part programs of being confirmed is write in the file, for example when the user had selected a micro-processor kernel, simulation system was extracted the program code of this kernel automatically from database, and with in its writing system structural framing file; The testing authentication report then is on said system structural framing basis, test case according to the user produces test report, this test report generates journal file automatically by testing authentication module of the present invention, the generation of journal file is based on as Fig. 5, according to user's order, automatically the intermediateness structure that test command, system structural framework is in operation by system, final operation result are written to successively realizes in the file that this test report is in order to estimate the quality of the CMP system architecture that is generated.
The applicating example of the single-chip analog system with multi-processor structure that the present invention proposes is described as follows:
Fig. 6 is a system construction drawing with chip multiprocessors of two processor cores, and this chip multiprocessors system framework is generated by the chip multiprocessors structural simulation device that the present invention proposes.
The chip multiprocessors that has two kernels with Fig. 6 is an example, by the start address (in simulation system) that different core is set, illustrates that the system performance that adopts single-chip analog system with multi-processor structure to obtain promotes.Wherein, to have used dimension be that 16 one-dimension array is carried out quicksort to the Quick application program; The EightQueen application program has realized that classical eight queens problem finds the solution; The Hanoi application program has realized that hanoi tower problem finds the solution.
| Filename | Core indicates | Application name | The operation week issue | Total periodicity |
| Base&Hanoi.cod | ?A | ?Base | ?482 | ?3255 |
| ?B | ?Hanoi | ?3255 | ||
| Base&Quick.cod | ?A | ?Base | ?519 | ?74594 |
| ?B | ?Quick | ?74594 | ||
| Base&EightQueen | ?A | ?Base | ?498 | ?1026611 |
| ?B | ?EightQueen | ?1026611 | ||
| Base&Hanoi.cod | ?A | ?Hanoi | ?2607 | ?2607 |
| ?B | ?Base | ?567 | ||
| Base&Quick.cod | ?A | ?Quick | ?54676 | ?54676 |
| ?B | ?Base | ?581 | ||
| Base&EightQueen | ?A | ?EightQueen | ?733204 | ?733204 |
| ?B | ?Base | ?579 | ||
| Hanoi&Quick.cod | ?A | ?Hanoi | ?2966 | ?74794 |
| ?B | ?Quick | ?74794 | ||
| Hanoi&EightQueen | ?A | ?Hanoi | ?3142 | ?1026711 |
| B | ?EightQueen | ?1026711 | ||
| ?Hanoi&Quick.cod | A | ?Quick | ?55054 | ?55054 |
| B | ?Hanoi | ?312 | ||
| ?Hanoi&EightQueen | A | ?EightQueen | ?733673 | ?733673 |
| B | ?Hanoi | ?3435 | ||
| ?Quick&EightQueen.cc | A | ?Quick | ?58908 | ?1025276 |
| B | ?EightQueen | ?1025276 | ||
| ?Quick&EightQueen.cc | A | ?EightQueen | ?742473 | ?742473 |
| B | ?Quick | ?66095 |
In the table: represent when core is denoted as A that core A runs application program, core B is motionless; Vice versa.
Claims (1)
1, a kind of single-chip analog system with multi-processor structure is characterized in that, mainly comprises:
Top control module; Be used to make up the CMP system structural framework;
Pretreatment module: be used for generating the user and wish various signals of the CMP that generates and definition;
Kernel generation module: the micro-processor kernel that is used for generating the CMP system framework;
Testing authentication module: be used for the setting of various test modes;
The output module of forming by CMP system structural framework and testing authentication report: be used for the system structural framework that according to user definition customization generates chip multiprocessors, and according to user's test case generation test report;
The annexation of each module is: this top control module links to each other with pretreatment module, kernel generation module, testing authentication module respectively, this pretreatment module links to each other with the testing authentication module with the kernel generation module simultaneously, this kernel generation module links to each other with the CMP system structural framework of output module, and this testing authentication module links to each other with the testing authentication report of output module.
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| CN100336033C CN100336033C (en) | 2007-09-05 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100530103C (en) * | 2007-12-29 | 2009-08-19 | 中国科学院计算技术研究所 | Simulator and method |
| CN101256502B (en) * | 2007-02-27 | 2011-02-09 | 国际商业机器公司 | System and method for simulating multiprocessor system |
| CN104750603A (en) * | 2013-12-30 | 2015-07-01 | 联芯科技有限公司 | Multi-core DSP (Digital Signal Processor) software emulator and physical layer software testing method thereof |
| CN113282219A (en) * | 2021-07-22 | 2021-08-20 | 深圳英集芯科技股份有限公司 | Method for drawing assembly line CPU architecture diagram and terminal equipment |
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| US6014512A (en) * | 1996-10-18 | 2000-01-11 | Samsung Electronics Co., Ltd. | Method and apparatus for simulation of a multi-processor circuit |
| JP4226085B2 (en) * | 1996-10-31 | 2009-02-18 | 株式会社ルネサステクノロジ | Microprocessor and multiprocessor system |
| AU2001255808A1 (en) * | 2000-03-15 | 2001-09-24 | Arc Cores, Inc. | Method and apparatus for debugging programs in a distributed environment |
| US6718294B1 (en) * | 2000-05-16 | 2004-04-06 | Mindspeed Technologies, Inc. | System and method for synchronized control of system simulators with multiple processor cores |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256502B (en) * | 2007-02-27 | 2011-02-09 | 国际商业机器公司 | System and method for simulating multiprocessor system |
| CN100530103C (en) * | 2007-12-29 | 2009-08-19 | 中国科学院计算技术研究所 | Simulator and method |
| CN104750603A (en) * | 2013-12-30 | 2015-07-01 | 联芯科技有限公司 | Multi-core DSP (Digital Signal Processor) software emulator and physical layer software testing method thereof |
| CN104750603B (en) * | 2013-12-30 | 2018-12-11 | 辰芯科技有限公司 | A kind of multi-core DSP software simulator and its physical layer software test method |
| CN113282219A (en) * | 2021-07-22 | 2021-08-20 | 深圳英集芯科技股份有限公司 | Method for drawing assembly line CPU architecture diagram and terminal equipment |
| CN113282219B (en) * | 2021-07-22 | 2021-09-28 | 深圳英集芯科技股份有限公司 | Method for drawing assembly line CPU architecture diagram and terminal equipment |
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