CN1642011A - Clock decimal frequency dividing method - Google Patents
Clock decimal frequency dividing method Download PDFInfo
- Publication number
- CN1642011A CN1642011A CN 200410002149 CN200410002149A CN1642011A CN 1642011 A CN1642011 A CN 1642011A CN 200410002149 CN200410002149 CN 200410002149 CN 200410002149 A CN200410002149 A CN 200410002149A CN 1642011 A CN1642011 A CN 1642011A
- Authority
- CN
- China
- Prior art keywords
- clock
- frequency division
- frequency
- fractional
- enable signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a decimal frequency division method for clock. According to m frequency division and m+1 frequency division inserting method to take decimal frequency division to the clock to gain a basic clock and generate an enable signal. Using the enable signal reforming the basic clock to gain the needed frequency clock signal. The invention can improve the equitability of the clock, and by deducting or increasing impulse it also can improve duty ratio and the capability of clock. Thus, the decimal frequency division clock gained from the invention is almost the same as double frequency first then decimal frequency division on capability and quality.
Description
Technical field
The present invention relates to the clock technology of the communications field, relate in particular to a kind of fractional frequency division method of clock.
Background technology
In present communication system, because the needs of design, to some Synchronization Design, need to adopt the way of fractional frequency division to obtain clock, as in the SDH of 38.88M synchro system, the extraction of the expense of corresponding STM-1 needs to use the overhead extraction clock of 2.048M sometimes.But 2.048M can not obtain by the 38.88M integer, can only obtain by fractional frequency division.
The principle of clock fractional frequency division is as follows:
The frequency of supposing input clock is f0, and output frequency is fx, then:
K=f0/fx=m+n, wherein
Wherein, m is the integer part of f0/fx, and n is the fractional part of f0/fx.
In order to realize the K frequency division, can carry out a m frequency division and b m+1 frequency division to f0, and relation below satisfying:
That is: (a+b) k=am+b (m+1)
Obtain after the arrangement:
If obtain the 2.048M clock, then f0=38.88MHz, fx=2.048MHz substitution following formula are calculated by 38.88M: m=18, a=1, b=63 promptly carries out 1 time 18 frequency division to 38.88MHz and 63 times 19 frequency divisions just can obtain the 2.048MHz clock.
Consult Fig. 1, fractional frequency division commonly used is the principle according to above-mentioned fractional frequency division, is to interleave behind a m frequency division of clock of fo, b the m+1 frequency division to obtain the fractional frequency division clock that needs with frequency, and its frequency is fx.Fractional frequency division mainly contains following two kinds of methods when specific implementation:
Method one:
If by 38.88M clock fractional frequency division to 8.192 clocks, according to the principle of above-mentioned fractional frequency division:
F0=38.88MHz, fx=8.192MHz substitution are calculated m=4, a=65, b=191 promptly carries out 65 times 4 frequency divisions to 38.88MHz and 191 times 5 frequency divisions just can obtain the 8.192MHz clock.At this moment the method for Cai Yonging just has a lot, as: can carry out 65 times 4 frequency divisions earlier, carry out 191 times 5 frequency divisions again; Also can carry out 65 4-5 earlier and replace frequency division, carry out 126 times 5 frequency divisions again.
Though this implementation method is simpler, from top fractional frequency division characteristics as can be known, adopt the clock duty cycle of 38.88M frequency division to 8.192M, can arrive 60%; Shake/the deviation ratio of clock is bigger simultaneously.Therefore adopt the clock that obtains of this fractional frequency division, only be applicable to the situation not high clock duty cycle; Use the reference clock of this fractional frequency division clock as phase-locked loop if desired, situations such as losing lock will appear in phase-locked loopback.
Method two:
In order to improve the clock quality of fractional frequency division, the 38.88M frequency multiplication to 77.76M or to the 155.52M clock, is obtained the 8.192M clock with 77.76M and 155.52M clock fractional frequency division then.
1, f0=77.76MHz, fx=8.192MHz substitution aforementioned formula are calculated m=9, a=65, b=63 promptly carries out 65 times 9 frequency divisions to 77.76MHz and 63 times 10 frequency divisions just can obtain the 8.192MHz clock.
Adopt 65 times the 9-10 frequency division, just can obtain duty and when shake the clock that improves a lot carrying out 2 times 9 frequency divisions.
2, f0=155.52MHz, fx=8.192MHz substitution are calculated m=18, a=1, b=63; Promptly 155.52MHz is carried out 1 time 18 frequency division and 63 times 19 frequency divisions just can obtain the 8.192MHz clock.
This clock is basically near with the clock of 2.048 crystal oscillators generations.
Though on principle, the difference on the frequency of raising clock can effectively improve the performance and the quality of the clock behind the fractional frequency division; But, can make system configuration become complicated like this, and cost improve significantly owing to want earlier clock to be carried out process of frequency multiplication.
Summary of the invention
The invention provides a kind of fractional frequency division method of clock, have complex structure and the high problem of cost when improving clock performance in the prior art to solve.
A kind of fractional frequency division method of clock, this method is:
The mode that interleaves by m frequency division and m+1 frequency division is treated frequency-dividing clock and is carried out fractional frequency division, obtains a fundamental clock, and produces an enable signal simultaneously;
Utilize the described fundamental clock of described enable signal shaping, obtain the clock signal of required frequency.
According to said method:
In the identical time, treat that the number of the clock half period of frequency-dividing clock treats that with two frequencys multiplication the number of the clock cycle of frequency-dividing clock equates to determine the number that interleaves of m frequency division and m+1 frequency division, make the long and short cycle of the clock signal that obtains behind the fractional frequency division even, with the clock uniformity behind the raising fractional frequency division.
By with fractional frequency division in the reverse triggering on the triggering edge for the treatment of sub-frequency clock signal of adopting along producing described enable signal.
According to the interleaving number and two frequencys multiplication treated that the frequency-dividing clock fractional frequency division recently produces enable signal to the duty of required frequency clock of m frequency division and m+1 frequency division, make by the duty ratio of the fundamental clock after the enable signal shaping with two frequencys multiplication are treated the frequency-dividing clock fractional frequency division is identical to the duty ratio of required frequency clock.
The described fundamental clock of shaping is meant that enable signal and fundamental clock are carried out logical operation to be come from basic clock signal deduction or increase pulse.
The present invention by enable signal deduction or increase pulse, can also improve duty ratio by the uniformity that can improve clock that interleaves of different frequency divisions, and clock performance is provided.Thereby adopt fractional frequency division clock that the present invention obtains and first frequency multiplication again the clock that obtains of fractional frequency division in performance and basic identical qualitatively; Because not needing to treat sub-frequency clock signal carries out process of frequency multiplication, thereby system configuration is simpler, thereby can reduce system cost to a certain extent.
Description of drawings
Fig. 1 is a fractional frequency division theory diagram in the prior art;
Fig. 2 is a fractional frequency division theory diagram of the present invention;
Fig. 3 is for typically handling schematic diagram with frequency word transmission system (SDH) cost of device;
Fig. 4 is the clock generating schematic diagram.
Embodiment
Consult shown in Figure 2ly, the present invention realizes that the method for fractional frequency division is: determine to realize a the m frequency division that fractional frequency division need carry out and parameter a, b, the m of b m+1 frequency division according to the frequency of the frequency for the treatment of frequency-dividing clock f0 (to call clock f0 in the following text) and required clock fx (to call clock fx in the following text); The mode that interleaves by m frequency division and m+1 frequency division is treated frequency-dividing clock f0 and is carried out fractional frequency division then, obtains fundamental clock f1; And produce enable signal simultaneously, and remove shaping fundamental clock f1 by this enable signal, obtain the clock signal fx of required frequency.
If fractional frequency division adopts the rising edge of clock f0, then enable signal adopts trailing edge; Otherwise if fractional frequency division adopts the trailing edge of clock f0, then enable signal adopts rising edge.The logical operation that the clock signal of enable signal after with fractional frequency division carried out according to specific implementation can adopt " with ", " or ", " non-" etc.
The principle that enable signal produces: according to the interleave number of clock f0 fractional frequency division to the m frequency division of clock fx and m+1 frequency division, and with the situation of frequency doubling clock 2f0 fractional frequency division to the duty ratio of same frequency clock, rationally produce enable signal, the duty ratio of the clock after the shaping of use enable signal is identical with the duty ratio of the same frequency clock that arrives with clock 2f0 fractional frequency division.
Being described in detail as follows of said method:
According to the principle of fractional frequency division as can be known:, will inevitably be to carry out m frequency division, b m+1 frequency division a time if carry out fractional frequency division to clock fx by clock f0.
(1) if m is an odd number, then the high level of m frequency division is to the maximum: (m+1)/2, low level is: (m-(m+1)/2)=(m-1)/2; Otherwise low level is to the maximum: (m+1)/2, high level is: (m-(m+1)/2)=(m-1)/2.Therefore the duty ratio of the fractional frequency division clock fx that obtains is ((m+1)/2)/m=(m+1)/2m to the maximum.
(2) if m is an even number, then the duty ratio that obtains of m+1 frequency division is bigger.The high level that in like manner can obtain the m+1 frequency division is to the maximum: (m+2)/2, low level is: ((m+1)-(m+2)/2)=m/2; Otherwise low level is to the maximum: (m+2)/2, high level is: ((m+1)-(m+1)/2)=m/2.Therefore the duty ratio of the fractional frequency division clock fx that obtains is ((m+1)+1)/2 to the maximum)/(m+1)=(m+2)/2 (m+1).
(3), comprehensive (1), (2) can get, the maximum duty cycle of fractional frequency division be (m+1)/2m (m is the odd number more than or equal to 3).
Formula by (3) can obtain, and the maximum duty cycle of fractional frequency division is 2/3.Along with the increase of frequency dividing ratio, duty ratio is more and more littler.This just illustrates by fractional frequency division and arrives identical clock, improves and treat that the frequency of frequency-dividing clock can obtain the reason of the better clock of duty ratio.
Principle according to above-mentioned fractional frequency division can get: if carry out fractional frequency division to clock fx, k1=f0/fx=m1+n1 by clock f0; Clock 2f0 carries out fractional frequency division to clock fx, k2=2f0/fx=m2+n2;
F0 is carried out the half period counting, reaches if desired, need following equation with the effect of 2f0 frequency division to fx:
X*2m1+Y*2(m1+1)＝Z*(m2)+W*(m2+1)
Wherein:
(1), the equation forward part is the number of the clock half period of f0 frequency division in a period of time, the rear section is the number of the clock cycle of 2f0 frequency division in the identical time.
(2), X, Y, Z, W are the indefinite factors:
X: represent with the clock periodicity of f0 frequency division to the f0 of the short period (carrying out the m1 frequency division) of fx;
Y: represent with the clock periodicity of f0 frequency division to the f0 of the long period (carrying out the m1+1 frequency division) of fx;
W: represent with the clock periodicity of 2f0 frequency division to the 2f0 of the short period (carrying out the m2 frequency division) of fx;
Z: represent with the clock periodicity of 2f0 frequency division to the 2f0 of the long period (carrying out the m2+1 frequency division) of fx.
This equation is an indeterminate equation, determines that its principle of separating is to make the duty ratio of the fractional frequency division clock that obtains as far as possible little, and clock jitter is as far as possible little, just makes the clock of different duty carry out reasonable must interleaving.Such as: for carrying out 50 times 5 frequency divisions if desired, the clock of 40 times 4 frequency divisions preferably adopts the 5-4 frequency division 40 times, and then 10 times 5 frequency divisions.And do not adopt earlier 50 frequency divisions, the method for 40 frequency divisions again.After rationally being separated, can adopt multiple distinct methods with the f0 fractional frequency division to fx, as detain half pulse etc., obtain the fractional frequency division clock fx that needs.
It is that the clock decimal of f0 is the clock of fx to crossover frequency that the inventive method that Here it is adopts frequency, also can reach with 2 times the f0 clock division theoretical foundation to the clock performance of fx.
Consult shown in Figure 4, at optical synchronization digital transmission system (Synchronous Digital Hierarchy, SDH) in, at present for the Overhead that transmits, adopt the clock of 2.048M/8.192M, and what adopt in the system all is the clock of 38.88M/77.76M basically, in some low capacity systems, at this moment therefore the normal system clock (see figure 1) that adopts 38.88M need obtain the 2.048M/8.192M clock by the 38.88M frequency division.Be that example illustrates method of the present invention to the 8.192M clock now with the 38.88M frequency division.
(1), determines parameter in the fractional frequency division
According to fractional frequency division as can be known, need 4/5 frequency division by the 38.88M frequency division to the 8.192M clock; Need 9/10 frequency division by the 77.76M frequency division to the 8.192M clock;
Substitution formula: X*2m1+Y*2 (m1+1)=Z* (m2)+W* (m2+1)
Have: 8*X+10*Y=9*Z+10*W;
Separating of this equation is a lot, just can obtain the 8.192MHz clock by 77.76MHz being carried out 65 times 9 frequency divisions and 63 times 10 frequency divisions.Can obtain, the 77.76M frequency division is best to the clock that 8.192M adopts the 9-10-9-10 frequency division to obtain, and therefore can get Z=W, so can obtain 8*X+10*Y=19*Z.
As seen having separated of this equation:
X＝1，Y＝3，Z＝2；
X＝2，Y＝6，Z＝4；
X=3, Y=9, Z=8; Deng;
Because frequency division is big more at interval, the shake of clock is big more, therefore should get X=1, Y=3, this group of Z=2 is separated, and like this 38.88M is carried out the 8.192M clock that the 5-5-5-4 frequency division obtains, can be similar with the 8.192M clock quality that the frequency division that carries out 10-10-9-9 with 77M obtains.
Separate as can be known from above-mentioned getting, determine that the number that interleaves of m frequency division and m+1 frequency division is that according to the absolute value minimums that number and m+1 frequency division interleave the number differences of interleaving with the m frequency division be principle.
(2), specific implementation, consult shown in Figure 4:
A, employing be 63 5-5-5-4 frequency divisions earlier, and then carry out the 4-5 frequency division 2 times, and the frequency division number of times adds up to 63*4+4=256.Obtain clock signal sysclk8m_tmp behind the rising edge fractional frequency division with clock signal sys38m.
B and then be an enable signal enable with the trailing edge of clock signal sys38m, the key of enable signal is the high level of the 8M clock of the 1st, 2 time 5 frequency division will be deducted the 38M cycle half, and the duty ratio of 5 frequency divisions is adjusted into 50%; Respectively deduct the 38m cycle half before and after the 8M clock of the 3rd 5 frequency divisions, the duty ratio of adjusting the 3rd 5 frequency divisions and the 4th 4 frequency divisions is 55.55%.
C, with enable signal enable and signal sysclk8m_tmp with just obtain the sysclk8m signal, promptly transmit the clock signal of Overhead.
As seen the duty ratio of the sysclk8m that obtains is 55.5% to the maximum, and the shake of clock simultaneously also improves a lot.Basically approach effect, carry out the frequency division of 10-10-9-9 when being equivalent to the 77M fractional frequency division with the 77M frequency division.For the clock of other frequencies, its fractional frequency division is identical with above-mentioned processing procedure.
Claims (6)
1, a kind of fractional frequency division method of clock will treat that frequency-dividing clock carries out obtaining required clock behind m frequency division and the m+1 frequency division; It is characterized in that this method is:
The mode that interleaves by m frequency division and m+1 frequency division is treated frequency-dividing clock and is carried out fractional frequency division, obtains a fundamental clock, and produces an enable signal simultaneously;
Utilize the described fundamental clock of described enable signal shaping, obtain the clock signal of required frequency.
2, the method for claim 1, it is characterized in that, in the identical time, treat that the number of the clock half period of frequency-dividing clock treats that with two frequencys multiplication the number of the clock cycle of frequency-dividing clock equates to determine the number that interleaves of m frequency division and m+1 frequency division, makes the long and short cycle of the clock signal that obtains behind the fractional frequency division even.
3, the method for claim 1 is characterized in that, by with fractional frequency division in the reverse triggering on the triggering edge for the treatment of sub-frequency clock signal of adopting along producing described enable signal.
4, the method for claim 1, it is characterized in that, according to the interleaving number and two frequencys multiplication treated that the frequency-dividing clock fractional frequency division recently produces enable signal to the duty of required frequency clock of m frequency division and m+1 frequency division, make by the duty ratio of the fundamental clock after the enable signal shaping with two frequencys multiplication are treated the frequency-dividing clock fractional frequency division is identical to the duty ratio of required frequency clock.
As the arbitrary described method of claim 1 to 4, it is characterized in that 5, the described fundamental clock of shaping is meant that enable signal and fundamental clock are carried out logical operation to be come from basic clock signal deduction or increase pulse.
6, method as claimed in claim 2 is characterized in that, determines that the number that interleaves of m frequency division and m+1 frequency division is that according to the absolute value minimums that number and m+1 frequency division interleave the number differences of interleaving with the m frequency division be principle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200410002149XA CN100382430C (en) | 2004-01-05 | 2004-01-05 | Clock decimal frequency dividing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200410002149XA CN100382430C (en) | 2004-01-05 | 2004-01-05 | Clock decimal frequency dividing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1642011A true CN1642011A (en) | 2005-07-20 |
| CN100382430C CN100382430C (en) | 2008-04-16 |
Family
ID=34867299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200410002149XA Expired - Fee Related CN100382430C (en) | 2004-01-05 | 2004-01-05 | Clock decimal frequency dividing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100382430C (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101060330B (en) * | 2007-03-22 | 2011-06-22 | 郑尧 | A broken number frequency division synthesizer |
| WO2011079630A1 (en) * | 2009-12-29 | 2011-07-07 | 中兴通讯股份有限公司 | Method and apparatus for clock frequency division |
| CN1972122B (en) * | 2005-11-21 | 2011-12-14 | 洛阳卓航测控设备有限责任公司 | Pulse cycle skip delay output control method |
| CN103178834A (en) * | 2013-03-07 | 2013-06-26 | 上海山景集成电路股份有限公司 | Fractional frequency division system |
| CN103414469A (en) * | 2013-06-27 | 2013-11-27 | 深圳市创成微电子有限公司 | RFID fractional-N PLL technology |
| CN104954015A (en) * | 2014-03-26 | 2015-09-30 | 拉碧斯半导体株式会社 | Method of generating a clock, and semiconductor device |
| CN106027165A (en) * | 2016-07-06 | 2016-10-12 | 华南理工大学 | Signal receiving device and method, and communication device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3649874B2 (en) * | 1997-09-25 | 2005-05-18 | 三洋電機株式会社 | Frequency divider circuit |
| JP3415574B2 (en) * | 2000-08-10 | 2003-06-09 | Ｎｅｃエレクトロニクス株式会社 | PLL circuit |
| US6456164B1 (en) * | 2001-03-05 | 2002-09-24 | Koninklijke Philips Electronics N.V. | Sigma delta fractional-N frequency divider with improved noise and spur performance |
-
2004
- 2004-01-05 CN CNB200410002149XA patent/CN100382430C/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1972122B (en) * | 2005-11-21 | 2011-12-14 | 洛阳卓航测控设备有限责任公司 | Pulse cycle skip delay output control method |
| CN101060330B (en) * | 2007-03-22 | 2011-06-22 | 郑尧 | A broken number frequency division synthesizer |
| WO2011079630A1 (en) * | 2009-12-29 | 2011-07-07 | 中兴通讯股份有限公司 | Method and apparatus for clock frequency division |
| US8391438B2 (en) | 2009-12-29 | 2013-03-05 | Zte Corporation | Method and apparatus for clock frequency division |
| CN103178834A (en) * | 2013-03-07 | 2013-06-26 | 上海山景集成电路股份有限公司 | Fractional frequency division system |
| CN103178834B (en) * | 2013-03-07 | 2015-06-17 | 上海山景集成电路股份有限公司 | Fractional frequency division system |
| CN103414469A (en) * | 2013-06-27 | 2013-11-27 | 深圳市创成微电子有限公司 | RFID fractional-N PLL technology |
| CN104954015A (en) * | 2014-03-26 | 2015-09-30 | 拉碧斯半导体株式会社 | Method of generating a clock, and semiconductor device |
| CN104954015B (en) * | 2014-03-26 | 2019-08-20 | 拉碧斯半导体株式会社 | Clock generation method and semiconductor device |
| CN106027165A (en) * | 2016-07-06 | 2016-10-12 | 华南理工大学 | Signal receiving device and method, and communication device |
| CN106027165B (en) * | 2016-07-06 | 2017-09-15 | 华南理工大学 | OOK pulsed signals device, method and communicator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100382430C (en) | 2008-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1272907C (en) | Clock data recovering system with external early/late input | |
| CN1127200C (en) | Frequency synthetic circuit regulated by digit | |
| CN1589425A (en) | Glitch-free clock select switching | |
| CN1890881A (en) | Delta-sigma type fraction division pll synthesizer | |
| CN1608346A (en) | Frequency divider with reduced jitter and transmitter based thereon | |
| CN1767048A (en) | Latch clock generation circuit and serial-parallel conversion circuit | |
| US8471607B1 (en) | High-speed frequency divider architecture | |
| CN1642011A (en) | Clock decimal frequency dividing method | |
| CN1774863A (en) | Equiphase multi-phase clock signal generator circuit and serial digital data receiving circuit using the same | |
| CN1091977C (en) | Clock synchronization method for non-integral number frequency multiplication system | |
| CN101051837A (en) | Frequency correcting device and its method USB interface built-in vibrator | |
| CN1835389A (en) | Method able to eliminate frequency error of digital controlled oscillator and phase accumulator | |
| CN110311672B (en) | Low-delay high-frequency clock frequency division circuit, frequency divider and frequency division method | |
| CN101841332B (en) | Digital phase-locked loop | |
| CN1697324A (en) | Method and device for redlization of debouncing for transmission signal | |
| CN101183871A (en) | Method of implementing conversion of input clock to high-frequency clock and phase-locked loop apparatus | |
| CN101079632A (en) | Low-jitter spread spectrum clocking generator | |
| CN101039109A (en) | Spread spectrum block control apparatus and spread spectrum clock generating apparatus | |
| CN1879303A (en) | A frequency multiplier | |
| CN1262065C (en) | Frequency synthesizer | |
| CN100352160C (en) | High frequency binary phase detector | |
| CN101060330A (en) | A broken number frequency division synthesizer | |
| CN1801691A (en) | Quadrature phase signal producing apparatus and data recovery circuit | |
| CN1420654A (en) | Digital signal processing method and data processor | |
| CN1878266A (en) | Audio processing circuit and related method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080416 Termination date: 20120105 |