CN1635732A - Instruction system with reconfigurable password coprocessor - Google Patents
Instruction system with reconfigurable password coprocessor Download PDFInfo
- Publication number
- CN1635732A CN1635732A CN 200310114568 CN200310114568A CN1635732A CN 1635732 A CN1635732 A CN 1635732A CN 200310114568 CN200310114568 CN 200310114568 CN 200310114568 A CN200310114568 A CN 200310114568A CN 1635732 A CN1635732 A CN 1635732A
- Authority
- CN
- China
- Prior art keywords
- instruction
- password
- reconstruct
- coding
- insformat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Storage Device Security (AREA)
Abstract
This invention refers to an instruction system of reconfigurable cipher coprocessor adopting very long instruction word (VLIW), which contains execution instruction, configuration instruction, stop instruction and skip instruction. Said instruction system changes the problem of current special cipher chip (without instruction system) only realizing special cipher algorithm and has good flexibility and use performance.
Description
Technical field
But the present invention relates to a kind of instruction system of reconstruct password coprocessor.
Background technology
Present development and application along with the network information technology, routine office work and life depend on more and more that network environment communicates and information sharing, thereby the information in the network communication process is accurately transmitted and effectively maintained secrecy and becomes the important topic of safe handling network.
The password chip is the key core parts that make up safety information product, and the password chip that is widely used now both at home and abroad all is the special-purpose device for specific password algorithm design. The system structure of chip be fix and malleable not, the realization of password algorithm is finished by hardware, does not therefore also just have corresponding instruction system. Thereby there is a following shortcoming and defect:
1, special-purpose password chip in use only can be realized its special algorithm, the password algorithm that the user can only use this kind to pre-determine is encrypted/and data decryption and can not arbitrarily changing;
2, special-purpose password chip self bad adaptability can't satisfy different user or same user to the requirement of different password algorithms. If need to change algorithm, then must change chip, this just causes the raising of design cost and prolongs the design cycle;
3, any password algorithm has the possibility that is broken, in case the password algorithm is broken or can not continue use owing to other reason causes the password algorithm, original password algorithm that then needs to upgrade, special-purpose password chip then can not be realized upgrading, thereby the property expanded, security are not relatively poor.
As mentioned above, but the password chip realizes that reconstruct password algorithm is the key factor that addresses the above problem. But formerly openly do not disclose in the prior art, realize that the circuit design of Reconfigurable cipher chip also belongs to blank, more do not have the relevant technology of the instruction system design of Reconfigurable cipher chip.
Summary of the invention
But the instruction system of reconstruct password coprocessor of the present invention, but its purpose is to provide the interface of realizing between cryptographic consumer and the reconstruct password coprocessor hardware circuit, but thereby is the medium that cryptographic consumer is rely the reconstruct password coprocessor is implemented to control realization and upgraded required password algorithm.
Described instruction system, but its performance directly has influence on the performance of reconstruct password coprocessor. Mainly have following decisive factor:
The Password Operations number of types that A, instruction system provide. The type of the Password Operations that instruction system can provide is more, and then its password algorithm of supporting is just more;
B, instruction system are realized the instruction quantity of the required execution of password algorithm. Instruction strip number is fewer, and then the speed of enciphering/deciphering is faster.
The size of code of C, password program. The size of code of password program represents its shared storage space.
The complete function of D, instruction system. Be that instruction system not only can provide a large amount of common Password Operations, and necessary program control function should be provided.
The complexity of E, instruction system, namely instruction system can not be too complicated, to reduce the complexity of design difficulty and instruction encoded control logic.
Above-mentioned factor is mutually restriction, can not reach simultaneously optimum, therefore needs to consider various factors in the design of instruction system. But for reaching the purpose that realizes flexibly, fast different password algorithms of reconstruct password coprocessor, the flexibility of instruction system and performance are the most important.
If the Password Operations type that instruction system is realized is too many, will cause the hardware circuit scale to be difficult to too greatly realize, instruction system of the present invention comprises the basic code operation type that frequency of utilization is higher. Simultaneously additional with the general operation type of part, thereby but the operation type set that consists of the instruction system of reconstruct password coprocessor close. Specifically,
Described instruction system mainly comprises following operation type: 32 displacement positions, 128 displacement positions, 28 circulations move to left, 32*32 displacement, 64*64 displacement, 64*32 displacement, the replacement of 8*8S box, 32 bit linear feedback shifts, 16 are different or computing, 16 moulds 216 add/and subtraction, 16 mould 216+1 multiplication, the inverse operation of 16 mould 216+1 multiplication, 32 mould 232 multiplication, 8 mould multinomial multiplication, 16 logic computings, 16 bit comparison computings, peek, poke, read/write register heap etc.
In order to improve the performance of instruction system, will reduce the instruction strip number of realizing the required execution of password algorithm. Because any one password algorithm all is to be made of according to certain sequential relation (parallel, serial) a series of operations, and the execution of each operation is to give corresponding module by instruction to drive with the control coding of determining. Therefore, the operation that each coding line drives simultaneously is more, realizes that then the instruction strip number of the required execution of password algorithm is just fewer, and the speed of enciphering/deciphering is just faster.
Instruction system of the present invention adopts overlength coding line (VLIW) but technology designs the reconstruct password coprocessor, drives simultaneously the purpose of a plurality of operations to reach each coding line, includes a plurality of operation control codings in each coding line.
But form the control coding of reconstruct password coprocessor module, be divided into following several types:
Operation enable code-control operate whether carry out, the function of functional configuration code-configuration module, Data Source code-determine operand, the purpose address etc. of whereabouts code-operating result as a result.
But realize an effective Password Operations at the reconstruct password coprocessor, often need dissimilar control codings to work in coordination and just can finish. For example, we will realize that the S box of one 8 input data to 8 an output data replaces conversion, at first we need to dispose the function of S box, it is the replacement conversion function that the S box is realized, this need to compose with 2048 functional configuration codes the S box, also need in addition to operate 1 of enable code, 6 of Data Source codes need 2055 control codings altogether so realize this operation.
As mentioned above, a large amount of codings all are assembled in the coding line, and then the length of coding line is too long, thereby make the shared storage space of password program be difficult to too greatly realize.
For addressing this problem, according to the characteristic of control coding, namely most functional configuration codes remains unchanged or changes number of times seldom in the enciphering/deciphering process, and other control codings such as Data Source code need frequently to change. Instruction system of the present invention comprises static coding and dynamically encodes.
In the enciphering/deciphering process, remaining unchanged or changing number of times control coding seldom is called static coding; In the enciphering/deciphering process, the control coding that needs frequently to change is called dynamic coding.
Because static being coded in a lot of the continuous clock cycle can not change, and therefore do not need in the period it is controlled at this section, thereby the instruction in this section period do not need to comprise static coding. Dynamically coding then almost needs to change in each clock cycle, therefore must give real-time control by current instruction.
According to the above-mentioned characteristic that static state is encoded and dynamically encoded, we are assembled in the static state coding respectively in the different instructions with dynamic coding, form two kinds of different instruction forms.
Because the general function that is used for configuration password computing module of static coding, so the instruction form of the static coding of assembly unit is the configuration-direct form; And the general concrete execution that is used for the control Password Operations of dynamically encoding, so the instruction form that assembly unit is dynamically encoded is for carrying out the instruction form.
For those operations that needs a large amount of functional configuration codes, we can at first use configuration-direct that corresponding module is carried out functional configuration, and then with carrying out instruction driving module different Data Sources are operated. If one period, the function of module does not change, and just different Data Sources is carried out identical operation (this is the general feature that many password algorithms have), so in this section the period, only need to the functions of modules configuration once, then the operation enable code of module and Data Source code are controlled in real time got final product by carrying out instruction.
In the enciphering/deciphering process, adopt configuration-direct and carry out the method that instruction is combined with, can greatly reduce the redundancy coding in the coding line, reduce the length of coding line, increase the number of the effective operation that comprises in the coding line, thereby can effectively improve enciphering/deciphering speed and reduce the size of code of password program.
Except above-mentioned configuration-direct form and execution instruction form; consider the needs of programme-control aspect; instruction system of the present invention also is provided with redirect and shuts down two kinds of instruction forms, but to improve the complete function of reconstruct password coprocessor instruction system.
As mentioned above; but the instruction system of described reconstruct password coprocessor; the instruction structure adopts overlength coding line (VLIW) structure, comprises carrying out instruction form, configuration-direct form, shutdown instruction form, redirect instruction form and other instruction form, and the instruction form is:
| insformat[m：n] | inscode[n-1：0] |
Wherein:
Insformat is instruction form control territory, is used for expression and carries out instruction, configuration-direct, shutdown instruction, redirect instruction and other instruction form.
Inscode is the instruction encoding domain. Specifically:
Described configuration-direct, in the static state coding of assembly unit is arranged, but be used for the password computing module of reconstruct password coprocessor is carried out functional configuration. But described reconstruct password coprocessor has a large amount of static state codings, is kept at respectively in a plurality of configuration file registers, is loaded by configuration-direct.
The form of configuration-direct is:
| insformat[m：n] | contreg_num[n-1： n2] | contreg_addr[n2-1 ：n1] | contdata[n 1-1：0] |
Wherein:
Insformat is instruction form control territory.
Contreg_num is configuration file register encoding domain, is used for indicating the configuration file register that is loaded.
Contreg-addr is the data address in the configuration file register, because the data amount that some configuration file register comprises is too large, need to pack into several times, therefore needs to an address of data allocations of packing at every turn.
Contdata is configuration data (i.e. static coding).
Described execution instruction, in the dynamic coding of assembly unit is arranged, but the module that is used for driving the reconstruct password coprocessor is carried out various basic operations to data. But the dynamic coding of all of described reconstruct password coprocessor can all be assembled in a kind of execution instruction form, also can separately be assembled in the multiple execution instruction form. It is larger that the former operates parallel property, but instruction length is larger; It is less that the latter operates parallel property, but instruction length is also less. Be assembled in operating under the prerequisite that resource is not conflicted and data are uncorrelated that same the coding in the instruction drive, all can carry out simultaneously.
The form of carrying out instruction is:
| insformat[ m：n] | opcod_k[n-1 ：nk] | … | Opcode_1[n 2-1：n1] | opcode_0[n1-1： 0] |
Wherein:
Insformat is instruction form control territory.
opcode_0
-Opcode_k is the operate coding territory, comprises the operation enable code, Data Source code, as a result whereabouts code etc.
Described redirect instruction, redirect instruction are used for the redirect of control program to be carried out, and its form is:
| insformat[m：n] | cond_code[n-1 ：n2] | jump_addr[n2- 1：n1] | reserved[n1-1：0] |
Wherein:
Insformat is instruction form control territory.
Cond_code is the condition coding, be used for the condition that the expression redirect occurs, include: unconditional redirect, relatively the result less than be designated redirect in 1 o'clock, relatively the result equal to be designated redirect in 1 o'clock, relatively the result greater than be designated redirect in 1 o'clock, relatively the result less than or equal to be designated redirect in 1 o'clock, relatively the result is more than or equal to being designated redirect in 1 o'clock, not redirect.
Jump_addr is jump address.
Reserved keeps encoding domain.
Described shutdown instruction is used for finishing program implementation, but makes the reconstruct password coprocessor be in idle state, keeps simultaneously the present state of all registers constant. Its instruction form is:
| insformat[m：n] | reserved[n-1：0] |
Wherein:
Insformat is instruction form control territory.
Reserved keeps encoding domain.
In sum, but the instruction system of reconstruct password coprocessor of the present invention has the following advantages and useful effect:
1, changes the present situation that existing special-purpose password chip (not having instruction system) can only be realized specific password algorithm, have larger flexibility and serviceability;
2, described instruction system have less program code amount, more complete function and and lower design difficulty, but can effectively support the characteristic of hardware circuit reconstruct, the parallel property of abundant development and operation, improve the utilization rate of hardware resource, thereby but make cryptographic consumer can on the reconstruct password coprocessor, realize flexibly, fast different password algorithms.
Concrete enforcement mode
But the instruction system of reconstruct password coprocessor as described in the present invention, can realize polytype password algorithm, it adopts overlength coding line (VLIW) structure, instruction length be 202 (in fact, because the minimum memory cell of memory is byte, therefore in actual applications, we need to fill instruction, the length that makes it is the integral multiple of byte, namely 208).
Described instruction system has 4 kinds of instruction forms, and its instruction form is:
| insformat[201：200] | inscode[199：0] |
Wherein:
Insformat is instruction form control territory, and insformat=00 represents to carry out instruction, and insformat=01 represents configuration-direct, and insformat=10 represents to shut down instruction, and insformat=11 represents the redirect instruction.
Inscode is the instruction encoding domain.
But the instruction system of described reconstruct password coprocessor has following 4 kinds of instruction forms, carries out instruction, configuration-direct, shutdown instruction and redirect instruction that is:.
Described configuration-direct, the static coding of inner assembly unit, but be used for the password computing module of reconstruct password coprocessor is carried out functional configuration. But the reconstruct password coprocessor has 17830 static codings, is kept at respectively in 14 configuration file registers, is loaded by configuration-direct.
The form of configuration-direct is:
| insformat[201： 200] | contreg_num [199：196] | contreg_addr[195： 192] | contdata[191：0] |
Wherein:
Insformat is instruction form control territory, at insformat=01 here.
Contreg_num is configuration file register encoding domain.
Contreg_addr is the data address in the configuration file register.
Contdata is configuration data (i.e. static coding).
Below be the explanation of coding, title and the capacity of described configuration file register:
| The contreg_num coding | Corresponding configuration file register | The capacity of configuration file register |
| 0000 | The configuration file register of 32*32 displacement module 0 | 160 |
| 0001 | The configuration file register of 32*32 displacement module 1 | 160 |
| 0010 | The configuration file register of 64*32 displacement module | 192 |
| 0011 | The configuration file register of 64*64 displacement module 0 loads 192, minute twice loading at every turn. | 384 |
| 0100 | The configuration file register of 64*64 displacement module 1 loads 192, minute twice loading at every turn. | 384 |
| 0101 | Keep | |
| 0110 | Keep | |
| 0111 | The configuration file register of 8*8S box 0 loads 128 at every turn, minute No. 16 loadings. | 2048 |
| 1000 | The configuration file register of 8*8S box 1 loads 128 at every turn, minute No. 16 loadings. | 2048 |
| 1001 | The configuration file register of 8*8S box 2 loads 128 at every turn, minute No. 16 loadings. | 2048 |
| 1010 | The configuration file register of 8*8S box 3 loads 128 at every turn, minute No. 16 loadings. | 2048 |
| 1011 | The configuration file register of 8*8S box 4 loads 128 at every turn, minute No. 16 loadings. | 2048 |
| 1100 | The configuration file register of 8*8S box 5 loads 128 at every turn, minute No. 16 loadings. | 2048 |
| 1101 | The configuration file register of 8*8S box 6 loads 128 at every turn, minute No. 16 loadings. | 2048 |
| 1110 | The configuration file register of 8*8S box 7 loads 128 at every turn, minute No. 16 loadings. | 2048 |
| 1111 | The mould multinomial is taken advantage of _ feedback shift configuration file register | 166 |
Described execution instruction, inner assembly unit is dynamically encoded, but for the module that drives the reconstruct password coprocessor data is carried out various password computings.
But described reconstruct password coprocessor has 195 dynamically codings, all is assembled in and carries out in the instruction form. Can carry out various different Password Operations to 128 bit data simultaneously at most.
The form of carrying out instruction is:
| insformat [201：200] | reserved [199：195] | lfsr322 _en [194] | lfsr322 op [193] | lfsr321_en [192] | lfsr321op [191] | ||||||||||||||||||
| lfsr320 _en [190] | lfsr3 20op [189] | mpmul87 _en [188] | mpmul86 _en [187] | mpmul85 _en [186] | mpmul84 _en [185] | mpmul83_en [184] | |||||||||||||||||
| mpmul82 _en [183] | mpmul81 _en [182] | mpmul80 _en [181] | lu16 _en [180 ] | lu16o p [179： 178] | mmul32_ en [177] | mmul161iv_en [176] | |||||||||||||||||
| mmul161 1_en [175] | mmul161 0_en [174] | madd16 1_en [173] | madd16 1op [172] | madd16 0_en [171] | madd16 0op [170] | xor162_en [169] | |||||||||||||||||
| xor161 _en [168] | xor16 0_en [167] | sbox7 r_en [166] | sbox6 r_en [165] | sbox5 r_en [164] | sbox4 r_en [163] | sbox3r_en [162] | sbox2 r_en [161] | ||||||||||||||||
| sbox1r _en [160] | sbox0r_ en [159] | comp_ en [158] | xor163_ en [157] | pmt641_e n [156] | pmt640_ en [155] | Pmt6432_en [154] | |||||||||||||||||
| pmt321 _en [153] | pmt320_ en [152] | Sf128 _en [151] | Sf128 sf [150] | Sf128 dir [149] | Sf128sb [148： 142] | sf32_en [141] | sf32s f [140] | ||||||||||||||||
| sf32di r [139] | sf32sb [138： 134] | lsf28 1_en [133] | lsf28 1sb [132] | lsf28 0_en [131] | lsf280s b [130] | load-en [129] | store _en [128] |
| rf7w_e n [127] | rf7w_ addr [126： 123] | rf7r_ en [122] | rf7r_a ddr [121： 118] | rf6w_ en [117] | rf6w_ad dr [116： 113] | rf6r_en [112] | rf6r_ addr [111： 108] |
| rf5w_e n [107] | rf5w_ addr [106： 103] | rf5r_ en [102] | rf5r_a ddr [101： 98] | rf4w_ en [97] | rf4w_ad dr [96：93] | rf4r_en [92] | rf4r_ addr [91： 88] |
| rf3w_e n [87] | rf3w_ addr [86： 83] | rf3r_ en [82] | rf3r_a ddr [81： 78] | rf2w _en [77] | rf2w_add r [76：73] | rf2r_en [72] | rf2r_ addr [71： 68] |
| rf1w_e n [67] | rf1w_ addr [66： 63] | rf1r_ en [62] | rf1r_a ddr [61： 58] | rf0w_ en [57] | rf0w_ad dr [56：53] | rf0r_en [52] | rf0r_ addr [51： 48] |
| db7ctr l [47： 42] | db6ct rl [41： 36] | db5ct rl [35： 30] | db4ctr l [29： 24] | db3ct rl [23： 18] | db2ctrl [17：12] | db1ctrl [11：6] | db0ct rl [5：0] |
Wherein:
Insformat: instruction form control territory, at insformat=00 here.
Reserved: keep the territory.
The operation of lfsr32i_en: i 32 bit linear feedback shift registers enables signal, and 1 is effective. (i=0,1,2)
The operation type control signal of lfsr32iop: i 32 bit linear feedback shift registers, 0 is the feedback shift operation, 1 is initial data loading operation. (i=0,1,2)
The operation of mpmul8i_en: i 8 mould multinomial multiplication computing modules enables signal, and 1 is effective. (i=0,1,2,3,4,5,6,7)
The operation of logic computing unit, lu16_en:16 position enables control signal, and 1 is effective.
The operation type control signal of logic computing unit, lu16op:16 position.
Mmul32_en: the operation of mould 232 multipliers enables signal.
The operation of mmul161iv_en:16 position mould 216+1 multiplication inverse operation module enables signal.
Mmul161i_en: the operation of i mould 216+1 multiplier enables signal. (i=0,1)
Madd16i_en: the operation of i mould 216 adders enables signal. (i=0,1)
Madd16iop: the operation type of i mould 216 adders (addition, subtraction) control signal. (i=0,1)
The operation of xor16i_en: i 16 exclusive-OR operators enables signal. (i=0,1,2,3)
The operation of sbox7r_en: i 8 * 8S box enables signal. (i=0,1,2,3,4,5,6,7)
The operation of pmt64i_en: i 64 * 64 displacement modules enables signal. (i=0,1)
The operation of pmt32i_en: i 32 * 32 displacement modules enables signal. (i=0,1)
The operation of sf128_en:128 displacement bit arithmetic module enables signal.
The displacement mode control signal of sf128sf:128 displacement bit arithmetic module.
The direction of displacement control signal of sf128dir:128 displacement bit arithmetic module.
The displacement figure place control signal of sf128sb:128 displacement bit arithmetic module.
The operation of sf32_en:32 displacement bit arithmetic module enables signal.
The displacement mode control signal of sf32sf:32 displacement bit arithmetic module.
The direction of displacement control signal of sf32dir:32 displacement bit arithmetic module.
The displacement figure place control signal of sf32sb:32 displacement bit arithmetic module.
The move to left operation of module of 28 circulations of lsf28i_en: i enables signal. (i=0,1)
The move to left displacement figure place control signal of module of 28 circulations of lsf28isb: i. (i=0,1)
Load_en: data loading enables signal, and 1 is effective.
Store_en: the result preserves and enables signal, and 1 is effective.
Rfiw_en: i register heap write operation and enabled signal. (i=0,1,2,3,4,5,6,7)
Rfiw_addr: i register heap write the operation address. (i=0,1,2,3,4,5,6,7).
Rfir-en: i register heap read operation and enabled signal. (i=0,1,2,3,4,5,6,7)
Rfir_addr: i register heap reads to operate the address. (i=0,1,2,3,4,5,6,7)
Dbictrl: the gating control signal of i bar data bus. (i=0,1,2,3,4,5,6,7)
The pmt6432_en:pmt6432 module enables signal;
Comp_en: relatively operation enables signal.
Described redirect instruction, redirect instruction are used for the redirect of control program to be carried out, and its form is:
| insformat[2 01：200] | cond_code[199 ：197] | jump_addr[196 ：189] | reserved[188：0] |
Wherein:
Insformat is instruction form control territory, at insformat=11 here.
Cond_code is the condition coding, and its coding is defined as follows:
Cond_code=000: unconditional redirect,
Cond_code=001: relatively the result is redirect in 1 o'clock less than sign (less_id),
Cond_code=010: relatively the result equal the sign (equal_id) be redirect in 1 o'clock,
Cond_code=011: relatively the result is redirect in 1 o'clock greater than sign (large_id),
Cond_code=100: relatively the result is redirect in 1 o'clock less than or equal to sign (lesseq_id),
Cond_code=101: relatively the result is redirect in 1 o'clock more than or equal to sign (largeq_id),
Cond_code=110: not redirect,
Cond_code=111: not redirect.
Jump_addr is jump address.
Reserved keeps encoding domain.
Described shutdown instruction is used for finishing program implementation, but makes the reconstruct password coprocessor be in idle state, keeps simultaneously the present state of all registers constant.
Its instruction form is:
| insformat[201：200] | reserved[199：0] |
Wherein:
Insformat is instruction form control territory, at insformat=10 here.
Reserved keeps encoding domain.
As mentioned above, but use the enciphering/deciphering speed of the password algorithm that described instruction system is achieved as follows at the reconstruct password coprocessor and the size of code following (but the dominant frequency of reconstruct password coprocessor is 111Mhz) of enciphering/deciphering program:
| The password algorithm | Enciphering rate (bps) | The size of code of encipheror (byte) | Deciphering speed (bps) | The size of code of decrypted program (byte) |
| DES | 8.36*10 7 | 2.16K | 8.36*10 7 | 2.16K |
| IDEA | 8.36*10 7 | 2.16K | 8.36*10 7 | 2.16K |
| AES | 7.21*10 7 | 5K | 6.73*10 7 | 5.36K |
| Gifford | 1.71*10 8 | 2.08K | 1.71*10 8 | 2.08K |
| Geffe | 1.1*10 8 | 3.28K | 1.1*10 8 | 3.28K |
Claims (6)
- But 1, a kind of instruction system of reconstruct password coprocessor, it is characterized in that: described instruction system adopts overlength coding line (VLIW) structure, and its instruction form is instruction form control territory (insformat)+instruction encoding domain (inscode).
- But 2, the instruction system of reconstruct password coprocessor according to claim 1 is characterized in that: described instruction system has 4 kinds of instruction forms, namely carries out instruction, configuration-direct, shutdown instruction and redirect instruction.
- But 3, the instruction system of reconstruct password coprocessor according to claim 2, it is characterized in that: the static coding of the inner assembly unit of described configuration-direct, its form are the interior data address (contreg_addr) of instruction form control territory (insformat)+configuration file register encoding domain (contreg_num)+configuration file register+configuration datas (contdata i.e. static coding).
- But 4, the instruction system of reconstruct password coprocessor according to claim 2, it is characterized in that: the inner assembly unit of described execution instruction is dynamically encoded, its form is instruction form control territory (insformat)+operate coding territory (opcode_0-opcode_k), wherein the operate coding territory mainly includes the operation enable code, Data Source code, as a result whereabouts code.
- But 5, the instruction system of reconstruct password coprocessor according to claim 2 is characterized in that: the form of described redirect instruction is: instruction form control territory (insformt)+condition coding (cond_code)+jump address (jump_addr)+reservation encoding domain (reserved).
- But 6, the instruction system of reconstruct password coprocessor according to claim 2 is characterized in that: the form of described shutdown instruction is instruction form control territory (insformat)+reservation encoding domain (reserved).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200310114568 CN1635732A (en) | 2003-12-27 | 2003-12-27 | Instruction system with reconfigurable password coprocessor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200310114568 CN1635732A (en) | 2003-12-27 | 2003-12-27 | Instruction system with reconfigurable password coprocessor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1635732A true CN1635732A (en) | 2005-07-06 |
Family
ID=34843455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200310114568 Pending CN1635732A (en) | 2003-12-27 | 2003-12-27 | Instruction system with reconfigurable password coprocessor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1635732A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101170406B (en) * | 2006-10-27 | 2010-10-06 | 北京中电华大电子设计有限责任公司 | A realization method for calculation coprocessor based on dual core public key password algorithm |
| CN102521535A (en) * | 2011-12-05 | 2012-06-27 | 苏州希图视鼎微电子有限公司 | Information safety coprocessor for performing relevant operation by using specific instruction set |
| CN101996155B (en) * | 2009-08-10 | 2014-01-29 | 北京多思科技发展有限公司 | Processor supporting a plurality of command systems |
-
2003
- 2003-12-27 CN CN 200310114568 patent/CN1635732A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101170406B (en) * | 2006-10-27 | 2010-10-06 | 北京中电华大电子设计有限责任公司 | A realization method for calculation coprocessor based on dual core public key password algorithm |
| CN101996155B (en) * | 2009-08-10 | 2014-01-29 | 北京多思科技发展有限公司 | Processor supporting a plurality of command systems |
| CN102521535A (en) * | 2011-12-05 | 2012-06-27 | 苏州希图视鼎微电子有限公司 | Information safety coprocessor for performing relevant operation by using specific instruction set |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100336020C (en) | Information processing apparatus and a ROM image generation apparatus for the apparatus | |
| CN1145879C (en) | Control program product and data processing system | |
| CN1089460C (en) | Data processing with multiple instruction sets | |
| CN1121014C (en) | Eight-bit microcontroller having a RISC architecture | |
| CN1655118A (en) | Processor and compiler | |
| CN1917421A (en) | Method of producing decryption apparatus having element for encryption processing and information used for the encryption processing, decryption apparatus therefrom | |
| CN1856759A (en) | Code obfuscation and controlling a processor by emulation | |
| CN1734475A (en) | Semiconductor integrated circuit and information processing apparatus | |
| CN1495620A (en) | Semiconductor device with encrypted part or external interface and content reproducing method | |
| CN1663172A (en) | Round key generation for AES RIJNDAEL block cipher | |
| CN1799024A (en) | Processing message digest instructions | |
| CN1764881A (en) | Instructions to assist the processing of a cipher message | |
| CN1296790C (en) | Memory management unit code verifying device and code decoder | |
| CN1183462C (en) | Data processing device with variable pipeline series | |
| CN1367895A (en) | Migration of different source languages to executing medium | |
| CN1291328C (en) | Method and system for storing divided files and restoring treatment | |
| CN1125403C (en) | Information processing apparatus and storage medium | |
| CN1635732A (en) | Instruction system with reconfigurable password coprocessor | |
| CN1945541A (en) | Processing operation information transfer control system and method | |
| CN101031904A (en) | Programmable processor system with two kinds of subprocessor to execute multimedia application | |
| CN1635731A (en) | Reconfigurable password coprocessor circuit | |
| CN1607497A (en) | Autonomous device driver | |
| CN1271523C (en) | Central processor with extended instruction | |
| CN1816800A (en) | Program processing system, program processing method, and computer program | |
| CN1726654A (en) | Method and device for calculating an iterated state for a feedback shift register arrangement |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |