CN1632743A - Method and apparatus for writing out data in processor - Google Patents
Method and apparatus for writing out data in processor Download PDFInfo
- Publication number
- CN1632743A CN1632743A CN 200310122431 CN200310122431A CN1632743A CN 1632743 A CN1632743 A CN 1632743A CN 200310122431 CN200310122431 CN 200310122431 CN 200310122431 A CN200310122431 A CN 200310122431A CN 1632743 A CN1632743 A CN 1632743A
- Authority
- CN
- China
- Prior art keywords
- data
- address
- shade
- rotational information
- working storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
This invention provides a material writing device in processor, which comprises the following: one rotation device coupled with its inner memory to rotate the material in the memory to the first position according to the non-aligning writing address; one writing composite memory coupled with the rotation device to store the material in the rotation device; one blind cover coupled with the rotation device and the writing memory device to choose the material and write them to the memory device according to the writing address.
Description
Technical field
The invention relates to the technical field of Data Processing, refer to a kind of method and apparatus that in processor, writes out data unjustified position to the reservoir especially.
Background technology
When processor carried out Data Processing, whether the alignment of data was related to the usefulness of many key operations, for example the usefulness of computing such as word string, array.As shown in Figure 1, the data (ABCDEFGHIJKL) of a need processing is written to a storage device 100 in desiring by working storage R16, R17 and R18 101h to 10Ch locates, and often crosses over the data storage border of this storage device 100.Because this storage device 100 and non-processor data ability are stored to this storage device 100 non-alignment positions so work as the processor desire with this document, processor needs to carry out earlier many extra computings.
At the unjustified problem of processing data, a kind of existing method is after the data with these storage device 100 non-alignment positions is written into processor, utilizes various processor instructions to operate again and obtain needed data.As shown in Figure 2, one document ABCD to be write the non-alignment position, the data (abcd) that will be arranged in the 100h place earlier is written into working storage R1, working storage R1 24 bits that move to right are preserved with the data (a) that will need to preserve, working storage R1 24 bits that move to left are placed the appropriate location with the data (a) that will need to preserve.8 bits that again data (ABCD) of working storage R16 moved to right are restored among the working storage R2 (0ABC), with working storage R1 and working storage R2 carries out or (OR) computing and deposit the result among the working storage R1 (aABC).Secondly, the data (efgh) that will be arranged in 104h place more earlier is written into working storage R1, working storage R1 8 bits that move to left is preserved with the data (fgh) that will need to preserve, with working storage R1 data (fgh) the placement appropriate location of 8 bits will need to preserve that move to right.24 bits that again data (ABCD) of working storage R16 moved to left are restored among the working storage R2 (D000), working storage R1 and working storage R2 are carried out exclusive disjunction and deposit the result among the working storage R1 (Dfgh), and the contents value with working storage R1 is written to reservoir 104h place at last.
As shown in the above description, if the required unjustified data length that is writen to reservoir is n word group (a word group is 32 bits), existing method then needs 12n instruction to describe and writes out action, needs 12n instruction cycle just can finish at least simultaneously and writes out action.This makes procedure code tediously long, occupies the storage area, and the burden that also increases processor simultaneously makes processor efficient not high.
Use processor instruction to handle the problem of the tediously long and efficient of procedure code that unjustified data causes at existing method, in U.S. USP4,814, in No. 976 patent cases, be to be written into the action that unjustified data is promptly alignd simultaneously, and, be divided into twice and write out a document of crossing the boundary.As shown in Figure 3, earlier the content among the working storage R16 (ABC) is writen to reservoir 101h to 103h and locates, this moment, the data at reservoir 100h place was not changed.Again the content among the working storage R16 (D) is writen to reservoir 104h place, this moment, the data at reservoir 105h to 107h place was not changed.In like manner, in regular turn the content of working storage R17 and working storage R18 being written to reservoir 105h to 10Ch respectively locates.
As shown in the above description,, then need 2n instruction to describe and write out action, need 2n instruction cycle just can finish at least simultaneously and write out action if the required unjustified data length of writing out is n word group.And, processor pipeline sluggishness (Stall) possibility is improved because same reservoir and working storage position are made repetitive read-write.And same reservoir position is repeated to write out, can waste bus bandwidth, especially in some system that does not have cache, the delay that is caused is obvious especially.Therefore, the design of existing processor still has many disappearances and gives improved necessity.
The inventor proposes a kind of " writing out the method and apparatus of data in processor " that can address the above problem in line with the spirit of actively inventing, and several times research experiment is eventually to finishing the present invention.
Summary of the invention
The object of the invention provides a kind ofly writes out the method and apparatus of unjustified data with processor, could describe the problem of writing out action because of using than multiple instruction to avoid prior art, and reduce the instruction cycle simultaneously and write out action to finish, and raising execution efficient.
According to a characteristic of the present invention, be to propose a kind of method of in processor, writing out data, wherein, data is to be writen to unjustified address in the storage device, this storage device has the word group of a plurality of m bits of being separated by block boundary, this method mainly comprises an initial rotation step, is that the unjustified address that this data of retrieval and foundation are write out rotates to primary importance with it, to produce one first rotational information; One first shade writes out step, is to this first rotational information shade and be writen to this storage device according to the unjustified address that writes out; One relaying rotation step is the follow-up data of this data of retrieval, according to the unjustified address that writes out it is rotated to primary importance, to produce one second rotational information; One first writes out step, is that this first rotational information of combination does not write out the part of part and this second rotational information, and is writen to this storage device; One finishes the rotation step, is that the follow-up data with this data rotates to primary importance, to produce one the 3rd rotational information; One second writes out step, is the part that this second rotational information of combination does not write out part and the 3rd rotational information, and it is writen to this storage device; And one second shade writes out step, to the 3rd rotational information shade and be writen to this storage device.
According to another characteristic of the present invention, be to propose a kind of method of in processor, writing out, wherein, data is to be writen to unjustified address in the storage device, this storage device has the word group of a plurality of m bits of being separated by block boundary, this method mainly comprises: an initial rotation step is that the unjustified address that this data of retrieval and foundation are write out rotates to primary importance with it, to produce one first rotational information; One first shade writes out step, is to this first rotational information shade and be writen to this storage device according to the unjustified address that writes out; And one second shade writes out step, is to not writing out part in this first rotational information, carrying out shade and be writen to this storage device.
According to a characteristic more of the present invention, be to propose a kind of device that in processor, writes out data, wherein, this data is the inside working storage that is stored in this processor, it will be writen to unjustified address in the storage device, this storage device has the word group of a plurality of m bits of being separated by block boundary, and this device mainly comprises a whirligig, and writes out a combination working storage and a selection shade device.This whirligig is to be coupled to this inside working storage, according to the address that writes out of this unjustified data, rotates to a primary importance with data that should the inside working storage; This writes out the combination working storage is to be coupled to this whirligig, with the data of temporary this whirligig; And this selection shade device is to be coupled to this whirligig and to write out the combination working storage, writes out address according to this, selecting this whirligig of shade and to write out the data of combination working storage, and it is writen to this storage device.
Modern design of the present invention can provide on the industry and utilize, and can promote effect really.
Description of drawings
Fig. 1: be the synoptic diagram that one group of working storage data is written to unjustified position in the reservoir;
Fig. 2: be the procedure code that prior art is written to one group of working storage data unjustified position in the reservoir;
Fig. 3: be the procedure code that another prior art is written to one group of working storage data unjustified position in the reservoir;
Fig. 4: be the calcspar that writes out data device in the processor of the present invention;
Fig. 5: the order format that is the technology of the present invention;
Fig. 6: the synoptic diagram that is the SCB instruction of the technology of the present invention;
Fig. 7: the synoptic diagram that is the SCW instruction of the technology of the present invention;
Fig. 8: the synoptic diagram that is the SCE instruction of the technology of the present invention;
Fig. 9: be SCB, the SCW of the technology of the present invention and the execution situation of SCE instruction;
Figure 10 a: exemplary applications that is the technology of the present invention;
Figure 11: the Another Application example that is the technology of the present invention.
Embodiment
Fig. 4 shows the calcspar that writes out the device of data in processor of the present invention, and it includes: a whirligig 200, writes out combination working storage 300 (Store Combine Register, STCR) and and selects shade device 400.Wherein, data is to be stored in the inside working storage 100 of this processor, it will be writen to the unjustified position in the storage device 500, this storage device 500 has the word group of a plurality of m bits of being separated by block boundary, in present embodiment, m is preferably 32 bits, that is this storage device 500 is made up of the word group of a plurality of 32 bits.
This whirligig 200 is to be coupled to this inside working storage 100, according to the unjustified address of writing out of this data, rotates to a primary importance with data that should inside working storage 100.This writes out combination working storage 300 is to be coupled to this whirligig 200, with the data of temporary this whirligig 200.This selection shade device 400 is to be coupled to this whirligig 200 and to write out combination working storage 300, according to the unjustified address of writing out of this data, selecting this whirligig 200 of shade and to write out the data of combination working storage 300, and it is writen to this storage device 500.
Write out in the processor of the present invention in the device of data three instructions of definition with to this whirligig 200, write out combination working storage 300 and select shade device 400 to produce relevant control signal.These three instructions are respectively stored combinations initial order (Store Combine Begin, SCB), the instruction of stored combinations word group (Store Combine Word, SCW) and stored combinations END instruction (StoreCombine End, SCE).Its form as shown in Figure 5.
SCB rD, [Addr] instruction as shown in Figure 6, be that working storage rD contents value is rotated 0,1,2 and 3 bit group (byte) respectively according to the address Addr that writes out (s=Addr[1:0]), be written to this again and write out combination working storage 300 (STCR), and respectively after 0,1,2 and 3 bit group of shade, be written to this accumulator apparatus 500 again according to the address Addr that writes out (s=Addr[1:0]).For example, SCB R16, [101h] instruction is according to 1 bit group of address 101h (s=1) rotation of writing out with working storage R16 contents value, be written to this again and write out combination working storage 300 (STCR), and according to after 1 bit group of address 101h (s=1) shade of writing out, be written to this accumulator apparatus 500 address 101h places again, if working storage R16 contents value is ABCD and executes SCB R16, after [101h] instruction, this writes out combination working storage 300 (STCR) contents value is DABC, and accumulator apparatus address 101h to 013h place contents value is ABC, and accumulator apparatus address 100h place contents value does not change.
SCW rD, [Addr] instruction as shown in Figure 7, be that working storage rD contents value is rotated 0,1,2 and 3 bit group respectively according to the address Addr that writes out (s=Addr[1:0]), and according to the address Addr that writes out (s=Addr[1:0]) 0,1,2 and 3 bit group of shade respectively, again be stored in the bit group combination of writing out combination working storage 300 (STCR) after, be written to this accumulator apparatus 500, last, the working storage rD contents value that rotates through is written to this writes out in the combination working storage 300 (STCR).For example, SCW R16, [101h] instruction is according to address 101h (s=1) rotation 1 bit group (DABC) of writing out with working storage R16 contents value (ABCD), and according to address 101h (s=1) 1 bit group of shade (D) of writing out, again be stored in bit group (abcd) the combination back (aABC) of writing out combination working storage 300 (STCR), be written to this accumulator apparatus 500 address 101h places (aABC) again, at last, the working storage rD contents value (DABC) that rotates through is written to this to be write out in the combination working storage 300 (STCR), so execute SCB R16, after [101h] instruction, this writes out combination working storage 300 (STCR) contents value is DABC, and accumulator apparatus address 101h to 013h place contents value is ABC, and accumulator apparatus address 100h place contents value is a.
SCE[Addr] instruction as shown in Figure 8, be the contents value that will write out combination working storage 300 (STCR) according to the address Addr that writes out (s=Addr[1:0]) 0,1,2 and 3 bit group of shade respectively, be written to this accumulator apparatus 500 again.For example, SCW[101h] instruction be will write out the contents value (abcd) of combination working storage 300 (STCR) according to address 101h (s=1) 3 bit groups of shade (bcd) of writing out, be written to this accumulator apparatus 500 address 100h places (a) again, so execute SCE[101h] after the instruction, accumulator apparatus address 101h to 103h place contents value does not change, and accumulator apparatus address 100h place contents value is a.
Fig. 9 then is this SCB rD, [Addr], SCW rD, [Addr] and SCE[Addr] instruct at two kinds of data arrangement mode (little endian, big endian) the various execution situations under, wherein, in this data of writing out in the combination working storage 300 (STCR) is abcd, the data at 100h in reservoir～103h place is XYZW, data in working storage rD is ABCD, it is 4N that s=0 represents institute's access reservoir address, it is 4N+1 that s=1 represents institute's access reservoir address, it is 4N+2 that s=2 represents institute's access reservoir address, and it is 4N+3 that s=3 represents institute's access reservoir address.N is a positive integer.
Figure 10 is the synoptic diagram that shows utilization of the present invention, when desire with one group at working storage R16, when the data among R17 and the R18 (ABCDEFGHIJKL) is written to the 101h of reservoir 500～10Ch position, it is to carry out a SCB R16 earlier, [101h] instruction, so that this working storage R16 contents value (ABCD) is rotated 1 bit group (DABC) (initial rotation step) according to the address 101h (s=1) that writes out, be written to this again and write out combination working storage 300 (STCR), and according to after 1 bit group of address 101h (s=1) shade of writing out, be written to these accumulator apparatus 500 address 101h～103h place (first shade writes out step) again, so execute SCB R16, after [101h] instruction, this writes out combination working storage 300 (STCR) contents value is DABC, and accumulator apparatus address 101h to 103h place contents value is ABC, and accumulator apparatus address 100h place contents value does not change (a).
Thereafter, carry out a SCW R17 again, [105h] instruction, so that working storage R17 contents value (EFGH) is rotated 1 bit group (HEFG) (relaying rotation step) according to the address 105h (s=1) that writes out, and according to address 105h (s=1) 1 bit group of shade (H) of writing out, again be stored in bit group (DABC) the combination back (DEFG) of writing out combination working storage 300 (STCR), be written to 4 Byte 104h～108h place (DEFG) (first writes out step) that this accumulator apparatus 500 comprises address 105h again, at last, the working storage R17 contents value (HEFG) that rotates through is written to this to be write out in the combination working storage 300 (STCR), so execute SCW R17, after [105h] instruction, this writes out combination working storage 300 (STCR) contents value is HEFG, and accumulator apparatus address 104h to 107h place contents value is DEFG.
Afterwards, carry out a SCW R18 again, [109h] instruction, so that working storage R18 contents value (IJKL) is rotated 1 bit group (LIJK) (relaying rotation step) according to the address 109h (s=1) that writes out, and according to address 109h (s=1) 1 bit group of shade (L) of writing out, again be stored in bit group (HEFG) the combination back (HIJK) of writing out combination working storage 300 (STCR), be written to 4 Byte 108h～10Bh (HIJK) (second writes out step) that this accumulator apparatus 500 comprises address 109h place again, at last, the working storage R18 contents value (IJKL) that rotates through is written to this to be write out in the combination working storage 300 (STCR), so execute SCW R18, after [109h] instruction, this writes out combination working storage 300 (STCR) contents value is LIJK, and accumulator apparatus address 108h to 10Ch place contents value is HIJK.
At last, carry out this SCE[10Dh] instruction, it is to write out the contents value (LIJK) of combination working storage 300 (STCR) according to address 10Dh (s=1) 3 bit groups of shade (IJK) of writing out, be written to this accumulator apparatus 500 address 10Ch places (L) (second shade writes out step) again, so execute SCE[10Dh] after the instruction, this writes out combination working storage 300 (STCR) contents value is LIJK, and accumulator apparatus address 10Dh to 10Fh place contents value does not change (n, o, p), and accumulator apparatus address 10Ch place contents value be L.
Figure 11 is the synoptic diagram that shows another utilization of the present invention, when desire with one group of data (ABCD) in working storage R16 be written to reservoir 500 101h～the 104h position constantly, it is to carry out a SCBR16 earlier, [101h] instruction, so that this working storage R16 contents value (ABCD) is rotated 1 bit group (DABC) according to the address 101h (s=1) that writes out, be written to this again and write out combination working storage 300 (STCR), and according to after 1 bit group of address 101h (s=1) shade of writing out, be written to these accumulator apparatus 500 address 101h～103h place again, so execute SCB R16, after [101h] instruction, this writes out combination working storage 300 (STCR) contents value is DABC, and accumulator apparatus address 101h to 013h place contents value is ABC, and accumulator apparatus address 100h place contents value does not change (a).
Thereafter, carry out a SCE[105h] instruction, it is to write out the contents value (DABC) of combination working storage 300 (STCR) according to address 105h (s=1) 3 bit groups of shade (ABC) of writing out, being written to this accumulator apparatus 500 address 104h places (D) again, so execute SCE[105h] after the instruction, this writes out combination working storage 300 (STCR) contents value is DABC, and accumulator apparatus address 105h to 107h place contents value does not change (f, g, h), and accumulator apparatus address 104h place contents value is D.
By above-mentioned explanation as can be known, if the required data length that is writen to the unjustified position of reservoir 500 is n word group, technology of the present invention only needs (n+1) individual instruction just can describe and writes out action, not only can shorten procedure code, only need (n+1) individual instruction cycle just can finish simultaneously and write out action, also significantly improve and carry out efficient.And can not repeat to write out to same reservoir and working storage position, processor pipeline sluggishness (Stall) possibility is reduced, because necessary writing out only done once in same reservoir position, save bus bandwidth, bus bandwidth is used can be reached optimization.
To sum up institute is old, and no matter the present invention all shows it totally different in the feature of prior art with regard to purpose, means and effect, in fact is one to have the invention of practical value.But it should be noted that above-mentioned many embodiment give an example for convenience of explanation.
Claims (20)
1. a method of writing out data in processor is characterized in that, wherein, data is to be writen to unjustified address in the storage device, and this storage device has the word group of a plurality of m bits of being separated by block boundary, and this method mainly comprises:
One initial rotation step is that the unjustified address that this data of retrieval and foundation are write out rotates to primary importance with it, to produce one first rotational information;
One first shade writes out step, is to this first rotational information shade and be writen to this storage device according to the unjustified address that writes out;
One relaying rotation step is the follow-up data of this data of retrieval, according to the unjustified address that writes out it is rotated to primary importance, to produce one second rotational information;
One first writes out step, is that this first rotational information of combination does not write out the part of part and this second rotational information, and is writen to this storage device;
One finishes the rotation step, is that the follow-up data with this data rotates to primary importance, to produce one the 3rd rotational information;
One second writes out step, is the part that this second rotational information of combination does not write out part and the 3rd rotational information, and it is writen to this storage device; And
One second shade writes out step, to the 3rd rotational information shade and be writen to this storage device.
2. the method for claim 1 is characterized in that, wherein, m is 32.
3. method as claimed in claim 2 is characterized in that, it is to right rotation 8 bits that described this rotates to primary importance.
4. method as claimed in claim 2 is characterized in that, it is to right rotation 16 bits that described this rotates to primary importance.
5. method as claimed in claim 2 is characterized in that, it is to right rotation 24 bits that described this rotates to primary importance.
6. a method of writing out in processor is characterized in that, wherein data is to be writen to unjustified address in the storage device, and this storage device has the word group of a plurality of m bits of being separated by block boundary, and this method mainly comprises:
One initial rotation step is that the unjustified address that this data of retrieval and foundation are write out rotates to primary importance with it, to produce one first rotational information;
One first shade writes out step, is to this first rotational information shade and be writen to this storage device according to the unjustified address that writes out; And
One second shade writes out step, is to not writing out part in this first rotational information, carrying out shade and be writen to this storage device.
7. method as claimed in claim 6 is characterized in that, it is less than the m bit that described this first part rotational information does not write out part.
8. method as claimed in claim 6 is characterized in that, wherein, m is 32.
9. method as claimed in claim 8 is characterized in that, it is to right rotation 8 bits that described this rotates to primary importance.
10. method as claimed in claim 8 is characterized in that, it is to right rotation 16 bits that described this rotates to primary importance.
11. method as claimed in claim 8 is characterized in that, it is to right rotation 24 bits that described this rotates to primary importance.
12. device that in processor, writes out data, it is characterized in that, described this data is the inside working storage that is stored in this processor, it will be writen to unjustified address in the storage device, this storage device has the word group of a plurality of m bits of being separated by block boundary, and this device mainly comprises:
One whirligig is to be coupled to this inside working storage, according to the unjustified address of writing out of this data, rotates to a primary importance with data that should the inside working storage;
One writes out the combination working storage, is to be coupled to this whirligig, with the data of temporary this whirligig; And
One selects the shade device, is to be coupled to this whirligig and to write out the combination working storage, writes out unjustified address according to this, selecting this whirligig of shade and to write out the data of combination working storage, and it is writen to this storage device.
13. device as claimed in claim 12, it is characterized in that, described this processor is carried out one first instruction, so that this whirligig is according to the address that writes out of this data, rotate to a primary importance in order to do data that should the inside working storage, to produce one first rotational information, and keep in and write out the combination working storage to this, this selection shade device is according to the address that writes out of this data, selecting this whirligig of shade and to write out the data of combination working storage, and it is writen to this storage device
14. device as claimed in claim 12, it is characterized in that, described this processor is carried out one second instruction, so that this whirligig is retrieved the follow-up data of this data, and rotates to primary importance with it, to produce one second rotational information, and keep in and write out the combination working storage to this, this selection shade device makes up the part that this first rotational information does not write out part and this second rotational information, and is writen to this storage device according to the address that writes out of this data.
15. device as claimed in claim 12, it is characterized in that, described this processor is carried out one the 3rd instruction, so that this whirligig is retrieved the follow-up data of this data, and rotates to primary importance with it, to produce one the 3rd rotational information, and keep in and write out the combination working storage to this, this selection shade device makes up the part that this second rotational information does not write out part and the 3rd rotational information according to the address that writes out of this data, and it is writen to this storage device.
16. device as claimed in claim 12 is characterized in that, described this selection shade device does not write out part according to the address that writes out of this data to the 3rd rotational information, and it is writen to this storage device.
17. device as claimed in claim 12 is characterized in that, wherein, m is 32.
18. device as claimed in claim 17 is characterized in that, described this whirligig is to right rotation 8 bits.
19. device as claimed in claim 17 is characterized in that, described this whirligig is to right rotation 16 bits.
20. device as claimed in claim 17 is characterized in that, described this whirligig is to right rotation 24 bits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101224317A CN100421068C (en) | 2003-12-23 | 2003-12-23 | Method and apparatus for writing out data in processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101224317A CN100421068C (en) | 2003-12-23 | 2003-12-23 | Method and apparatus for writing out data in processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1632743A true CN1632743A (en) | 2005-06-29 |
| CN100421068C CN100421068C (en) | 2008-09-24 |
Family
ID=34844499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101224317A Expired - Fee Related CN100421068C (en) | 2003-12-23 | 2003-12-23 | Method and apparatus for writing out data in processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100421068C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916235A (en) * | 2010-08-02 | 2010-12-15 | 凌阳科技股份有限公司 | Central processing unit and method for storing data thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7051168B2 (en) * | 2001-08-28 | 2006-05-23 | International Business Machines Corporation | Method and apparatus for aligning memory write data in a microprocessor |
| US6721866B2 (en) * | 2001-12-21 | 2004-04-13 | Intel Corporation | Unaligned memory operands |
-
2003
- 2003-12-23 CN CNB2003101224317A patent/CN100421068C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916235A (en) * | 2010-08-02 | 2010-12-15 | 凌阳科技股份有限公司 | Central processing unit and method for storing data thereof |
| CN101916235B (en) * | 2010-08-02 | 2013-09-11 | 凌阳科技股份有限公司 | Central processing unit and method for storing data thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100421068C (en) | 2008-09-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6809964B2 (en) | Nonvolatile semiconductor memory device capable of transferring data internally without using an external bus | |
| US10684778B2 (en) | Data updating in non-volatile memory | |
| US6374337B1 (en) | Data pipelining method and apparatus for memory control circuit | |
| US6611272B1 (en) | Method and apparatus for rasterizing in a hierarchical tile order | |
| US7102646B1 (en) | Demand-based memory system for graphics applications | |
| EP1242868B1 (en) | Organization of blocks within a nonvolatile memory unit to effectively decrease sector write operation time | |
| CN107767324B (en) | Large remote sensing image fast caching method | |
| US20050055493A1 (en) | [method for accessing large block flash memory] | |
| JP4861338B2 (en) | Improving the performance of the memory unit of the data processing device by separating the read function and the fetch function | |
| CN1324480C (en) | NAND flash memory | |
| US20120173795A1 (en) | Solid state drive with low write amplification | |
| CN1659525A (en) | Method and apparatus for multithreaded cache with simplified implementation of cache replacement policy | |
| CN1734431A (en) | Method for software controllable dynamically lockable cache line replacement system | |
| CN1195817A (en) | Method and system for implementing cache coherency mechanism for utilization within non-inclusive cache memory hierarchy | |
| US20040246502A1 (en) | Rendering sub-sections | |
| JPH0661068B2 (en) | Memory relocation method and hierarchical storage system | |
| EP1395951B1 (en) | Method and system for processing two-dimensional image data | |
| CN1632743A (en) | Method and apparatus for writing out data in processor | |
| US8375162B2 (en) | Method and apparatus for reducing write cycles in NAND-based flash memory devices | |
| CN1777875A (en) | Reducing cache trashing of certain pieces | |
| WO2008043287A1 (en) | Configurable single instruction multiple data unit | |
| CN1335958A (en) | Variable-instruction-length processing | |
| CN1152301C (en) | Method and apparatus for loading instruction buffer | |
| CN100495319C (en) | Method and device for reading misaligned data in processor | |
| US4916654A (en) | Method for transfer of data via a window buffer from a bit-planar memory to a selected position in a target memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080924 Termination date: 20141223 |
|
| EXPY | Termination of patent right or utility model |