CN1627283A - Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same - Google Patents

Abstract

Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.

Description

Integrated circuit and method of operating with data antiphase circuit of multidigit prefetch architecture

The application is that the part of No. the 10/397773rd, the U.S. Patent application of on March 26th, 2003 application continues (CIP) application, is incorporated herein that it is open as a reference.Please also require the right of priority of Korean application 2003-90939 number of application on Dec 13rd, 2003 in this, be incorporated herein that it is open as a reference.

Technical field

The present invention relates to integrated circuit (IC)-components, particularly relate to integrated circuit (IC)-components with high data bandwidth.

Background technology

Support the integrated circuit (IC)-components of high data bandwidth may suffer simultaneous switching noise (SimultaneousSwitching Noise, SSN), especially when high frequency switches a plurality of output pins or drives parallel signal line group (for example bus).The routine techniques that reduces SSN comprises the use data antiphase circuit, and the operation of this data antiphase circuit is to be limited in the number of the parallel data signal of switching value during the continuous data output cycle.For example, Fig. 1 shows the routine data negative circuit 10 that comprises input XOR circuit 11, data comparator 13 and output XOR circuit 12.Input XOR circuit 11 receives a plurality of current input signal FDO1-FDO8 and a plurality of previous output signal DO1-DO8 that feeds back from the parallel output pin of data antiphase circuit 10.Exclusive or logic gate in the input XOR circuit 11 produces a plurality of signals that are provided to the input end of data comparator 13.Data comparator 13 is configured to produce marking signal (FLG), as long as data are to (FDO1, DO1), (FDO2, DO2), (FDO3, DO3), (FDO4, DO4), (FDO5, DO5), (FDO6, DO6), (FDO7, O7) and (FDO8, the number of the potential difference DO8) (Δ) is more than or equal to four (4), and this marking signal just has and equals 1 logical value.This marking signal is also censured and is made parity signal (S).Therefore if preceding value=[00000000] of DO1-DO8 and new numerical value=[11111110] of FDO1-FDO8 are so because Δ=7, so marking signal FLG will have 1 value.In the case, new output signal DO1-DO8 will equal [00000001], and meaning only has output pin switching value between old output signal and new output signal.Marking signal FLG also will be provided as the output of data antiphase circuit 10, can correctly decipher their value so that receive the circuit or the device of this output signal.On the contrary, if the new numerical value of the preceding value of DO1-DO8=[00001111] and FDO1-FDO8=[00000001], so because of Δ=3, so marking signal FLG will have 0 value.In the case, will not carry out the data operated in anti-phase by output XOR circuit 12, and the new output signal DO1-DO8 that will produce is [00000001].

It will be appreciated by those skilled in the art that, the reception of the marking signal FLG that receives on the input end of the rejection gate in output XOR circuit 12 may be delayed with respect to the rising edge of current input signal FDO1-FDO8, and described FDO1-FDO8 input signal is to estimate when determining the value of marking signal FLG.Specifically, by rising edge time-delay and that may equal current input signal FDO1-FDO8 of input XOR circuit 11 and data comparator 13 generations with by the delay between the rising of the marking signal FLG that exports XOR circuit 12 receptions.This delay can make the width of the effective window of data (datavalid window) of the output terminal existence of exporting XOR circuit 12 reduce, and therefore reduces the maximum operation frequency of data antiphase circuit 10.

Authorize to disclose in No. the 5931927th, the United States Patent (USP) of Takashima and be used for reducing parallel output signal another routine techniques to the SSN of the integrated circuit of data bus.Specifically, ' 927 Fig. 3 of patent illustrates and produces m-bit data signal and the bit parity signal input/output device to bus.If necessary, can be by half of anti-phase m-bit data signal, so that the number of " 1 " signal value that produces during the output cycle more is approximately equal to the number of " 0 " signal value.Specifically, ' 927 patents show circuit A (left side) and circuit A (right side), and each circuit receives the 1/2m bit data.Ifs circuit A (left side) and circuit A (right side) be receive logic 1 signal, and the parity checking output from two circuit outputs will equal " 1 " so, and it has reflected the fact that existence " 1 " is Duoed than " 0 ".When these take place, the anti-phase sign of data that is produced by exclusive XNOR door will be set as the logical one value.When the anti-phase sign of data is made as the logical one value, the output of circuit A (right side) will be anti-phase by data antiphase circuit so.Thus, output buffer (left side) will receive all " 1 " from circuit A (left side), and output buffer (right side) will receive all " 0 " from data antiphase circuit.The unit output state also will produce a marking signal (F1), in case so that data are passed through bus, can correctly be deciphered from the data of circuit A are anti-phase.

Therefore, in Fig. 3 of ' 927 patents, if be provided to the m-bit data signal of circuit A (left side) and circuit A (right side) during the period 1 be: 11111000 and 00000111, the m-bit data signal that provides during second round is: 00000111 and 11111000, so the anti-phase sign of data will be set, the m-bit data that is provided to bus during the continuous cycle will be:

Period 1: 11,111,000 00000111

↓↓↓↓↓↓↓↓??↓↓↓↓↓↓↓↓

Second round: 00,000,111 11111000 Δs=16

Therefore, use the circuit of Fig. 3 of ' 927 patents, " 1 " that produces during the period 1 and the number of " 0 " are (each eight) that equate, " 1 " that produces during second round and the number of " 0 " also are (each eight) that equate.But the number of the potential difference from the period 1 to the second round (Δ) will equal maximal value 16 (being Δ=16), this means when passing through from the period 1 to the second round, and all output signal lines that arrive bus will switch from high to low or from low to high.Approximately equate level even the sum in the sum of " 1 " during the period 1 and during second round and " 0 " remains, the switching of these high level also may cause unacceptable simultaneous switching noise.

Thus, although there are these classic methods that is used to reduce simultaneous switching noise, still need to handle the data antiphase circuit of high data bandwidth, described data antiphase circuit has high degree of immunity to SSN.Still need simultaneously the data antiphase circuit that can under high frequency, operate.

Summary of the invention

When carrying out high data bandwidth switching manipulation, reduce simultaneous switching noise according to the integrated circuit (IC)-components of the embodiment of the invention.These devices also make it possible to be carried out with series form on data pins by the data that produce and handle with parallel form at first.Can in memory device, produce the data of parallel form, as have double data rate (DDR) (DDR) memory device of 4 look ahead (prefetch), or be configured to drive other devices a plurality of signal wires, that comprise circuit bus driver with parallel data stream.

In some embodiments of the invention, a kind of data antiphase circuit is provided, described data antiphase circuit parallel processing new data and the relevant new data of output data that calculates and before produced, this previous output data that produces is fed as the input of arriving data antiphase circuit.Specifically, data antiphase circuit is configured to by carrying out first group and second position and the bit comparison between the corresponding positions in the group in order in order in data, calculates first group and second potential difference (bit difference) between the group in order in order of the data of its input end parallel receive.Data antiphase circuit also is configured to a half of the figure place in the potential difference number between the form of the first orderly group of data and the second orderly form of organizing is organized in order greater than second of data, in the first orderly form of organizing of the parallel data of the second anti-phase form of organizing in order of its output terminal generation and data.First form of organizing in order of data may be the noninverting form or the anti-phase form of data.

The integrated circuit (IC)-components of an embodiment more according to the present invention comprises data antiphase circuit, and described data antiphase circuit is configured to calculate at least first group and second value of organizing in order in order with orderly group of previous output data parallel present input data.Specifically, data antiphase circuit comprises main combinational logic, be configured to export respectively present input data first in order group and second in order group anti-phase or noninverting form as current output data first in order group and second organize in order.These main combinational logics be configured to orderly group of output data formerly and current output data first in order the anti-phase number (Δ) in position between the group remain on first half of size of group in order that is less than or equal to current output data.This logic also be configured to current output data first in order group and current output data second in order the anti-phase number (Δ) in position between the group remain on second half of size of group in order that is less than or equal to current output data.In this way, experience is transformed into the signal wire of following one-period or the number of pin can keep relatively little from one-period, suppresses simultaneous switching noise thus.In an embodiment more of the present invention, data antiphase circuit can comprise a plurality of delay circuits, is configured to produce orderly group delay form of data.Provide these delay circuits to dwindle data orderly group delay form and the delay surplus between the generation of outer parity signal.

According to an embodiment more of the present invention, a kind of data antiphase circuit with semiconductor devices of multiple position prefetch architecture is provided, this data antiphase circuit comprises a plurality of negative circuits.A plurality of input data that the output data of exporting during a plurality of negative circuit parallel receives and clock period formerly (below be called original input data) is looked ahead simultaneously, for a plurality of input data carry out anti-phase/noninverting, and produce a plurality of output datas.Each of a plurality of negative circuits receives adjacent two the input data on the output order in original input data and a plurality of input data, determine the anti-phase numbers of corresponding positions of two input data, and according to the result who determines be execution in back of two input data anti-phase/noninverting.

Preferably, at least one of a plurality of negative circuits comprises first logical circuit, comparer and second logical circuit.First logical circuit receives the original input data and the first input data in a plurality of input data, and the position that defines how many original input datas is anti-phase with the corresponding positions of the first input data, and exports internal logic signal according to the result who determines.Comparer is the output identification signal in response to internal logic signal.Second logical circuit is anti-phase and export the first input data as first output data of a plurality of output datas or the first not anti-phase input data of output in response to marking signal.

Preferably, at least one of a plurality of negative circuits comprises first logical circuit, comparer, marker generator and second logical circuit.First logical circuit receives J (J is the positive integer greater than 1) input data and the J-1 input data in a plurality of input data, the position that defines how many J input data is anti-phase with the corresponding positions of J-1 input data respectively, exports internal logic signal according to the result who determines.Comparer is exported internal flag signal in response to internal logic signal.The marker generator circuit in response to the J-1 marking signal anti-phase and output internal flag signal as J marking signal or the not anti-phase internal flag signal of output as the J marking signal.Second logical circuit in response to the J marking signal anti-phase and export J input data as the not anti-phase J input data of the J output data in a plurality of output datas or output as the J output data.

Preferably, at least one of a plurality of negative circuits comprises first logical circuit, comparator circuit, selector switch and second logical circuit.First logical circuit receives J (J is the positive integer greater than 1) input data and the J-1 input data in a plurality of input data, the position that defines how many J input data is anti-phase with the corresponding positions of J-1 input data, exports internal logic signal according to the result who determines.Comparator circuit is exported internal flag signal and anti-phase internal flag signal in response to internal logic signal.Selector switch select internal flag signal and anti-phase internal flag signal in response to the J-1 marking signal any one also export selected signal as first marking signal.Second logical circuit is in response to the J marking signal, and is anti-phase and export J input data as J output data in a plurality of output datas and the not anti-phase J input data of output.

Preferably, at least one of a plurality of negative circuits also comprises delay circuit, and this delay circuit receives the first input data, postpones for the first input data schedule time, and the first input data of output delay are to second logical circuit.Wherein the schedule time is up to the time of marking signal from being spent till comparer is exported after the first input data are input to first logical circuit.

Preferably, at least one of a plurality of negative circuits also comprises delay circuit, this delay circuit receives J input data, delay control J imports the data schedule time, and the J of output delay input data are to second logical circuit, and wherein the schedule time is up to exporting the time that is spent till the J marking signal from marker generator after J input data are input to first logical circuit.

According to a further aspect in the invention, a kind of data inversion method of using in the semiconductor devices with multidigit prefetch architecture is provided, this method comprises: (a) output data of exporting during parallel receive and clock period formerly (below, be called original input data) a plurality of input data of looking ahead simultaneously; (b) determine in original input data and a plurality of input data the corresponding positions figure places inverting each other of two adjacent on output order input data, and produce a plurality of marking signals according to the result who determines; And (c) in response to a plurality of marking signals a plurality of input data are carried out anti-phase/noninverting, and produce a plurality of output datas.

Description of drawings

To make above-mentioned and other characteristics of the present invention and advantage become more obvious by the detailed description to its exemplary embodiment with reference to the accompanying drawings, wherein:

Fig. 1 illustrates the routine data negative circuit;

Fig. 2 is the block diagram that comprises according to the semiconductor memory of data antiphase circuit of the present invention;

Fig. 3 is according to the embodiment of the invention, the detailed diagram of data antiphase circuit shown in figure 2;

Fig. 4 is the detailed circuit diagram of first negative circuit shown in Fig. 3;

Fig. 5 is the detailed circuit diagram of second negative circuit shown in Fig. 3;

Fig. 6 is the circuit diagram of the example of the comparer shown in the key diagram 3;

Fig. 7 be according to another embodiment of the present invention, the detailed diagram of data antiphase circuit shown in figure 2;

Fig. 8 is the detailed circuit diagram of second negative circuit shown in Fig. 7;

Fig. 9 is the circuit diagram that illustrates the example of the comparator circuit shown in Fig. 7;

Figure 10 be according to another embodiment of the present invention, the detailed diagram of data antiphase circuit shown in figure 2;

Figure 11 a is the sequential chart that is used for the input signal of second logical circuit shown in Fig. 3;

Figure 11 b is the sequential chart that is used for the input signal of second logical circuit shown in Figure 10; And

Figure 12 is the block diagram of comparing data negative circuit.

Embodiment

Describe the present invention in more detail referring now to accompanying drawing, wherein show the preferred embodiments of the present invention.But the present invention can be with multiple multi-form embodiment, should not be considered as to be limited to embodiment set forth herein; On the contrary, provide these embodiment so that the disclosure is completely and completely, and scope of the present invention is passed to present technique field personnel fully.Identical Reference numeral is represented similar elements all the time, and signal wire thereon can be represented by identical reference symbol with signal.Signal can be considered to different signals synchronously and/or through less Boolean calculation (for example, anti-phase) yet.And, when device or element are represented as response to (a plurality of) signal, can correspond directly to (a plurality of) signal or indirect response in (a plurality of) signal (for example, in response to another (a plurality of) signal of deriving) by described (a plurality of) signal.

Fig. 2 is the block diagram that comprises according to the semiconductor memory of data antiphase circuit of the present invention.Fig. 2 shows the semiconductor memory 100 with 4 prefetch architecture (pre-fetch), comprises 8 DQ pads (pad) DQ1 to DQ8.With reference to figure 2, semiconductor memory 100 comprises memory cell array 110, data antiphase circuit 200, data output state 120 and marking signal buffer 130.Memory cell array 110 in response to the data read command look ahead simultaneously first to fourth input data FDOi_1 to FDOi_4 (i=1 to 8) and and line output first to fourth import data FDOi_1 to FDOi_4.First to fourth input data FDOi_1 to FDOi_4 includes 8 bit data, and each input data is corresponding to 8 DQ pad DQ1 to DQ8.As a result, in response to the data read command, read four group octets data/group (promptly 32) from memory cell array 110.

In Fig. 2, FDOi_1 represents the one digit number certificate that will at first export from i DQ pad, and FDOi_2 represents will be from the one digit number certificate of i DQ pad second output.Equally, FDOi_3 represents will be from the one digit number certificate of i DQ pad the 3rd output, and FDOi_4 represents will be from the one digit number certificate of i DQ pad the 4th output.Therefore, data representation sequence FDO8_1, FDO8_2, FDO8_3 and the FDO8_4 that exports on the 8th DQ pad.

Data antiphase circuit 200 receives first to fourth input data FDOi_1 to FDOi_4 from memory cell array 110 outputs, and whether decision distinguishes each input data of anti-phase first to fourth input data FDOi_1 to FDOi_4.Then, data antiphase circuit 200 is according to the result of decision, anti-phase and export each data of first to fourth not anti-phase input data FDOi_1 to FDOi_4 of each input data of first to fourth input data FDOi_1 to FDOi_4 or output, as first to fourth output data DOi_1 to DOi_4 (i=1 to 8).In addition, data antiphase circuit 200 output identification signal Sj (j=1 to 4), which data among the expression first to fourth input data FDOi_1 to FDOi_4 are by anti-phase.This marking signal also can be called parity signal.

Data output state 120 receives from first to fourth output data DOi_1 to DOi_4 of data antiphase circuit 200 outputs, and exports first to fourth output data DOi_1 to DOi_4 to semiconductor memory 100 outsides by first to the 8th DQ pad DQ1 to DQ8.

Therebetween, the marking signal Sj (j=1 to 4) from data antiphase circuit 200 outputs outputs to semiconductor memory 100 outsides by marking signal buffer 130.Marking signal preferably outputs to semiconductor memory 100 outsides by data masking pin (DM pin hereinafter referred to as).The DM pin is the pin that separates with data pins, is usually included among the SDRAM.In WriteMode, the DM pin is used for sheltering (mask) input data, that is it is used to prevent to import data and writes semiconductor memory.The DM pin is not used in reading mode usually.Thus, because conventional DM pin is used for the output identification signal, so semiconductor memory does not need to be used for the extra pin of output identification signal.

Fig. 3 be according to an embodiment of the invention, the detailed diagram of data antiphase circuit shown in Figure 2.With reference to figure 3, data antiphase circuit 200 comprises first to fourth negative circuit 201 to 204.Fig. 3 shows the data antiphase circuit 200 that comprises according to 4 negative circuits of 4 schemes of looking ahead.The number of the negative circuit that comprises in the data antiphase circuit 200 can change according to the scheme of looking ahead.For example, if use 6 schemes of looking ahead, data antiphase circuit will comprise six negative circuits so.

First to fourth negative circuit 201 to 204 comprises first logical circuit 211 to 214, comparer 221 to 224 and second logical circuit 231 to 234.In addition, second to the 4th negative circuit 202 to 204 also comprises marker generator 242 to 244.In first negative circuit 201,8 the 4th output data DOi_4 ' that first logical circuit 211 receives 8 the first input data FDOi_1 and exports from the 4th negative circuit 204 during the clock period formerly, and output internal logic signal XOi_1 (i=1 to 8).In more detail, first logical circuit 211 is determined the corresponding position anti-phase (toggle) of the first input data FDOi_1 with the 4th output data DOi_4 ' of how many positions, and exports internal logic signal XOi_1 according to determined result.Comparer 221 is exported the first marking signal S1 in response to internal logic signal XOi_1.Second logical circuit 231 is anti-phase and export the first input data FDOi_1 or the not anti-phase first input data FDOi_1 of output as the first output data DOi_1 in response to the first marking signal S1.Here, the 4th output data FDOi_4 ' is latched the circuit (not shown) and latchs.In addition, the first input data FDOi_1 is the data of at first exporting by first to the 8th DQ pad among first to fourth input data FDOi_1, FDOi_2, FDOi_3 and the FDOi_4 that looks ahead at the same time.First negative circuit 201 will be described in more detail with reference to figure 4 in the back.

In second negative circuit 202, first logical circuit 212 receives 8 first input data FDOi_1 and 8 the second input data FDOi_2, output internal logic signal XOi_2 (i=1 to 8).In more detail, first logical circuit 212 determines that the first input data FDOi_1 of how many positions is anti-phase with the corresponding position of the second input data FDOi_2, and exports internal logic signal XOi_2 according to determined result.Comparer 222 is exported the first internal flag signal P1 in response to internal logic signal XOi_2.Marker generator 242 is anti-phase and export the first internal flag signal P1 or the not anti-phase first internal flag signal P1 of output as the second marking signal S2 in response to the first marking signal S1.Second logical circuit 232 is anti-phase and export the second input data FDOi_2 or the not anti-phase second input data FDOi_2 of output as the second output data DOi_2 in response to the second marking signal S2.Here, the second input data FDOi_2 is the data of exporting by first to the 8th DQ pad second in the middle of first to fourth input data FDOi_1, FDOi_2, FDOi_3 and the FDOi_4 that looks ahead at the same time.Second negative circuit 202 will be described in more detail with reference to figure 5 in the back.

In the 3rd negative circuit 203, first logical circuit 213 receives 8 second input data FDOi_2 and 8 the 3rd input data FDOi_3, and output internal logic signal XOi_3 (i=1 to 8).In more detail, first logical circuit 213 determines that the second input data FDOi_2 of how many positions is anti-phase with the corresponding position of the 3rd input data FDOi_3, and exports internal logic signal XOi_3 according to determined result.Comparer 223 is exported the second internal flag signal P2 in response to internal logic signal XOi_3.Marker generator 243 is anti-phase and export the second internal flag signal P2 or the not anti-phase second internal flag signal P2 of output as the 3rd marking signal S3 in response to the second marking signal S2.Second logical circuit 233 is anti-phase and export the 3rd input data FDOi_3 or not anti-phase the 3rd input data FDOi_3 of output as the 3rd output data DOi_3 in response to the 3rd marking signal S3.Here, the 3rd input data FDOi_3 is the data of exporting by first to the 8th DQ pad the 3rd in the middle of first to fourth input data FDOi_1, FDOi_2, FDOi_3 and the FDOi_4 that looks ahead at the same time.

In the 4th negative circuit 204, first logical circuit 214 receives 8 the 3rd input data FDOi_3 and 8 the 4th input data FDOi_4, and output internal logic signal XOi_4 (i=1 to 8).In more detail, first logical circuit 214 determines that the 3rd input data FDOi_3 of how many positions is anti-phase with the corresponding position of the 4th input data FDOi_4, and exports internal logic signal XOi_4 according to determined result.Comparer 224 is exported the 3rd internal flag signal P3 in response to internal logic signal XOi_4.Marker generator 244 is anti-phase and export the 3rd internal flag signal P3 or not anti-phase the 3rd internal flag signal P3 of output as the 4th marking signal P4 in response to the 3rd marking signal S3.Second logical circuit 234 is anti-phase and export the 4th input data FDOi_4 or not anti-phase the 4th input data FDOi_4 of output as the 4th output data DOi_4 in response to the 4th marking signal S4.Here, the 4th input data FDOi_1 is the data of exporting by first to the 8th QD pad the 4th in the middle of first to fourth input data FDOi_1, FDOi_2, FDOi_3 and the FDOi_4 that looks ahead at the same time.Here, comparer 221 to 224 will be described in more detail with reference to figure 6 in the back.

With reference to figure 4 first negative circuit 201 is described in more detail.As shown in Figure 4, first logical circuit 211 of first negative circuit 201 and second logical circuit 231 comprise 8 XOR gate XOR 11 to XOR18 and XOR 21 to XOR 28 respectively.Here, according to the figure place that comprises in one of data of looking ahead at the same time, the number of the XOR gate that comprises in first logical circuit 211 and second logical circuit 231 is different.

The XOR gate XOR 11 to XOR 18 of first logical circuit 211 carries out 8 the first input data FDO1_1 to FDO8_1 and the xor operation from 8 the 4th output data DO1_4 ' of the 4th negative circuit 204 outputs to DO8_4 ' during the clock period formerly, thus output internal logic signal XO1_1 to XO8_1.In more detail, when the first input data FDO1_1 to FDO8_1 and the 4th output data DO1_4 ' were identical to DO8_4, XOR gate XOR 11 to XOR 18 exported internal logic signal XO1_1 to XO8_1 with low level.In addition, when the first input data FDO1_1 to FDO8_1 and the 4th output data DO1_4 ' to DO8_4 ' not simultaneously, that is, when the first input data FDO1_1 to FDO8_1 and the 4th output data DO1_4 ' were anti-phase to the corresponding positions of DO8_4 ', XOR gate XOR 11 to XOR 18 was with high level output internal logic signal XO1_1 to XO8_1.For example, suppose the first input data FDO1_1 to FDO8_1 be " 10001111 " and the 4th output data DO1_4 ' to DO8_4 ' be " 11110000 ".In the case, XOR gate XOR11 is with low level output internal logic signal XO1, and XOR gate XOR 12 to XOR 18 is with high level output internal logic signal XO2_1 to XO8_1.

If half of internal logic signal XO1_1 to XO8_1 or more, that is, four of internal logic signal XO1_1 to XO8_1 or more many places are in high level, comparer 221 receives the first marking signal S1 that internal logic signal XO1_1 to XO8_1 and output have high level so.On the contrary, if fewer than half internal logic signal XO1_1 to XO8_1, that is three of internal logic signal XO1_1 to XO8_1 or still less be in high level, comparer 221 outputs would have the low level first marking signal S1 so.Here, if the first marking signal S1 is in high level, this means first input data FDO1_1 to FDO8_1 and the 4th output data DO1_4 ' to the number of the antiphase of DO8_4 ' be total bit half or more.

The XOR gate XOR 21 to XOR 28 of second logical circuit 231 carries out the xor operation of the first input data FDO1_1 to FDO8_1 and the first marking signal S1 and exports 8 the first output data DO1_1 to DO8_1.Here, if the first marking signal S1 is in high level, the first output data DO1_1 to DO8_1 is identical with the inverse value of the first input data FDO1_1 to FDO8_1 so.In addition, if the first marking signal S1 is in low level, the first output data DO1_1 to DO8_1 is identical with the first input data FDO1_1 to FDO8_1 so.

Next, will second negative circuit 202 be described in more detail with reference to figure 5.First logical circuit 212 and second logical circuit 232 with reference to figure 5, the second negative circuits 202 comprise 8 XOR gate XOR 11 to XOR 18 and XOR 21 to XOR 28 respectively.The XOR gate XOR 11 to XOR 18 of first logical circuit 212 carries out the xor operation of the first input data FDO1_1 to FDO8_1 and the second input data FDO1_2 to FDO8_2 and exports internal logic signal XO1_1 (XO1-2) to XO8_2.Here, the XOR 11 to XOR 18 of first logical circuit 212 operates in the mode identical with the XOR gate XOR 11 to XOR 18 of first logical circuit 211 shown in Fig. 4, therefore omits detailed description.

If half of internal logic signal XO1_2 to XO8_2 or more, that is, four of internal logic signal XO1_2 to XO8_2 or more many places are in high level, comparer 222 receives the first internal flag signal P1 that internal logic signal XO1_2 to XO8_2 and output have high level so.On the contrary, if fewer than half internal logic signal XO1_2 to XO8_2, that is three of internal logic signal XO1_2 to XO8_2 or still less be in high level, comparer 222 outputs would have the low level first marking signal P1 to first node ND1 so.Here, if the first internal flag signal P1 is in high level, half that the anti-phase figure place that this means the first input data FDO1_1 to FDO8_1 and the second input data FDO1_2 to FDO8_2 is a total bit or more.

The marker generator 242 of second negative circuit 202 comprises phase inverter 251 and 252 and switch 253 and 254.In Fig. 5, switch 253 and 254 is nmos pass transistors.Phase inverter 251 anti-phase from first node ND1 output the first internal flag signal P1 and export the first anti-phase internal flag signal P1B.The first marking signal S1 of anti-phase comparer 221 outputs from first negative circuit 201 of phase inverter 252 also exports the first anti-phase marking signal S1B.

The drain electrode of nmos pass transistor 253 is connected to the output terminal of phase inverter 251, and its source electrode is connected to Section Point ND2.In addition, the first marking signal S1 is input to the grid of nmos pass transistor 253.The drain electrode of nmos pass transistor 254 is connected to first node ND1, and its source electrode is connected to Section Point ND2.In addition, the anti-phase first marking signal S1B is input to the grid of nmos pass transistor 254.

Nmos pass transistor 253 is switched in response to the first marking signal S1 or ends, and nmos pass transistor 254 is switched in response to the first anti-phase marking signal S1B or ends.That is, if the first marking signal S1 is in high level, nmos pass transistor 253 conductings so, and nmos pass transistor 254 ends.On the contrary, if the first marking signal S1 is in low level, nmos pass transistor 253 ends so, and nmos pass transistor 254 conductings.

If nmos pass transistor 253 conductings, the first so anti-phase internal flag signal P1B outputs to Section Point ND2 as the second marking signal S2, if and nmos pass transistor 254 conductings, the first internal flag signal P1 outputs to Section Point ND2 as the second marking signal S2 so.

As a result, marker generator 242 is according to the level of the first marking signal S1, and is anti-phase and export the first not anti-phase internal flag signal P1 of the first internal flag signal P1 or output as the second marking signal S2.

The XOR gate XOR 21 to XOR 28 of second logical circuit 232 carries out the xor operation of the first input data FDO1_1 to FDO8_1 and the second marking signal S2 and exports the second output data DO1_2 to DO8_2.Here, if the second marking signal S2 is in high level, the second output data DO1_2 to DO8_2 is identical with the inverse value of the first input data FDO1_1 to FDO8_1 so.In addition, if the second marking signal S2 is in low level, the second output data DO1_2 to DO8_2 is identical with the first input data FDO1_1 to FDO8_1 so.

Here, third and fourth negative circuit 203 is operated in the mode identical with second negative circuit 202 with 204.

Next, will comparer shown in Figure 3 221 to 224 be described in more detail with reference to figure 6.With reference to figure 6, comparer 221 to 224 comprises comparison voltage generator circuit 310, pedestal generator circuit 320 and differential amplifier 330 respectively.

Comparison voltage generator circuit 310 produces comparative voltage VCOM and exports comparative voltage VCOM to output node OUT1 in response to the internal logic signal XO1_j to XO8_j (j=1 to 4) that exports respectively from first logical circuit 211 to 214.Comparison voltage generator circuit 310 comprises a PMOS transistor WP and 8 nmos pass transistor WN.

The source electrode of PMOS transistor WP is connected to builtin voltage VDD, and its grid is connected to ground voltage, and its drain electrode is connected to output node OUT1.The drain electrode of 8 nmos pass transistor WN is connected to output node OUT1, and its source electrode is connected to ground voltage.In addition, internal logic signal XO1_j to XO8_j is input to the grid of 8 nmos pass transistor WN respectively.Nmos pass transistor WN is switched in response to internal logic signal XO1_j to XO8_j or ends.Here, when the number of the nmos pass transistor WN of conducting increased, the level of comparative voltage VCOM reduced.

Pedestal generator circuit 320 produces the reference voltage V REF of predetermined reference voltage V REF and output generation to output node OUT2.Pedestal generator circuit 320 comprises 1 PMOS transistor WP and 8 nmos pass transistor WN and WN '.The source electrode of PMOS transistor WP is connected to builtin voltage VDD, and its grid is connected to ground voltage, and its drain electrode is connected to output node OUT2.The drain electrode of 8 nmos pass transistor WN and WN ' is connected to output node OUT2, and its source electrode is connected to ground voltage.The grid of four NMOS transistors WN among 8 nmos pass transistor WN and the WN ' is connected to ground voltage, and remaining four NMOS transistors WN and the grid of WN ' are connected to builtin voltage VDD.Here, the size of nmos pass transistor WN ' is set as 1/2 of the size that is approximately other nmos pass transistors WN.

The level of reference voltage V REF is connected to nmos pass transistor WN and the WN ' decision of builtin voltage VDD by its grid.That is when three nmos pass transistor WN and size were 1/2 the nmos pass transistor WN ' conducting of nmos pass transistor WN, reference voltage V REF was the voltage that produces at output node OUT2 place.

Thus, when the WN of the four NMOS transistors at least conducting in the comparison voltage generator circuit 310, the level of comparative voltage VCOM becomes less than the level of reference voltage V REF.

Differential amplifier 330 is compared comparative voltage VCOM and output identification signal S1 (or Pk, k=1 to 3) with reference voltage V REF.In more detail, as comparative voltage VCOM during less than reference voltage V REF, differential amplifier 330 outputs have the marking signal S1 (or Pk) of high level.In addition, as comparative voltage VCOM during greater than reference voltage V REF, differential amplifier 330 outputs have low level marking signal S1 (or Pk).

Next, the operation of describing according to the data antiphase circuit 200 of the embodiment of the invention with reference to figure 3 to 6.Table 1 has been listed the example values of the 4th output data DOi_4 ' that exports during the cycle formerly and the example values of the first to fourth input data FDOi_1 to FDOi_4 that looks ahead simultaneously.

[table 1]

Data	Place value
									?i＝1	?i＝2	?i＝3	?i＝4	??i＝5	??i＝6	??i＝7	??i＝8
	?DOi_4’	?1	?1	?0	?0	??0	??0	??1									??1
?FDOi_1									?1	?1	?1	?1	??1	??1	??0	??0
	?FDOi_2	?1	?1	?1	?1	??1	??1	??0									??1
?FDOi_3									?1	?0	?0	?0	??0	??0	??0	??1
	?FDOi_4	?1	?0	?0	?0	??0	??0	??1									??0

Be received in output with reference to each of first logical circuit 211 to 214 of figure 3, first to fourth negative circuits 201 to 204 and go up two adjacent data in proper order, carry out the xor operation of two adjacent datas, and output internal logic signal XOi_1 to XOi_4.

Output be in proper order first to fourth input data FDOi_1 to FDOi_4 200 anti-phase by data antiphase circuit/noninverting after, first to fourth input data FDOi_1 to FDOi_4 outputs to semiconductor memory 100 order when outside.In Fig. 3, the order of importing data FDOi_4 with the first input data FDOi_1, the second input data FDOi_2, the 3rd input data FDOi_3 and the 4th outputs to semiconductor memory 100 outsides with first to fourth anti-phase or noninverting input data FDOi_1 to FDOi_4.Thus, two adjacent data are respectively the first input data FDOi_1 and the second input data FDOi_2 on the output order, the second input data FDOi_2 and the 3rd input data FDOi_3, and the 3rd input data FDOi_3 and the 4th input data FDOi_4.First logical circuit 212 to 214 receives two adjacent data respectively.

In addition, owing to exported the 4th output data DOi_4 ' during the clock period formerly, therefore the output of the 4th output data DOi_4 ' is in proper order before the output order of the first input data FDOi_1.Thus, first logical circuit 211 receives the 4th output data DOi_4 ' and the first input data FDOi_1.

First logical circuit 211 to 214 is operated simultaneously.That is, when 211 operations of first logical circuit, 212 to 214 operations of first logical circuit.

Internal logic signal XOi_1 to XOi_4 represents to be input to two figure places that adjacent data are inverting each other of first logical circuit 211 to 214.

Carry out as the 4th output data DO1_4 ' to DO8_4 ' " 11000011 " with as the xor operation of the first input data FDO1_1 to FDO8_1 " 11111100 " with reference to the XOR gate XOR 11 to XOR 18 of figure 4, the first logical circuits 211.Here, because all except FDO1_1 and FDO2_1 of the remaining bit except position DO1_4 ' and DO2_4 ' of the 4th output data and the first input data are anti-phase, so XOR gate XOR 11 to XOR 18 outputs " 00111111 " are as internal logic signal XO1_1 to XO8_1.

Carry out as the first input data FDO1_1 to FDO8_1 " 11111100 " with as the xor operation of the second input data FDO1_2 to FDO8_2 " 11111101 " with reference to the XOR gate XOR 11 to XOR 18 of figure 5, the first logical circuits 212.Here, owing to the position FDO8_2 of the position FDO8_1 that has only the first input data and the second input data is anti-phase, so XOR gate XOR 11 to XOR 18 exports " 00000001 " as internal logic signal XO1_2 to XO8_2.

First logical circuit 213 is operated in the mode identical with first logical circuit 212 with 214, respectively output " 01111100 " as internal logic signal XO1_3 to XO8_3 and " 00000011 " as internal logic signal XO1_4 to XO8_4.

Then, the comparer 221 to 224 of first to fourth negative circuit 201 to 204 according to internal logic signal XOi_1 to XOi_4 determine the number of antiphase whether be total bit half or more, and according to the determined signal of output identification as a result S1 (or Pk).Here, comparer 221 to 224 is operated simultaneously.

In more detail, with reference to figure 6, " 00111111 " is imported into the comparison voltage generator circuit 310 of comparer 221 as internal logic signal XO1_1 to XO8_1.As a result, 6 the nmos pass transistor WN conducting in the comparison voltage generator circuit 310, and the level that outputs to the comparative voltage VCOM of output node OUT1 becomes less than reference voltage V REF.Because comparative voltage VCOM is less than reference voltage V REF, so the differential amplifier 330 outputs first marking signal S1.

In addition, " 00000001 " is input to the comparison voltage generator circuit 310 of comparer 222 as internal logic signal XO1_2 to XO8_2.The result, in comparison voltage generator circuit 310, nmos pass transistor WN conducting is only arranged, and the comparative voltage VCOM that outputs to output node OUT1 becomes greater than reference voltage V REF, because comparative voltage VCOM is greater than reference voltage V REF, differential amplifier 330 outputs have the low level first marking signal P1.

Comparer 223 is also operated in the mode identical with comparer 222 with 224, and output has the second internal flag signal P2 of high level and has low level the 3rd marking signal P3 respectively.

Then, the marker generator 242 to 244 of second to the 4th negative circuit 202 to 204 is sequentially operated, and sequentially produces second to the 4th marking signal S2 to S4.That is marker generator 242 produces the second marking signal S2, and marker generator 243 produces the 3rd marking signal S3, and marker generator 244 produces the 4th marking signal S4 then.

In more detail, with reference to figure 5, because the first marking signal S1 is in high level, nmos pass transistor 253 conductings of marker generator 242, and nmos pass transistor 254 ends.As a result, marker generator 242 is anti-phase to have the low level first internal flag signal P1, and exports the first anti-phase internal flag signal P1B as the S2 with high level.

Marker generator 243 is operated in the mode identical with marker generator 242 with 244, and output has low level the 3rd marking signal S3 and has low level the 4th marking signal S4 respectively.

Here, in table 2, listed internal logic signal XOi_1 to XOi_4, first to fourth marking signal S1 to S4 and first to the 3rd internal flag signal P1 to P3 that produces by data antiphase circuit 200.

[table 2]

Signal	Logic level
									??i＝1	??i＝2	??i＝3	??i＝4	????i＝5	??i＝6	??i＝7	??i＝8
	??XOi_1	??0	??0	??1	??1	????1	??1	??1									??1
??XOi_2									??0	??0	??0	??0	????0	??0	??0	??1
	??XOi_3	??0	??1	??1	??1	????1	??1	??0									??0
??XOi_4									??0	??0	??0	??0	????0	??0	??1	??1
	??P1	???????????????????????????????0
??P2										???????????????????????????????1
	??P3	???????????????????????????????0
??S1										???????????????????????????????1
	??S2	???????????????????????????????1
??S3										???????????????????????????????0
	??S4	???????????????????????????????0

Next, second logical circuit 231 to 234 of first to fourth negative circuit 201 to 204 is in response to first to fourth marking signal S1 to S4, and is anti-phase and export first to fourth not anti-phase input data FDOi_1 to FDOi_4 of first to fourth input data FDOi_1 to FDOi_4 or output as first to fourth output data DOi_1 to DOi_4.Here, second logical circuit 231 to 234 is sequentially operated.Thus, sequentially export the first output data DOi_1, the second output data DOi_2, the 3rd output data DOi_3 and the 4th output data DOi_4.

Carry out as the first input data FDO1_1 to FDO8_1 " 11111100 " and have the xor operation of the first marking signal S1 of high level with reference to the XOR gate XOR 21 to XOR 28 of figure 4, the second logical circuits 231.Because the first marking signal S1 is in high level, the inverse value " 00000011 " of XOR gate XOR 21 to the XOR 28 outputs first input data FDO1_1 to FDO8_1 of second logical circuit 231 is as the first output data DO1_1 to DO8_1.Carry out as the second input data FDO1_2 to FDO8_2 " 11111101 " and have the xor operation of the second marking signal S2 of high level with reference to the XOR gate XOR 21 to XOR 28 of figure 5, the second logical circuits 232.Because the second marking signal S2 is in high level, the inverse value " 00000010 " of XOR gate XOR 21 to the XOR 28 outputs second input data FDO1_2 to FDO8_2 of second logical circuit 232 is as the second output data DO1_2 to DO8_2.Second logical circuit 233 is also operated in the mode identical with second logical circuit 232, and exports the 3rd input data FDO1_3 to FDO8_3 " 10000001 " as the 3rd not anti-phase output data DO1_3 to DO8_3.In addition, the 4th input data FDO1_4 to FDO8_4 " 10000010 " are operated and exported to second logical circuit 234 also as the 4th not anti-phase output data DO1_4 to DO8_4 in the mode identical with second logical circuit 232.Here, in table 3, listed first to fourth DOi_1 to the DOi_4 output data of exporting by second logical circuit 231 to 234.

[table 3]

Data	Place value
									??i＝1	??i＝2	??i＝3	??i＝4	??i＝5	??i＝6	??i＝7	??I＝8
	??DOi_1	??0	??0	??0	??0	??0	??0	??1									??1
??DOi_2									??0	??0	??0	??0	??0	??0	??1	??0
	??DOi_3	??1	??0	??0	??0	??0	??0	??0									??1
??DOi_4									??1	??0	??0	??0	??0	??0	??1	??0

As can be seen from Table 3, compare with the number of the antiphase of listed first to fourth input data FDOi_1 to FDOi_4 in the above-mentioned table 1, by data antiphase circuit 200 anti-phase/number of the antiphase of noninverting first to fourth output data DOi_1 to DOi_4 is significantly reduced.

Fig. 7 be according to another embodiment of the present invention, in the detailed diagram of the data antiphase circuit shown in Fig. 2.With reference to figure 7, data antiphase circuit 400 comprises first to fourth negative circuit 401 to 404.Fig. 7 shows the example data negative circuit 400 of looking ahead based on 4, comprise 4 negative circuits.Here, first negative circuit 401 is operated in the mode identical with first negative circuit 201 shown in Fig. 3 and 4, therefore omits detailed description.In addition, second to the 4th negative circuit 402 to 404 is except following difference, to operate to the identical mode of the 4th negative circuit with second shown in Fig. 3.

First difference is comparer 221 to 224 outputs first to the 3rd internal flag signal P1 to P3 of second to the 4th negative circuit 202 to 204, and internal flag signal P1, P1B to P3, the P3B of comparator circuit 422 to 424 outputs first to the 3rd complementation of second to the 4th negative circuit 402 to 404.Second difference is that second to the 4th negative circuit 202 to 204 comprises marker generator 242 to 244, and second to the 4th negative circuit 402 to 404 comprises selector switch 442 to 444.

With reference to figure 8, second to the 4th negative circuit 402 to 404 is described in more detail according to these two differences.Fig. 8 is the detailed circuit diagram of second negative circuit shown in Fig. 7.Here, third and fourth negative circuit 403 is operated in the mode identical with second negative circuit 402 with 404, therefore will provide description according to second negative circuit 402 in Fig. 8.First logical circuit 412 of second negative circuit 402 and second logical circuit 432 comprise 8 XOR gate XOR 11 to XOR 18 and XOR 21 to XOR 28 respectively.The XOR gate XOR 11 to XOR 18 of first logical circuit 412 carries out the xor operation of the first input data FDO1_1 to FDO8_1 and the second input data FDO1_2 to FDO8_2, and output internal logic signal XO1_2 to XO8_2.

Comparator circuit 422 comprises comparer 451 and phase inverter 452.If half of internal logic signal XO1_2 to XO8_2 or more many places are in high level, comparer 451 receives the first internal flag signal P1 that internal logic signal XO1_2 to XO8_2 and output have high level so.On the contrary, if be in high level less than half internal logic signal XO1_2 to XO8_2 (three or still less), comparer 222 outputs have the low level first internal flag signal P1 so.Here, comparer 451 is operated in the mode identical with the comparer 221 to 224 shown in Fig. 6, therefore omits detailed description.The phase inverter 452 anti-phase first internal flag signal P1, and export the first anti-phase internal flag signal P1B.

The selector switch 442 of second negative circuit 402 comprises phase inverter 461 and switch 462 and 463.In Fig. 8, switch 462 and 463 can be a nmos pass transistor.The phase inverter 461 anti-phase first marking signal S1 that export from the comparer 421 of first negative circuit 401, and export the first anti-phase marking signal S1B.

The drain electrode of nmos pass transistor 462 is connected to the output terminal of phase inverter 452, and source electrode is connected to node ND.In addition, the first marking signal S1 is imported into the grid of nmos pass transistor 462.The drain electrode of nmos pass transistor 463 is connected to the output terminal of comparer 451, and source electrode is connected to node ND.In addition, the anti-phase first marking signal S1B is input to the grid of nmos pass transistor 463.

Nmos pass transistor 462 is switched in response to the first marking signal S1 or ends, and nmos pass transistor 463 is switched in response to the first anti-phase marking signal S1B or ends.That is, if the first marking signal S1 is in high level, nmos pass transistor 462 conductings so, and nmos pass transistor 463 ends.On the contrary, if the first marking signal S1 is in low level, nmos pass transistor 462 ends so, and nmos pass transistor 453 conductings.

If nmos pass transistor 462 conductings, the first anti-phase internal flag signal P1B is output to node ND as the second marking signal S2.If nmos pass transistor 463 conductings, the first internal flag signal P1 is output to node ND as the second marking signal S2.As a result, selector switch 442 is selected any one of the first internal flag signal P1 and the anti-phase first internal flag signal P1B according to the level of the first marking signal S1, and exports selected signal as the second marking signal S2.

The XOR gate XOR 21 to XOR 28 of second logical circuit 432 carries out the xor operation of the second input data FDO1_2 to FDO8_2 and the second marking signal S2, and exports the second output data DO1_2 to DO8_2.Here, if the second marking signal S2 is in high level, the second output data DO1_2 to DO8_2 is identical with the inverse value of the second input data FDO1_2 to FDO8_2 so.In addition, if the second marking signal S2 is in low level, the second output data DO1_2 to DO8_2 is identical with the second input data FDO1_2 to FDO8_2 so.

Fig. 9 is the circuit diagram of the example of the comparator circuit shown in the key diagram 7.With reference to figure 9, each comparator circuit 422 to 424 comprises comparison voltage generator circuit 510, pedestal generator circuit 520 and internal flag signal generator circuit 530.Here, comparison voltage generator circuit 510 and pedestal generator circuit 520 are operated in the mode identical with comparison voltage generator circuit 310 shown in Figure 6 and pedestal generator circuit 320, therefore omit detailed description.

Internal flag signal generator circuit 530 comprises differential amplifier circuit 540 and output circuit 550 and 560.Differential amplifier circuit 540 comprises difference nmos pass transistor NM1 and NM2, amplifier PMOS transistor PM1 and PM2, amplifier nmos pass transistor NM3 and NM4, PMOS transistor PM3 to PM6 and current source nmos transistor NM5 reset.

The drain electrode of difference nmos pass transistor NM1 and NM2 is connected respectively to first output line L1 and the L1B, and comparative voltage VCOM and reference voltage V REF are input to the grid of difference nmos pass transistor NM1 and NM2 respectively.Difference nmos pass transistor NM1 and NM2 compare comparative voltage VCOM and reference voltage V REF, and respectively output signal output VO and VOB to first output line L1 and the LIB.

Amplifier PMOS transistor PM1 and PM2 and the second output line L2 and L2B cross-couplings, the source electrode of amplifier PMOS transistor PM1 and PM2 is connected to builtin voltage VDD.Amplifier nmos pass transistor NM3 and NM4 also with the second output line L2 and L2B cross-couplings, the source electrode of amplifier nmos pass transistor NM3 and NM4 also is connected respectively to first output line L1 and the L1B.Amplifier PMOS transistor PM1 and PM2 and amplifier nmos pass transistor NM3 and NM4 amplification are sent to output signal VO and the VOB of the first output line L1 and L1B and export institute's result amplified to second output line L2 and the L2B.Thus, node D1 and the D2 from the second output line L2 and L2B exports amplified output signal VO and VOB respectively.

Control signal PCOM is input to the grid of the PMOS transistor PM3 to PM6 that resets.Here, control signal PCOM is in response to read command, from the signal of additional control circuit (not shown) generation.The source electrode of PMOS transistor PM3 and PM4 of resetting is connected to builtin voltage VDD, and its drain electrode is connected respectively to second output line L2 and the L2B.Source electrode and the drain electrode of PMOS transistor PM5 of resetting is connected respectively to second output line L2 and the L2B, and the source electrode of the PMOS transistor PM6 that resets and drain electrode are connected respectively to first output line L1 and the L1B.The PMOS transistor PM3 to PM6 that resets is switched in response to control signal PCOM or ends.When conducting, the voltage level of reset PMOS transistor PM3 to PM6 precharge first output line L1 and L1B and the second output line L2 and L2B is to the level of builtin voltage VDD.

The drain electrode of current source nmos transistor NM5 is connected to the source electrode of difference nmos pass transistor NM1 and NM2, and the source electrode of current source nmos transistor NM5 is connected to ground voltage.Control signal PCOM is input to the grid of current source nmos transistor NM5.Current source nmos transistor NM5 is switched in response to control signal PCOM or ends, and the operation of the source of use current IS control differential amplifier circuit 540.

Output circuit 550 and 560 comprises negative circuit 551 and 561 and latch cicuit 552 and 562 respectively.Negative circuit 551 comprises PMOS transistor PM7 and PM8 and nmos pass transistor NM6 and NM7.The source electrode of PMOS transistor PM7 is connected to builtin voltage VDD, with and drain electrode be connected to the source electrode of PMOS transistor PM8.Control signal PCOMB is input to the grid of PMOS transistor PM7.Control signal PCOMB is the inversion signal of control signal PCOM.

The grid of PMOS transistor PM8 and nmos pass transistor NM6 is connected to node D1.The drain electrode of nmos pass transistor NM7 is connected to the source electrode of nmos pass transistor NM6, and the source electrode of nmos pass transistor NM7 is connected to ground voltage.Control signal PCOM is input to the grid of nmos pass transistor 7NM.In addition, the drain electrode of PMOS transistor PM8 and nmos pass transistor NM6 is connected to the input end of latch cicuit 552.Negative circuit 551 is in response to control signal PCOM and PCOMB and anti-phase output signal VO from node D1 output.Latch cicuit 552 latchs the output signal of negative circuit 551, and output institute latched signal is as internal flag signal Pk.

Negative circuit 561 comprises PMOS transistor PM9 and PM10 and nmos pass transistor NM8 and NM9.The source electrode of PMOS transistor PM9 is connected to builtin voltage VDD, with and drain electrode be connected to the source electrode of PMOS transistor PM10.In addition, control signal PCOMB is connected to the grid of PMOS transistor PM9.The grid of PMOS transistor PM10 and nmos pass transistor NM8 is connected to node D2.The drain electrode of nmos pass transistor NM9 is connected to the source electrode of nmos pass transistor NM8, and the source electrode of nmos pass transistor NM9 is connected to ground voltage.Control signal PCOM is input to the grid of nmos pass transistor NM9.The drain electrode of PMOS transistor PM10 and nmos pass transistor NM8 is connected to the input end of latch cicuit 562.Negative circuit 561 is in response to control signal PCOM and the anti-phase output signal VOB from node D2 output of PCOMB.Latch cicuit 562 latchs the output signal of negative circuit 561, and output institute latched signal is as internal flag signal PkB.As a result, from complementary internal flag signal Pk and the PkB of differential amplifier 540 outputs.

Next, the operation of aforesaid comparator circuit 422 and 424 is described.Comparison voltage generator circuit 510 produces comparative voltage VCOM in response to internal logic signal XO1_j to XO8_j.Pedestal generator circuit 520 produces predetermined reference voltage V REF.Here, if half of internal logic signal XO1_j to XO8_j or more (four or more) are in high level, comparative voltage VCOM becomes less than reference voltage V REF so.On the contrary, if be in high level less than the internal logic signal XO1_j to XO8_j of half (three or still less), comparative voltage VCOM becomes greater than reference voltage V REF so.In Fig. 9, the internal logic signal XO1_j to XO8_j that has described half or more (four or more) is in the example of high level.Thus, comparative voltage VCOM becomes less than reference voltage V REF.

Next, make control signal PCOM be in high level.In response to control signal PCOM, the current source nmos transistor NM5 conducting of differential amplifier circuit 540, the PMOS transistor PM3 to PM6 that resets ends.Difference nmos pass transistor NM1 and NM2 compare comparative voltage VCOM and reference voltage V REF, and respectively output signal output VO and VOB to first output line L1 and the L1B.Here, since comparative voltage VCOM less than reference voltage V REF, so the conduction resistance value of difference nmos pass transistor NM1 is greater than the conduction resistance value of difference nmos pass transistor NM2.As a result, the voltage level of output signal VOB becomes and is lower than the voltage level of output signal VO.

Amplifier PMOS transistor PM1 and PM2 and amplifier nmos pass transistor NM3 and NM4 amplify output signal VO and the VOB that is sent to the first output line L1 and L1B, and output institute amplifying signal is to second output line L2 and the L2B.After this, have the output signal VO of high level, and have low level output signal VOB from the node D2 output of the second output line L2B from the node D1 of second output line L2 output.

Output circuit 550 and 560 negative circuit 551 and 561 are respectively in response to control signal PCOM and PCOMB and reversed-phase output signal VO and VOB, output circuit 550 and 560 latch cicuit 552 and 562 latch the output signal of negative circuit 551 and 561 respectively in addition, and output institute latched signal is as internal flag signal Pk and PkB.That is latch cicuit 552 latchs the low level output signal that has from negative circuit 551 outputs, and output has the internal flag signal Pk of high level.In addition, latch cicuit 562 latchs from the output signal with high level of negative circuit 561 outputs, and output has low level internal flag signal PkB.

If the latch operation of latch cicuit 552 and 562 is finished, control signal PCOM is under an embargo and is in low level so.In response to control signal PCOM, PMOS transistor PM3 to PM6 conducting resets.Reset the voltage level of PMOS transistor PM3 to PM6 precharge first output line L1 and L1B and the second output line L2 and L2B to the level of builtin voltage VDD, be used for next compare operation of differential amplifier circuit 540.In addition, in response to control signal PCOM, current source nmos transistor NM5 ends.In addition, if control signal PCOM is under an embargo and is in low level, PMOS transistor PM7 and PM9 and nmos pass transistor NM7 and NM9 end so, and negative circuit 551 and 561 is under an embargo.

As a result, although the voltage level of the second output line L2 and L2B is precharged to the level of builtin voltage VDD, the output channel from node D1 and D2 to latch cicuit 552 and 562 is prevented from by negative circuit 551 and 561.Thus, become the output signal VO and internal flag signal Pk and the PkB not influence of VOB of the level of builtin voltage VDD to latching in advance by latch cicuit 552 and 562.

Figure 10 be according to another embodiment of the present invention, the detailed diagram of data antiphase circuit shown in Figure 2.With reference to Figure 10, data antiphase circuit 600 comprises first to fourth negative circuit 601 to 604.Here, first to fourth negative circuit 601 to 604 is operated in the mode identical with first to fourth negative circuit 201 to 204 shown in Fig. 3 except following difference, therefore omits detailed description.

This difference is to compare with first to fourth negative circuit 201 to 204, and first to fourth negative circuit 601 to 604 also comprises delay circuit 651 to 654.

At the fixed time, delay circuit 651 to 654 postpones first to fourth input data FDOi_1 to FDOi_4 respectively, and first to fourth input data DFDOi_1 to DFDOi_4 of difference output delay.In other words, be input to first logical circuit 611 after 614 at first to fourth input data FDOi_1 to FDOi_4, finally export the time durations that is spent from comparer 621 and marker generator 642 to 644 up to first to fourth marking signal S1 to S4, delay circuit 65_1 to 654 postpones first to fourth input data FDOi_1 to FDOi_4.

As a result, first to fourth of first to fourth marking signal S1 to S4 and delay input data DFDOi_1 to DFDOi_4 is input to second logical circuit 631 to 634 of first to fourth negative circuit 601 to 604 simultaneously.Therefore, the valid window (valid window) that is input to two signals of second logical circuit 631 to 634 respectively can keep maximal value.

Here, preferably be provided with the time delay of delay circuit 651 to 654 with differing from one another.For example, represent by T1, T2, T3 and T4 respectively the time delay of delay circuit 651 to 654.In addition, represent by TD the time delay of first logical circuit 611 to 614, represent by TC the time delay of comparer 621 to 624, represent by TF the time delay of marker generator 642 to 644.In the case, represent T1 to T4 time delay by following equation.

T1＝TD+TC，

T2＝T1+TF，

T3＝T2+TF，

T4＝T3+TF

.....(1)

As above-mentioned equation 1 finding, the T1 to T4 time delay of delay circuit 651 to 654 has the relation of T1＜T2＜T3＜T4.That is, elongated in the time delay of 654 direction delay circuit 651 to 654 from delay circuit 651 to delay circuit.After the marker generator 642 outputs second marking signal S2, marker generator 643 is exported the 3rd marking signal S3 according to the level of the second marking signal S2.Thus, T3 time delay of delay circuit 653 should be made as compensation by marker generator 642 and 643 time delays that produce.Equally, after marker generator 643 outputs the 3rd marking signal S3, marker generator 644 is exported the 4th marking signal S4 according to the level of the 3rd marking signal S3.Thus, T4 time delay of delay circuit 654 should be made as the time delay that compensation is produced by marker generator 642 to 644.

Next, with reference to figure 11a and 11b, the valid window interval of the valid window of the internal signal that produces when describing data antiphase circuit 200 operations as Fig. 3 internal signal of generation during at interval and when data antiphase circuit 600 operations.Figure 11 a is the sequential chart of the input signal of second logical circuit 231 to 234 shown in Fig. 3.Figure 11 b is the sequential chart of the input signal of second logical circuit 631 to 634 shown in Figure 10.

With reference to figure 11a and Fig. 3, first to fourth input data FDOi_1 to FDOi_4 is input to first logical circuit 211 to 214 and second logical circuit 231 to 234 simultaneously.But first to fourth marking signal S4 to S4 is delayed the time of the first to fourth input data FDOi_1 to FDOi_4 that is handled by first logical circuit 211 to 214 and comparer 221 to 224, is input to second logical circuit 231 to 234 then.As a result, between first to fourth input data FDOi_1 to FDOi_4 and first to fourth marking signal S1 to S4, produce invalid interval IV.Thus, the public significant interval V1 between first to fourth input data FDOi_1 to FDOi_4 and first to fourth marking signal S1 to S4, promptly effective anti-phase window interval reduces.The valid window this frequency of operation that reduces to limit semiconductor devices at interval.

On the contrary, in data antiphase circuit 600, first to fourth input data FDOi_j to FDOi_4 is delayed circuit 651 to 654 to postpone.Thus, with reference to figure 11b, first to fourth input data DFDOi_1 to DFDOi_4 of first to fourth marking signal S1 to S4 and delay is input to second logical circuit 631 to 634 simultaneously.As a result, between first to fourth input data FDOi_1 to FDOi_4 that postpones and first to fourth marking signal S1 to S4, do not produce invalid interval.Thus, can guarantee that the first to fourth public significant interval V2 that imports between data DFDOi_1 to DFDOi_4 and the first to fourth marking signal S1 to S4 that postpones is in maximal value.Here, delay circuit 651 to 654 can be applicable to data antiphase circuit shown in Figure 7 400.

As mentioned above, carry out the process of the figure place of determining that a plurality of data look ahead simultaneously are inverting each other simultaneously according to data antiphase circuit of the present invention and produce the process of marking signal according to determined result.In fact, data antiphase circuit consumes long time and produces marking signal.Can reduce data processing time significantly according to data antiphase circuit of the present invention, and can have the semiconductor devices high speed deal with data of multidigit prefetch architecture thus.

In addition, according to embodiments of the invention, according to the anti-phase figure place of past data and current data, anti-phase output or not anti-phase output internal flag signal, anti-phase or not anti-phase internal flag signal is with acting on anti-phase/noninverting marking signal of controlling current data.Thus, compare with the routine techniques that stands anti-phase/not anti-phase past data, can reduce the anti-phase time that spends of data and improve the frequency of operation of semiconductor devices with current data relatively.

Simultaneously, in data antiphase circuit, the logical circuit whether specified data is inverting each other and produce a large amount of electric current of the comparer consumption of marking signal and take big area according to the result who determines.Thus, best anti-phase logical circuit and the comparer that comprises peanut of data.According to data antiphase circuit of the present invention, each data only needs a logical circuit and a comparer, thinks that each execution of a plurality of data of looking ahead simultaneously is anti-phase/not anti-phase.Thus, data antiphase circuit according to the present invention takies minimum area and can the high speed processing data.

When comparing with comparative example of the present invention, aforesaid effect of the present invention is more apparent.

Figure 12 is the block diagram according to the data antiphase circuit of comparative example of the present invention.With reference to Figure 12, data antiphase circuit 700 comprises first logical circuit 701 to 707, comparer 711 to 717, second logical circuit 721 to 724, selector switch 731 to 733 and phase inverter 741 to 743.

Here, first logical circuit 701, comparer 711 and second logical circuit 721 to 724 are operated in the mode identical with first logical circuit 211 shown in Figure 3, comparer 221 and second logical circuit 231 to 234, therefore omit detailed description.

Data antiphase circuit 700 uses two first logical circuits and two comparers, is used to produce second to the 4th marking signal S2 to S4.For example, require first logical circuit 702 to 703 and comparer 712 and 713 to produce the second marking signal S2.Here, owing to produce third and fourth marking signal S3 and the S4, therefore the process that can be used for producing the second marking signal S2 is described in Figure 12 in the mode identical with producing the second marking signal S2.

First logical circuit 702 receives 8 first input data FDOi_1 and 8 the second input data FDOi_2, determine the anti-phase figure place of corresponding positions of the first input data FDOi_1 and the second input data FDOi_2, and output internal logic signal XOi21 is as determining the result.Comparer 712 receives internal logic signal XOi21, determines whether the number of antiphase is four or more, and has high level or low level noninverting marking signal NP1 according to determined result's output.

In addition, first logical circuit 703 receives by the oppisite phase data of 8 first anti-phase input data FDOi_1 of phase inverter 741 and 8 the second input data FDOi_2, determine the anti-phase figure place of corresponding positions of the anti-phase data and the second input data FDOi_2, and output internal logic signal XOi22 is as the result who determines.Comparer 713 receives internal logic signal XOi22, determines whether the number of antiphase is four or more, and has high level or low level anti-phase marking signal IP1 according to result's output of determining.

Selector switch 731 is selected noninverting marking signal NP1 and the anti-phase marking signal IP1 any one in response to the first marking signal S1 from comparer 711 output, and exports selected signal as the second marking signal S2.In more detail, if the first marking signal S1 is in high level, selector switch 341 is exported anti-phase marking signal IP1 as the second marking signal S2 so, if the first marking signal S1 is in low level, exports noninverting marking signal NP1 so as the second marking signal S2.

As mentioned above, be used to control the anti-phase/noninverting marking signal of the data of current output with generation according to two logical circuits of data antiphase circuit needs of comparative example of the present invention, two comparers and phase inverter.Thus, compare with data antiphase circuit of the present invention, this data antiphase circuit consumes more multiple current and takies bigger area.And, according to data antiphase circuit of the present invention and method, can high speed processing data and the current drain and the area occupied that reduce device.In addition, can prevent that according to data antiphase circuit of the present invention and method the valid window of internal signal from reducing.

Although with reference to its exemplary embodiment detail display with described the present invention, but the present technique field personnel be understood that, below not breaking away from, under the condition of the spirit and scope of the invention that claim limited, can carry out various changes in the form and details.For example, the foregoing description is described based on 4 schemes of looking ahead, and still, the figure place of looking ahead is variable.In addition, in the above-described embodiments, determine whether at per 8 bit data anti-phase, but this also is variable.

Claims (33)

1, a kind of integrated circuit (IC)-components comprises:

Data antiphase circuit, be configured to by carrying out position and the bit comparison between the corresponding positions in the first orderly group and second of data is organized in order, calculate first group and second potential difference between the group in order in order in the data of its input end parallel receive, and the first orderly group and second form of organizing in order that also are configured to produce concurrently data at its output terminal, wherein when data first in order group and data second in order the potential difference number between the form of group greater than second half of the data bits in the group in order of data, second form of organizing in order of data is second anti-phase forms of organizing in order of data, and described data antiphase circuit comprises: be configured to receive the first orderly group of data and the XOR circuit of the second orderly group; Be configured to produce the comparer of the first inner parity signal in response to the signal that produces by described XOR circuit; And be configured in response to the first outside parity signal and the described first inner parity signal and produce the parity signal generator of the second outside parity signal.

2, device as claimed in claim 1, the wherein said first outside parity signal represents whether first form of organizing in order of data is first anti-phase or noninverting forms of organizing in order of data, and the described second outside parity signal represents whether the form of the second orderly group of data is anti-phase or noninverting forms of the second orderly group of data.

3, device as claimed in claim 1, wherein said comparer are configured to produce the inside parity signal of a pair of complementation in response to the signal that is produced by described first XOR circuit.

4, device as claimed in claim 1, wherein said parity signal generator are configured to produce the inside parity signal of a pair of complementation in response to the described first inner basic even signal.

5, device as claimed in claim 3, wherein said parity signal generator is configured to select when the described first outside parity signal is in first logic state first right signal of the inside parity signal of described complementation as the second outside parity signal, and also is configured to select when the described first outside parity signal is in second logic state opposite with described first logic state right secondary signal of the inside parity signal of described complementation as the second outside parity signal.

6, a kind of integrated circuit (IC)-components comprises:

Data antiphase circuit, be configured to by carrying out position and the bit comparison between the corresponding positions in the first orderly group and second of data is organized in order, calculate first group and second potential difference between the group in order in order in the data of input end parallel receive, and also be configured to when data first in order group and data second in order the potential difference number between the form of group greater than second data bits one half in the group in order of data, the first orderly form of organizing in the parallel data of the second anti-phase form of organizing in order of its output terminal generation and data, described data antiphase circuit comprises a plurality of parity signal generators, and whether be configured to produce at least one first form of organizing in order of representing data is the first outside parity signal of the first anti-phase or noninverting form of organizing in order of data.

7, device as claimed in claim 5, wherein said data antiphase circuit comprises at least one delay circuit, be configured to organize and the first delay form of organizing in order of generation data in order in response to first of data, and also be configured to first in order the delay form and the first outside parity signal of group in response to data, produce first form of group in order of data at the output terminal of described data antiphase circuit.

8, device as claimed in claim 6, wherein the delay that provides by at least one delay circuit be used for keeping the rising edge of at least the first outside parity signal and data first in order the delay surplus between the corresponding rising edge of the data of the delay form of group postpone time enough width within the surplus at thresholding.

9, a kind of data antiphase circuit with semiconductor devices of multidigit prefetch architecture, described data antiphase circuit comprises:

A plurality of input data that a plurality of negative circuits, parallel receive and original input data are looked ahead simultaneously, carry out a plurality of input data anti-phase/noninverting, and produce a plurality of output datas,

Wherein said original input data is the output data of exporting during the clock period formerly, each negative circuit of described a plurality of negative circuits receives adjacent two the input data on the output order in the middle of described original input data and the described a plurality of input data, what corresponding positions of determining described two input data are inverting each other, and according to two input data are had the anti-phase definite result of how many corresponding positions carry out to described two import data back one anti-phase/noninverting.

10, data antiphase circuit as claimed in claim 9, each of wherein said original input data and described a plurality of input data comprise I position and output be in proper order a plurality of input data anti-phase by a plurality of negative circuits/noninverting after, order when I the data o pads of a plurality of input data by semiconductor devices outputs to external source, wherein I is the positive integer greater than 1.

11, data antiphase circuit as claimed in claim 10, at least one of wherein said a plurality of negative circuits comprises:

First logical circuit, receive the central original input data of described a plurality of input data and the first input data, define the position of how many described original input datas and the anti-phase result of corresponding positions of the described first input data, and export internal logic signal according to determined result;

Comparer, the output identification signal in response to described internal logic signal; And

Second logical circuit, in response to described marking signal, anti-phase and export the described first input data or the not anti-phase first input data of output first output data as described a plurality of output datas.

12, data antiphase circuit as claimed in claim 11, wherein said internal logic signal comprises the I position, and first logical circuit figure place with the output of first level in the middle of the internal logic signal of I position is identical with the anti-phase figure place of the original input data and the first input data.

13, data antiphase circuit as claimed in claim 12, if wherein half of I position internal logic signal or mostly are positions with first logic level, comparer is with the first logic level output identification signal so, if the I position internal logic signal less than half is the position with first logic level, comparer is exported the marking signal of second logic level opposite with first logic level so; And

If marking signal is in first logic level, second logical circuit anti-phase first is imported data and is exported anti-phase result as first output data so, if and marking signal is in second logic level, the not anti-phase first input data of second logical circuit output are as first output data so.

14, data antiphase circuit as claimed in claim 11, wherein comparer comprises:

The comparison voltage generator circuit produces comparative voltage in response to internal logic signal;

The pedestal generator circuit produces predetermined reference voltage;

Differential amplifier compares comparative voltage and reference voltage, and according to comparative result output identification signal.

15, data antiphase circuit as claimed in claim 11, at least one of wherein said a plurality of negative circuits also comprises delay circuit, described delay circuit receives the first input data, postpone the described first input data schedule time, and the first input data of output delay are to second logical circuit, wherein the schedule time is in first input after data are input to first logical circuit, up to the time that marking signal is spent till the comparer output.

16, as the data antiphase circuit of claim 10, wherein at least one of a plurality of negative circuits also comprises:

First logical circuit, receive J input data and J-1 input data in a plurality of input data, define the position of what J input data and the anti-phase result of corresponding positions of J-1 input data, export internal logic signal according to determined result, wherein J is the positive integer greater than 1;

Comparer is exported internal flag signal in response to described internal logic signal;

The marker generator circuit, in response to the J-1 marking signal, anti-phase and export described internal flag signal or the not anti-phase internal flag signal of output as the J marking signal; And

Second logical circuit, in response to the J marking signal, J input data or the not anti-phase J of output anti-phase and that export in a plurality of output datas import data as the J output data.

17, data antiphase circuit as claimed in claim 16, wherein said internal logic signal comprises the I position, and described first logical circuit figure place with the output of first logic level in the middle of the internal logic signal of I position is identical with the anti-phase figure place of J input data and J-1 input data.

18, data antiphase circuit as claimed in claim 17, wherein, if half of I position internal logic signal or mostly are positions with first logic level, comparer is with the first logic level output identification signal so, if the I position internal logic signal less than half is the position with first logic level, comparer is exported the marking signal with second logic level so

If the J-1 marking signal is in first logic level, so described marker generator is anti-phase and export internal flag signal as the J marking signal, if the J-1 marking signal is in second logic level, so described marker generator is exported not anti-phase internal flag signal as the J marking signal, and

If the J marking signal is in first logic level, so described second logical circuit is anti-phase and export J input data as the J output data, if the J marking signal is in second logic level, the not anti-phase J of so described second logical circuit output imports data as the J output data.

19, data antiphase circuit as claimed in claim 17, wherein said comparer comprises:

The comparison voltage generator circuit produces comparative voltage in response to internal logic signal;

The pedestal generator circuit produces predetermined reference voltage; And

Differential amplifier, with described comparative voltage and described reference voltage compares and export internal flag signal according to relatively result,

If wherein half in the internal logic signal of I position or mostly are positions with first logic level, the level of comparative voltage is higher than the level of reference voltage so.

20, data antiphase circuit as claimed in claim 16, wherein said marker generator comprises:

First phase inverter, anti-phase internal flag signal is also exported anti-phase internal flag signal;

Second phase inverter, anti-phase J marking signal is also exported anti-phase J marking signal;

First switch is switched in response to the J marking signal or ends, and when described first switch conduction, receives anti-phase internal flag signal, and exports anti-phase internal flag signal; And

Second switch is switched in response to anti-phase J marking signal or ends, and receives internal flag signal when described second switch conducting, and the output internal flag signal.

21, data antiphase circuit as claimed in claim 16, wherein at least one of a plurality of negative circuits also comprises: delay circuit, described delay circuit receive J input data, and delay control J imports the data schedule time, and the J of output delay input data are to second logical circuit

The wherein said schedule time is after J input data are input to first logical circuit, up to exporting the time that is spent till the J marking signal from described marker generator.

22, data antiphase circuit as claimed in claim 10, wherein at least one of a plurality of negative circuits also comprises:

First logical circuit, receive J input data and J-1 input data in a plurality of input data, define the position of how many described J input data and the anti-phase result of corresponding positions of J-1 input data, and export internal logic signal according to determined result, wherein J is the positive integer greater than 1;

Comparator circuit is in response to described internal logic signal output internal flag signal and anti-phase internal flag signal;

Selector switch in response to described J-1 marking signal, is selected any one in internal flag signal and the anti-phase internal flag signal, and is exported selected signal as the J marking signal; And

Second logical circuit, in response to the J marking signal, anti-phase and export the not anti-phase J input data of J input data or output as the J output data in a plurality of output datas.

23, data antiphase circuit as claimed in claim 22, wherein internal logic signal comprises the I position, first logical circuit figure place with the output of first logic level in the internal logic signal of I position is identical with the anti-phase figure place of J input data and J-1 input data.

24, data antiphase circuit as claimed in claim 23; If wherein half or more in the internal logic signal of I position are the positions with first logic level; Comparison circuit output has the internal flag signal and the anti-phase internal flag signal with second logic level of the first logic level so; And if be the position with first logic level less than half I position internal logic signal; Output has the internal flag signal and the anti-phase internal flag signal with first logic level of the second logic level so

If the J-1 marking signal is in first logic level, selector switch is exported anti-phase internal flag signal as the J marking signal so, if the J-1 marking signal is in second logic level, selector switch is exported internal flag signal as the J marking signal so, and

If the J marking signal is in first logic level, second logical circuit is anti-phase and export J input data as the J output data so, if the J marking signal is in second logic level, the not anti-phase J of second logical circuit output imports data as the J output data so.

25, data antiphase circuit as claimed in claim 23, wherein comparator circuit comprises:

Comparer is exported internal flag signal in response to internal logic signal; And

Phase inverter, anti-phase internal flag signal is also exported anti-phase internal flag signal,

Wherein said comparer comprises:

The comparison voltage generator circuit produces comparative voltage in response to internal logic signal;

The pedestal generator circuit produces predetermined reference voltage; And

Differential amplifier, with comparative voltage and reference voltage compares and according to comparative result output internal flag signal,

If wherein half of I position internal logic signal or mostly are positions with first logic level, comparative voltage is greater than reference voltage so.

26, data antiphase circuit as claimed in claim 23, wherein said comparator circuit comprises:

The comparison voltage generator circuit produces comparative voltage in response to internal logic signal;

The pedestal generator circuit produces predetermined reference voltage; And

The internal flag signal generator circuit compares comparative voltage and reference voltage, and exports internal flag signal and anti-phase internal flag signal according to result relatively,

If wherein half of I position internal logic signal or mostly are positions with first logic level, the level of comparative voltage is higher than reference voltage so.

27, data antiphase circuit as claimed in claim 26, wherein said internal flag signal generator circuit comprises:

Differential amplifier circuit is activated in response to control signal or forbids, when starting, comparative voltage and reference voltage is compared, and exports first output signal according to result relatively and arrive Section Point to first node and output second output signal;

First output circuit receives from first output signal of first node output in response to control signal, and first output signal that output is received is as internal flag signal; And

Second output circuit receives from second output signal of Section Point output in response to control signal, and second output signal that output is received is as anti-phase internal flag signal.

28, data antiphase circuit as claimed in claim 27, wherein said differential amplifier circuit comprises:

Current source circuit is activated in response to control signal or forbids;

Difference transistor when described current source circuit is activated, change the level of one of first output signal and second output signal in response to comparative voltage and reference voltage, and the result that output is changed is right to first output line;

Amplifier transistor when described current source circuit is activated, amplifies first output line to the first last output signal and second output signal, and exports institute's amplifying signal respectively to second output line right first node and Section Point; And

Reset transistor is switched in response to control signal or ends, when described reset transistor conducting precharge first output line to second output line to the builtin voltage level.

29, data antiphase circuit as claimed in claim 28, wherein said amplifier transistor and described second output line are to cross-couplings.

30, data antiphase circuit as claimed in claim 28, wherein said first output circuit comprises:

First negative circuit is activated in response to control signal or forbids, and when described first negative circuit is activated, and anti-phase and output is from first output signal of first node output; And

First latch cicuit latchs the first anti-phase output signal from first negative circuit output, and anti-phase and output institute latched signal is as internal flag signal,

Wherein said second output circuit comprises:

Second negative circuit is activated in response to control signal or forbids, and when described second negative circuit is activated, and anti-phase and output is from second output signal of Section Point output; And

Second latch cicuit latchs the second anti-phase output signal from second negative circuit output, and anti-phase and output institute latched signal is as anti-phase internal flag signal,

Wherein when described reset transistor conducting, first negative circuit and second negative circuit are under an embargo.

31, data antiphase circuit as claimed in claim 22, wherein said selector switch comprises:

Phase inverter, anti-phase J marking signal is also exported anti-phase J marking signal;

First switch is switched in response to the J marking signal or ends, and receives and export anti-phase internal flag signal when described first switch conduction; And

Second switch is switched in response to anti-phase J marking signal or ends, and receives and the output internal flag signal when described second switch conducting.

32, data antiphase circuit device as claimed in claim 22, wherein at least one of a plurality of negative circuits also comprises: delay circuit, described delay circuit receive J input data, and delay control J imports the data schedule time, and the J of output delay input data are to second logical circuit

Wherein the schedule time is after J input data are input to first logical circuit, up to exporting the time that is spent till the J marking signal from selector switch.

33, a kind of data inversion method of in semiconductor devices, using with multidigit prefetch architecture, this method comprises:

(a) parallel receive and original input data a plurality of input data of looking ahead simultaneously;

(b) determine that how many corresponding positions are central two adjacent on the output order input data of original input data and a plurality of input data have inverting each other, and produce a plurality of marking signals according to the result who determines; And

(c) in response to a plurality of marking signals carry out to a plurality of input data anti-phase/noninverting, and produce a plurality of output datas,

Wherein original input data is the output data of exporting during the clock period formerly.

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