CN1622636A - Single clock cycle length variable entropy decoding device - Google Patents
Single clock cycle length variable entropy decoding device Download PDFInfo
- Publication number
- CN1622636A CN1622636A CN 200410093097 CN200410093097A CN1622636A CN 1622636 A CN1622636 A CN 1622636A CN 200410093097 CN200410093097 CN 200410093097 CN 200410093097 A CN200410093097 A CN 200410093097A CN 1622636 A CN1622636 A CN 1622636A
- Authority
- CN
- China
- Prior art keywords
- shift register
- barrel shape
- output
- shape shift
- length
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
In the single clock period length variable entropy decoder, the externally read code word is first buffer stored in a FIFO buffer memory with output port of whole word width and read signal controlled with the carry signal of the length accumulator; the output of the FIFO buffer memory is fed to and latched in the first stage of barrel shaped shift register, which is shifted under the control of the current decoding sign length accumulating sum and has its shift output fed to the second stage of barrel shaped shift register; the second stage of barrel shaped shift register is shifted with the current decoding sign length; the datan after processing in two stages of barrel shaped shift register are fed vian interconnection bus to the hardware list checking unit and the gate selects one result of work sublist as output. The present invention provides the technology of decoding entropy coding sign in any word length within one clock period and raises the data throughput of decoding system.
Description
Technical field
What the present invention relates to is the interior decoding device of a kind of technical field of image processing, specifically a kind of single clock cycle length variable entropy decoding device.
Background technology
Since Moving Picture Experts Group-1 is formulated, because the outstanding performance performance of MPEG series standard, be acknowledged as the moving image compression standard of comparison success, especially the MPEG-2 international standard of releasing in 1993 becomes the technical standard that the audio/video encoding/decoding field is most widely used in the present consumer electronics especially.The variable entropy decoder is the important composition unit of MPEG series standard, also be according to the unit the highest in the decoder of MPEG series standard design to performance requirement, the method for designing of entropy decoding unit not only has influence on the operational efficiency of mpeg decode system, has directly determined the mpeg decode system to the input data throughput capabilities especially.According to the regulation of Moving Picture Experts Group-2, the flank speed of mpeg decoder can reach 80Mbps, and the variable entropy decoder of therefore low hardware cost and high operational efficiency is the key technology in the efficient mpeg decoder design.General at present employing CPU master control parsing or classification are tabled look-up/the classification pipeline mode, and this dual mode all can't be finished any long symbol and finish decoding in a clock cycle.
Find through literature search prior art, the Chinese patent publication number is 1302512, patent name is: " variable length decoder that the digital coding vision signal is deciphered ", this patent proposes a kind of controlling schemes that adopts the translation instruction cell processing input traffic of novel instruction set, this scheme adopts micro processor, apparatus to finish the variable entropy symbol substitution in inside, this Design of device weak point is: microprocessor control is all adopted in the parsing of input code flow, adopt the rotation/barrel shifter shifts of the annular of knowing clearly simultaneously, the project organization complexity, simultaneously, symbol resolution speed depends on the speed of service of little processing, and treatment effeciency is relatively low.
Summary of the invention
The present invention is directed to the deficiencies in the prior art and defective, a kind of single clock cycle length variable entropy decoding device is provided, it is applied in adopts the MPEG series standard and H.26X in the decoder of series standard, its input adopts first-in first-out (FIFO) buffer to latch the input data, use two-stage barrel shape shift register to cut off the combinational logic chain, directly obtain decoded output signal with the hardware consulting table unit, solved the problem in the background technology by look-up table.
The present invention is achieved by the following technical solutions, the present invention includes: FIFO buffer, two-stage barrel shape shift register, hardware consulting table unit, gate, size latch and length accumulator.Its connected mode is: the code word that reads from the outside is at first sent into buffer memory the FIFO buffer, and the output port of FIFO buffer is wide for whole word (Word), and the degree of depth is according to concrete application choice; The FIFO buffer read signal by length accumulator carry signal controlling.The output of FIFO buffer is sent in the first order barrel shape shift register and is latched, displacement under length accumulator output control, the displacement output signal is sent in the barrel shape shift register of the second level, the displacement of second level barrel shape shift register is exported control by the size latch, deliver to the hardware consulting table unit through the data after the processing of two-stage barrel shape shift register by the intraconnection bus, select a current hardware searching sublist as the work at present table by gate.
Comprise two stage latch and a barrel shifter shifts in each grade barrel shape shift register, two latchs in the first order barrel shifter shifts are cascade structure, are used for the wide data broadening of whole word with the output of FIFO buffer; First latch in the barrel shape shift register of the second level is used to latch the data of first order barrel shape shift register output, its output feedback is sent into second level barrel shape shift register, be used for cutting off critical data path from first order barrel shape shift register, the output that is input as second level barrel shape shift register of second register in the barrel shape shift register of the second level, be used to latch the output of second level barrel shape shift register, the high signal of second level barrel shape shift register as next symbol sent in its output again.The of particular note displacement control signal difference of two-stage barrel shape shift register in this device, the displacement under length accumulator output control of first order barrel shape shift register, second level barrel shape shift register is shifted under the size latch exports control, and the carry signal of length accumulator output is as the enable signal of the latch in two barrel shape shift registers.
The hardware consulting table unit is made up of four groups of hardware lookup table, stored the header table that defines in the coding protocol in first hardware lookup table, stored the AC/DC coefficient table in second hardware lookup table, store the motion vector information table in the 3rd hardware lookup table, stored the macro-block coding pattern table in the 3rd hardware lookup table.Hardware consulting table adopts parallel organization, selects a table as the work at present code table by decoding control signal by gate, sends the actual length that takies of each code word when tabling look-up.Codeword table in the hardware lookup table defines in coding protocol.
The present invention fundamentally solved prior art can't be in a clock cycle to input traffic in word length entropy coding symbol decoding problem arbitrarily, improved the decode system data throughput capabilities.Compare with background technology, the present invention is made up by hardware cell, need not the annex controller and carries out programming Control; What is more important, owing to adopt the devices at full hardware scheme to realize, in lookup unit, do not adopt pipelined architecture, the variable-length encoding symbol that is no more than 24bit of can in a clock cycle, decoding, and multistage flowing water buffer memory has been adopted in the barrel shape shift LD inside in the decoding device, adopt the displacement of two-stage barrel shape, the critical path when circuit is realized is shorter, so the circuit speed of service and data throughout can be very high.
Description of drawings
Fig. 1 structured flowchart of the present invention
Embodiment
As shown in Figure 1, the present invention includes: FIFO buffer 1, two-stage barrel shape shift register 2,3, hardware consulting table unit 4, gate 5, size latch 6 and length accumulator 7.The code word that reads from the outside is at first sent into buffer memory the FIFO buffer 1, the output port of FIFO buffer 1 is wide for whole word, the signal that reads of FIFO buffer 1 is controlled by length accumulator 7 carry signals, the output of FIFO buffer 1 is sent in the first order barrel shape shift register 2 and is latched, displacement under the current decoding symbols length that length accumulator 7 is exported adds up and controls, the displacement output signal is sent in the second level barrel shape shift register 3, the displacement of second level barrel shape shift register 3 is by the decoding symbols length control of size latch's 6 outputs, through two-stage barrel shape shift register 2, data after 3 processing are delivered to hardware consulting table unit 4 by the intraconnection bus.Gate 5 is subjected to the external decoder logic control, selects a hardware searching sublist as current work form according to decoded signal, and the symbol lengths signal of gate 5 outputs is sent in the length accumulator 7 after latching through size latch 6.
Comprise two stage latch and a barrel shifter shifts in each grade barrel shape shift register, two latchs in the first order barrel shifter shifts 2 are cascade structure, are used for the wide data broadening of whole word with 1 output of FIFO buffer; First latch in the second level barrel shape shift register 3 is used to latch the data of first order barrel shape shift register 1 output, its output feedback is sent into second level barrel shape shift register 3, be used for cutting off critical data path from first order barrel shape shift register 2, the output that is input as second level barrel shape shift register 3 of second register in the second level barrel shape shift register 3, be used to latch the output of second level barrel shape shift register 3, the high signal of second level barrel shape shift register 3 as next symbol sent in its output again.
The displacement control signal difference of two-stage barrel shape shift register 2,3, first order barrel shape shift register 2 is subjected to 7 controls of length accumulator, second level barrel shape shift register 3 is subjected to size latch's 6 controls, and the carry signal of length accumulator 7 outputs is as the enable signal of the latch in two barrel shape shift registers 2,3.
Hardware consulting table unit 4 is made up of four groups of hardware lookup table, stored the header table that defines in the coding protocol in first hardware lookup table, stored the AC/DC coefficient table in second hardware lookup table, store the motion vector information table in the 3rd hardware lookup table, stored the macro-block coding pattern table in the 3rd hardware lookup table.Hardware consulting table adopts parallel organization, and decoding control signal selects a table as the work at present code table by gate 5, sends the actual length that takies of each code word when tabling look-up.Codeword table in the hardware lookup table defines in coding protocol.
With the MPEG-2 Video Decoder is operation principle and the process that example illustrates this device, because the maximum symbol lengths at MPEG-2 video entropy coding is 24bit, the input data of therefore each lookup unit should not surpass 24bit, the output code word length of FIFO buffer 1 is decided to be 32bit, the 32bit data of fifo buffer 1 output are sent into first order barrel shifter shifts 2, it is 96Bits that first order barrel shape shift register 2 will be imported the data broadening by the register of two-stage cascade, what 2 pairs of length accumulators of first order barrel shape shift register 7 were exported adds up and is shifted, because the maximal possible length of first order barrel shape shift register 2 can reach 56bit, the output of first order barrel shape shift register 2 should not be less than 56+32bit, therefore the barrel shifter shifts in the barrel shape shift register adopts the displacement of 96bit bit wide in the device, the displacement length of first order barrel shape shift register 2 is unit with 32bit word word always, and integer word 32bit Word displacement always once is shifted.Data bit width position 32bit after the displacement output.Dateout through first order barrel shape shift register 2 is sent into second level barrel shifter shifts 3.3 couples of size latch's 6 of second level barrel shape shift register output displacement, maximum shift length is 24bit, therefore second level barrel shape shift register 3 adopts two 32bit latchs, with the data broadening is 64bit, wherein the 32bit data of first latches input in the second level barrel shape shift register 3 are as the low byte data of barrel shifter shifts, and this register has cut off the data path of first order barrel shape shift register simultaneously.The output that is input as barrel shifter shifts of second level barrel shape shift register 3, data after latching are as the input high byte data of barrel shifter shifts, second level barrel shape is shifted, will take the system in combination logic chain simultaneously into account can not be oversize, on 2 pairs in first order barrel shape shift register adds up and is shifted the basis of exporting, the project organization that second level barrel shifter shifts 3 has adopted array output to latch, carry chain is shorter; Directly drive the interconnected bus from the data of shift register output.Having comprised four hardware lookup table in the hardware consulting table unit 4, is respectively the header table, the AC/DC coefficient table, and motion vector information table and macro-block coding pattern table, all hardware lookup table all are articulated in above the interconnected bus.The external piloting control module can select a look-up table as the work at present form by gate 5 according to decoding control signal, behind look-up table output result, select the result of current look-up table that code-word symbol length is sent among the size latch 6 latchs according to decoding control signal, feed back to second level barrel shape shift register 3 then, if the current work of not decoding is then fed back one 0 value and is given second level barrel shape shift register 3.Length accumulator 7 is sent in another road output of size latch 6.Length accumulator 7 add up and as the displacement control signal of first order barrel shifter shifts 2, the carry signal of length accumulator 7 outputs is as the enable signal of the latch in first order barrel shape shift register 2 and the second level barrel shape shift register 3, and the read signal of fifo buffer 1.All actions under the unified control of the carry signal of length accumulator 7 of the Refresh Data of all data latches in fifo buffer 1 and the device.
Claims (4)
1, a kind of single clock cycle length variable entropy decoding device, comprise: FIFO buffer (1), hardware consulting table unit (4), gate (5), size latch (6) and length accumulator (7), it is characterized in that, also comprise: two-stage barrel shape shift register (2,3), the code word that reads from the outside is at first sent into buffer memory the FIFO buffer (1), the output port of FIFO buffer (1) is wide for whole word, the signal that reads of FIFO buffer (1) is controlled by the carry signal of length accumulator (7) output, the output of FIFO buffer (1) is sent in the first order barrel shape shift register (2) and is latched, displacement under length accumulator (7) control, the displacement output signal is sent in the second level barrel shape shift register (3), the displacement of second level barrel shape shift register (3) is controlled by size latch (6), through two-stage barrel shape shift register (2,3) data after the processing are delivered to hardware consulting table unit (4) by the intraconnection bus, select the result of a work sublist as output by gate 5.
2, single clock cycle length variable entropy decoding device according to claim 1, it is characterized in that, comprise two stage latch and a barrel shifter shifts in each grade barrel shape shift register, two latchs in the first order barrel shifter shifts (2) are cascade structure, are used for the wide data broadening of whole word with FIFO buffer (1) output; First latch in the second level barrel shape shift register (3) is used to latch the data of first order barrel shape shift register (1) output, its output feedback is sent into second level barrel shape shift register (3), be used for cutting off critical data path from first order barrel shape shift register (2), the output that is input as second level barrel shape shift register (3) of second register in the second level barrel shape shift register (3), be used to latch the output of second level barrel shape shift register (3), the high signal of second level barrel shape shift register (3) as next symbol sent in its output again.
3, according to claim 1 or 2 described single clock cycle length variable entropy decoding devices, it is characterized in that, first order barrel shape shift register (2) adds up and controls displacement down the output of the length accumulator (7) of decoding symbols, second level barrel shape shift register (3) displacement under the decoding symbols length control of size latch (6) output, the carry signal of length accumulator (7) output is as the enable signal of the latch in two barrel shape shift registers (2,3).
4, single clock cycle length variable entropy decoding device according to claim 1, it is characterized in that, hardware consulting table unit (4) is made up of four groups of hardware lookup table, stored the header table that defines in the coding protocol in first hardware lookup table, stored the AC/DC coefficient table in second hardware lookup table, stored the motion vector information table in the 3rd hardware lookup table, stored the macro-block coding pattern table in the 3rd hardware lookup table, hardware consulting table adopts parallel organization, select a table as the work at present code table by decoding control signal by gate (5), send the actual length that takies of each code word when tabling look-up, the codeword table in the hardware lookup table defines in coding protocol.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100930971A CN1297150C (en) | 2004-12-16 | 2004-12-16 | Single clock cycle length variable entropy decoding device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100930971A CN1297150C (en) | 2004-12-16 | 2004-12-16 | Single clock cycle length variable entropy decoding device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1622636A true CN1622636A (en) | 2005-06-01 |
| CN1297150C CN1297150C (en) | 2007-01-24 |
Family
ID=34766368
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100930971A Expired - Fee Related CN1297150C (en) | 2004-12-16 | 2004-12-16 | Single clock cycle length variable entropy decoding device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1297150C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100356793C (en) * | 2005-06-09 | 2007-12-19 | 清华大学 | High-speed changeable long code parallel decoder |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0124191B1 (en) * | 1994-01-18 | 1998-10-01 | 배순훈 | Vld |
| JP3450553B2 (en) * | 1995-10-31 | 2003-09-29 | 東芝マイクロエレクトロニクス株式会社 | Variable length code decoding device |
| JP3540248B2 (en) * | 2000-06-01 | 2004-07-07 | 松下電器産業株式会社 | Variable length code decoding device |
| JP2003209474A (en) * | 2002-01-15 | 2003-07-25 | Matsushita Electric Ind Co Ltd | Variable length coding decoding device |
-
2004
- 2004-12-16 CN CNB2004100930971A patent/CN1297150C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100356793C (en) * | 2005-06-09 | 2007-12-19 | 清华大学 | High-speed changeable long code parallel decoder |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1297150C (en) | 2007-01-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6819271B2 (en) | Parallel compression and decompression system and method having multiple parallel compression and decompression engines | |
| CN1039469C (en) | high speed variable length code decoding apparatus | |
| CN101790889B (en) | Architecture for multi-stage decoding of a cabac bitstream | |
| US20030058873A1 (en) | Network device with improved storage density and access speed using compression techniques | |
| CN102113220A (en) | Low power deserializer and demultiplexing method | |
| US5663726A (en) | High speed variable-length decoder arrangement with reduced memory requirements for tag stream buffering | |
| JP2004507858A (en) | Hardware implementation of compression algorithms. | |
| US6865668B1 (en) | Variable-length, high-speed asynchronous decoder circuit | |
| CN108965878B (en) | A kind of entropy decoding method and device | |
| US7504970B2 (en) | Data encoder | |
| CN1297150C (en) | Single clock cycle length variable entropy decoding device | |
| CN100433560C (en) | Programmable variable length decoder including interface of cpu processor | |
| JPH11501488A (en) | Variable length decoder | |
| US5432512A (en) | Apparatus for decoding variable length codes | |
| CN103428502B (en) | Decoding method and decoding system | |
| CN1129883A (en) | High speed variable length decoder | |
| CN111865330B (en) | High-speed parallel-serial conversion circuit suitable for JESD204B protocol standard | |
| CN101267559A (en) | Universal entropy decoding method and device for video decoder | |
| Higgie et al. | Efficient encoding and decoding algorithms for variable-length entropy codes | |
| Chen et al. | A low cost context adaptive arithmetic coder for H. 264/MPEG-4 AVC video coding | |
| Shimura et al. | C4: An FPGA-based compression algorithm for expether | |
| Lee et al. | A memory-based architecture for very-high-throughput variable length codec design | |
| KR100283088B1 (en) | Asynchronous variable length decoder | |
| Tian et al. | Review of Existing Statistical Codec Designs | |
| Hong et al. | A 360Mbin/s CABAC decoder for H. 264/AVC level 5.1 applications |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070124 Termination date: 20111216 |