CN1611045A - Error correction method and apparatus for data transmission system - Google Patents
Error correction method and apparatus for data transmission system Download PDFInfo
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- CN1611045A CN1611045A CN 02826527 CN02826527A CN1611045A CN 1611045 A CN1611045 A CN 1611045A CN 02826527 CN02826527 CN 02826527 CN 02826527 A CN02826527 A CN 02826527A CN 1611045 A CN1611045 A CN 1611045A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/0062—Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
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- Dc Digital Transmission (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
A receiver involved in high-speed data transmission includes a decision system. The decision system calculates a value of an input signal and holds the value as a tentative value. The decision system calculates an error value, amplifies the error value, and holds the amplified error value as a corrected value. If the amplified error values is within a marginal range and the input signal was in transition from a positive to negative state, or a negative to positive state, then the decision system overrides the tentative value with the corrected value.
Description
Technical field
The present invention relates generally to high speed data transfer.More specifically, the present invention relates in transmission system, proofread and correct jitter spectrum, this transmission system strict jitter toleration on the chattering frequency of wide region.Such as the input signal of 1.544Mbit/s digital circuit (T1) system of point-to-point special use, it is owing to several T1 link cascade in the network has bigger shake.
Background technology
In recent years, network application is very general, especially in response to the network application of using in the big array computation environment and the explosive growth of multiplicity of network.Therefore, in correlation technique, obtained the performance that many progress improve these network systems.For example, being used for the fully-integrated transceiver of T1 network channel service unit (CSUs) and the PRI application of integrated services digital network (ISDN) is that know and commercial now in the art.These devices, such as Intel LXT360 T1/E1 transceiver, useful in the network applications such as (timing recovery) of clock recovery in such as the T1 network system., exist some obstacles to stop this kind system that better jitter toleration is provided, and jitter toleration is a desired performance in communication network and other network applications.This obstacle may comprise very big amplitude jitter, the packing density of wide variation, a large amount of cable attenuations and bad harmony.
Shake is the probabilistic generic term that is used for describing in noise in the communication system or the input cycle data.In idealized system, data bit is in incremental time (timeincrements) arrival constantly, and this incremental time is the integral multiple that data bit repeats (bit repetition) time constantly., in real system, data pulse arrived in the moment of departing from these integral multiples time.This deviation may cause the error in the transfer of data, particularly when data during with high-speed transfer.This deviation or variation may be in amplitude, frequency or the phase places of data.Shake may be owing to following former thereby generation, comprising the imperfection of the difference on the frequency between intersymbol interference, transmitter and receiver clock, noise and Receiver And Transmitter clock forming circuit.
In digital communication system, shake is an important problem very.At first, shake causes in non-optimum sampling point up-sampling received signal, and this has caused the signal to noise ratio of receiver to reduce and has therefore limited information rate.Secondly, in legacy system, each receiver generally extracts it and receives sampling clock from input data signal.And shake makes this task very difficult.The 3rd, in long haul transmission system, a plurality of regenerators are arranged on its link, shake can accumulation.That is to say that each receiver extracts clock from the input data bit flow, the recovered clock of timing data, and use once more sends data once more.Thereby each follow-up receiver can be seen the gradually big input jiffer of degree.
When input signal comprised big high dither composition, receiver phase-locked loop (RPLL) often lost the ability of accurate tracking input signal phase motion.When this kind RPLL imbalance becomes symbol period greater than some, will produce error in label.This kind phase detuning can be thought the phase error from the recovered clock phase place of phase of input signals.Clock margin (timing margin) is defined as the maximum phase error that occurs when not causing error in label.
Fig. 1 shows relevant data and judges the scheme of tolerance limit constantly.
Fig. 1 is the stack of the possible signal trajectory of two code-element periods in personal attendant's machine data sequence, is called eye pattern.The clock margin shown in Fig. 1 be from time T 1 to time T3, wherein T2 be optimal judgement constantly.If phase error causes data decision to occur in before the time T 1 or after the time T 3, data decision may make a mistake so.Under this kind situation, because intersymbol interference, receiver begins to produce error.Usually, when this kind situation occurs in phase error and surpasses 40% symbol period, i.e. the right of the left side of time T 1 and T3 in Fig. 1.
Thereby, need one and can carry out method of its error calibration and device, even its permission also can be carried out the correction of error in label when phase error surpasses 40% symbol period.Also need the method for its error calibration and the device of the easy realization of a kind of energy to reduce owing to pattern is shaken the error rate of bringing.
Description of drawings
Fig. 1 shows a time domain eye pattern, and this eye pattern has the signal trajectory of two symbol periods in personal attendant's machine data sequence that prior art knows;
Fig. 2 shows according to one embodiment of present invention, a time domain eye pattern when phase error surpasses 40%;
Fig. 3 shows the block diagram of receiver according to an embodiment of the invention;
Fig. 4 shows total block diagram of a decision subsystem according to an embodiment of the invention;
Fig. 5 shows the concrete block diagram of a decision subsystem according to an embodiment of the invention; With
Fig. 6 shows the flow chart of a decision operation according to an embodiment of the invention.
Detailed Description Of The Invention
Fig. 2 shows a time domain eye pattern when phase error surpasses 40% according to an embodiment of the invention.Point 102 is points that error in label occurs when data from-1 to 1 change (transition); Point 204 is points that error in label occurs when data from 1 to-1 change; Point 102 and 204 can both be discerned the position of 40% (being the left side of center phase place in this example) of the about symbol period of its phase deviation T2.For example, when data decision constantly should be at T2 (t=1.0) and therefore is encoded as a+1 and but is substituted in T1 (t=0.6) judgement,, produce error event thus because its amplitude is lower than 0.5 and be a0 with digital coding when T1.Point 204 is identical with the phase place of putting 102 place's signals but polarity is opposite.
In Fig. 2, can see another example of the error event that the present invention can overcome.When data from 1 to-1 change, put the place that 306 is-symbol errors produce; And when data from-1 to 1 change, put the place that 408 is-symbol errors produce; Point 306 and 408 can both be identified in 40% position of the about symbol period of its phase deviation T2 on center phase place the right.Therefore when the data decision moment should also be that a+1 but is substituted in T3 (t=1.4) sampling with digital coding at T2 (t=0), and is to be worth 0 o'clock with digital coding thus, has just produced error event.Point 408 is identical with the phase place of putting 306 place's signals but polarity is opposite.
In the example that above-mentioned four examples and most of error occur, described sampled value has and approximates 0.5 range value greatly.Usually, when phase error was very little, described sampled value just approached 1,0 or-1.Therefore, sampled value 0.5 illustrates a kind of tolerance limit situation, and means and phase error may occur.The present invention utilizes these information not to be inconsistent as first finger that is used to indicate phase error to occur.
The present invention can also confirm that data variation takes place.The present invention can sample from the numerical value of adjacent moment, and sampled value is estimated, changes with check occurent data value in symbol period.In Fig. 2, suppose to be spaced apart half of described symbol period between the described adjacent sampling phase, shown in sampling S1 10 and S2 12.S1 10 is relevant with point 102 with S2 12, and wherein tentation data changes from a-1 to a+1.If S1 10 and S2 12 values approach on the contrary, for example be-1 or 1 in this example, so just can confirm that data change from a-1 to a+1.Usually, the present invention utilizes such fact, promptly when judgement phase place (wherein carrying out data decision) is changed in two adjacent sampling phases one or another (such as, T2 is changed to T1 or T3), great majority are owing to the just generation of mistaken verdict that sampling phase error produces occurs.This kind situation is exactly to be used to second designator of indicating phase error to take place.Therefore, when both of these case all satisfies, that is to say and find that data value is tolerance limit and changes that data value just has been corrected so within symbol period.
Fig. 3 shows the block diagram of receiver 20 according to an embodiment of the invention.Receiver 20 receives input traffic and extract data and phase information from input traffic.Input traffic is imported into band limit low pass filter (LPF) 21, and its output is imported into amplifier 22, uses automatic gain control (AGC) should export amplification on amplifier 22.By the output of using mould/number (A/D) converter 24 to come sampling amplifier 22.
Then digital signal is input to equalizer (EQL) 25.The digital signal of equalizer 25 outputs is transfused to into phase discriminator 26, extracts phase information in phase discriminator 26.The sampled digital output signal of equalizer 25 also is transfused to into decision system 30, determines the numerical value of balanced sampled signal in decision system 30.The phase information that phase discriminator 26 produces is by loop filter 27 filtering and be fed to oscillator 28 and come control generator phase place and frequency.The clock signal that oscillator 28 produces is as the input signal sampling clock of A/D converter 24.
Fig. 4 shows decision system 30 according to an embodiment of the invention.Decision subsystem 30 comprises 36, one change detection module 38 of 34, one error estimator module of 32, one error estimator module of an initial decision circuit, and an error correction module 40.The sampled digital signal of equalizer 25 outputs is transfused to into decision circuit 32, determines the numerical value of sampled digital output in decision circuit 32.Do not change numerical value if error correction module 40 activates, the output valve of decision circuit is exactly the value of decision subsystem 30 outputs so.
The value data of decision circuit 32 outputs is imported into error estimator module 34.Error estimator module 34 deducts from the data value that is input to decision circuit 32 from the data value of decision circuit 32 outputs.Then, the output of error estimator module 34 is amplified to 1 or-1 error amount that is corrected with representative, if error takes place and error correction module 40 is activated the error amount that so just uses this to be corrected.Such as, if error estimator module output is .3, output is amplified to 1 so.If error estimator module output is-.2 to export the result so and be amplified to-1.
The output of error estimator is transfused to into error estimator module 36, and whether error estimator module 36 decision signal values are in specified scope.The output of error estimator module is transfused to into error correction module 40.If realize signal value in specified scope, the output of error estimator module is depicted as high level signal so.
Be transfused to into change detection module 38 from the sampled digital output of equalizer 25 outputs.The neighbouring sample of numeral output is used by change detection module 38.Such as, adjacent phase samples is half symbols periodic sampling before judgement sampling constantly and afterwards, shown in Fig. 2 mid point S110 and S212.Whether change detection module 38 can approach normal value by the valuation adjacent phase samples is judged that as-1 and 1 inverse value whether complete data takes place changes (from value a-1 to value a+1 or from value a+1 to value a-1).The output of change detection module 38 also is transfused to error correction module 40.If change detection module 38 is judged a numerical value change takes place in symbol period, the output of change detection module 38 will be depicted as height so.
For example, if the output of change detection module 38 and error estimator module 36 all is high, error corrector 40 will send instruction and select corrected value but not nonce (tentativevalue) so.
Another embodiment of the present invention as shown in Figure 5, the sampled digital of equalizer 25 output is transfused to into decision circuit 32, decision circuit 32 is determined its numerical value.In the present embodiment, decision circuit 32 determines whether this output valve is-1,0 or 1.The output of decision circuit 32 is looked at as the nonce of data, and this value is not only used when error correction module 40 is activated.
The sampled digital output of equalizer 25 is input to error estimator module 34 with the output valve of decision circuit.The value of error estimator module 34 usefulness decision circuits output deducts the output valve of equalizer 25, calculates error signal.The output valve of error estimator module sends by signed boolean (SGN) circuit 50, signed boolean (SGN) circuit 50 with all negative values be amplified to-1 and with all on the occasion of be amplified to+1.For example, the value a-2 from error estimator module 34 is amplified to-1 by SGN circuit 50.This numerical value is corrected error value.
Whether the output valve of error estimator module also is transfused to into error estimator module 36 (see figure 4)s,, know in this specified scope and may have error within specified scope with decision numerical value.One by input data-1,0, in+1 data flow of forming, value 0.5 or-0.5 can not indicate whether its value is-1,0 or 1, thereby these values (+0.5 and-0.5) are considered to tolerance value.In one embodiment of the invention, error estimator module 36 is made up of an absolute value (ABS) circuit 51 and a comparator 53.
The output valve of error estimator module is input to ABS circuit 51, and it makes the error estimator module output valve all become absolute value under all conditions.The output valve of ABS circuit 51 is imported into comparator 53, and input value and reference value compare in comparator 53, and reference value is 0.4 in this example.In the present example, because comparator 53 is sought 0.5 the value of approximating from error estimator 34 outputs, so the output valve of ABS circuit 51 is compared with value 0.4.If the output valve of ABS circuit 51 is greater than 0.4, the output valve of comparator 53 is depicted as height so.With the output token of comparator 53 is SIGNAL_A.If SIGNAL_A is high, numerical value just is determined and is in marginal range so.SIGN_A is input into error correction module 40.
Change inspection side form piece 38 and confirm whether to have taken place numerical value change.In one embodiment of the invention, change detection module 38 comprises 60, one absolute values of an adder circuit (ABS) circuit 61 and a comparator 63.From equalizer 25, take in the input signal two test samplings away, wherein in Fig. 2 before the T1 half signal period take first sampling away, such as S110; Take second sampling away with the half symbols cycle after T1, such as S212.
The numerical value of sampling S110 and S212 is transfused to into adder circuit 60, deducts the numerical value of taking away before the T1 the numerical value that adder circuit 60 is taken away after T1.The output of adder circuit 60 is transfused to into ABS circuit 61, and ABS circuit 61 under any circumstance all becomes the result into absolute value.The output of ABS circuit 61 is input into comparator 63, and compares with reference value, reference value is 1.5 in example.Because this will indicate the data value of sampling SI 10 and S2 12 to approach normal value as 1 ,-1, so comparator 63 use values 1.5.Comparator 63 generates an output, and this output is marked as SIGNAL_B.If 61 outputs of ABS circuit are greater than 1.5, SIGNAL_B just is high so; If output is less than 1.5, SIGNAL_B is low just so.If two adjacent phase samples approach normal value as+1 or-1, so just can confirm the data variation in symbol period.And SIGNAL_B is outputted as height.SIGNAL_B is imported into error correction module 40.
If SIGNAL_A and SIGNAL_B are depicted as height, correction module 40 sends instruction and selects corrected value so, and this corrected value is exported (see figure 4) from error estimator module 34.Thereby from the data replacement nonce of error correction module 40 inputs, nonce is initially to be provided by decision circuit 32.
Fig. 6 shows the flow chart of a decision operation according to an embodiment of the invention.Decision circuit 32 calculates the value of input signal, and this value is remained nonce 70.Error estimator module 34 error of calculation values are amplified this error amount and this amplified error value are remained corrected value 72.Error estimator module 36 judges whether this amplified error value is in marginal range interior 74.Change detection module 38 determine input signals whether be in the symbol period from just to negative variation, perhaps from negative to positive variation 76.If amplified error value is in marginal range, and input signal is in the variation, error correction module 40 replaces nonces and uses corrected value 78 so.When in sampled signal is handled, be used in combination analog/digital converter and digital signal processor (DSP) when realizing transceiver, the present invention is even more important.Digital signal processor (DSP) method can be brought up to the quaternary or octal system structure with having long range simulation TI transceiver implementation now in essence, avoids crosstalking of interchannel in the silicon wafer.
The invention provides and be used for method of its error calibration and system in a kind of high speed data transmission system, shake or phase error can cause intersymbol crosstalking in high speed data transmission system.A receiver comprises a decision system.This decision system is determined the nonce of sampled input signal.This decision system calculates error amount, with its amplification and it as error correction value.Whether decision system determines this error amount in marginal range, and whether definite sampled input signal is in the conversion in a symbol period.If these situations occur simultaneously, decision system just abandons nonce so, and selects corrected value.
From the top relevant description of specific embodiments of the invention, be understandable that and under the situation of not leaving its spirit, carry out many modifications.The accessory claim book often will cover this kind modification, makes it in actual range of the present invention and spirit.Therefore, present disclosed embodiment is considered to example in every respect, is not limited to this.Scope of the present invention is indicated by the appended claims, rather than above-mentioned specification.And changing in the implication of the peer-to-peer of claims and the institute in the scope, often all is welcome.
Claims (21)
1, method of its error calibration in a kind of high speed data transmission system comprises:
Determine the value of the input signal on time decision frame (timeframe) and this value is remained nonce;
The valuation error amount amplifies this error amount and described amplified error value is remained corrected value;
Judge that described amplified error value is whether in the marginal range of regulation;
Determine whether described input signal relates to (involve) from just to the variation of negative state or the variation from negative to positive status in the signal period; And
If described error amount also relates to variation in described accepted tolerance scope and described signal, just described nonce being proofreaied and correct is described corrected value.
2, method of its error calibration in the high speed data transmission system as claimed in claim 1, wherein whether described two consecutive values of the described input signal of calculating before or after described time decision frame relate in the variation with definite described input signal.
3, method of its error calibration in the high speed data transmission system as claimed in claim 2, wherein described two consecutive values of half symbols computation of Period before or after described time decision frame.
4, method of its error calibration in the high speed data transmission system as claimed in claim 3, wherein said two consecutive values relate to one from less than-0.75 to greater than+0.75 variation or from greater than+0.75 to less than-0.75 variation.
5, method of its error calibration in the high speed data transmission system as claimed in claim 3, wherein said two consecutive values relate to from-1 to+1 or from+1 to-1 variation.
6, the decision system in a kind of high speed data transfer comprises:
A data decision circuit is used for determining that judgement input signal values constantly also remains nonce with this value;
An error estimator module is used for determining error amount, amplifies this error amount and described amplified error value is remained corrected value;
An error estimator module is used for determining that described amplified error value is whether in marginal range;
A change detection module, be used for determining described input signal whether be in the symbol period from just to negative state or from bearing to the variation of positive status; And
An error correction module is used for determining whether described nonce is replaced by described corrected value.
7, decision system as claimed in claim 6, wherein said error estimator module comprise one be used for making described error amount become on the occasion of absolute value circuit and one be used for comparator that described error amount and reference value are compared.
8, decision system as claimed in claim 6, wherein before described judgement constantly and the neighbouring sample value of described input signal afterwards be used for determining whether described input signal is in the variation.
9, decision system as claimed in claim 8, the wherein described neighbouring sample value of half symbols computation of Period before or after described judgement constantly.
10, decision system as claimed in claim 8, wherein said change detection module comprises an adder that is used for the described neighbouring sample value of addition, and one is used to make described neighbouring sample value after the addition is that positive absolute value circuit and one are with the described sampled value after the addition and the comparator that reference value compares.
11, a kind of making in high speed data transfer is used for the receiver of output data value, comprising:
An analog/digital converter is used for receiving inputted signal and export a sampled digital signal and a phase information;
A decision system is used to receive described sampled digital signal and exports value, wherein a decision system from receiver:
Receive described sampled digital signal,, and distribute nonce at judgement moment evaluation;
Error of calculation value is amplified this error amount and this amplified error value is remained corrected value;
Determine that described error amount is whether in marginal range;
Determine described input signal in a symbol period, whether be in from just to negative state or from negative to the variation of positive status; And
If if described error amount in marginal range and described input signal be in the variation in the symbol period, described corrected value is exported as described numerical value;
A phase discriminator is used for receiving the phase information after described numerical value and described phase information and output detect;
A loop filter is used to receive the phase information after the described detection, and exports filtered phase information; And
An oscillator is used to receive described filtered phase information, and with the sampling clock output of clock signal as analog/digital converter.
12, receiver as claimed in claim 11, wherein before described judgement constantly and the neighbouring sample value of described input signal afterwards be used to determine whether described sampled digital signal is in the variation.
13, receiver as claimed in claim 12, the wherein described neighbouring sample value of half symbols computation of Period before described judgement constantly and afterwards.
14, receiver as claimed in claim 11, wherein said decision system comprises:
A data decision circuit is used for receiving described sampled digital signal, at judgement moment evaluation and the described nonce of distribution;
An error estimator module is used for error of calculation value, amplifies described error amount and described amplified error value is kept as described corrected value;
An error estimator module is used for determining that described error amount is whether in marginal range;
A change detection module, be used for determining described sampled digital signal whether be in the symbol period from just to the variation of negative state or from negative to the variation of positive status; And
An error correction module, if be used for described error amount in marginal range and described sampled digital signal relate to variation, described corrected value is exported as described numerical value.
15, receiver as claimed in claim 14, wherein error estimator module comprises one to be used for making described error amount is positive absolute value circuit; And one be used for comparator that described error amount and reference value are compared.
16, receiver as claimed in claim 14, wherein said change detection module comprise an adder that is used for the described neighbouring sample value of addition, and one is used for making the neighbouring sample value of described addition is positive absolute value circuit; And comparator that consecutive value and the reference value that is used for described addition compares.
17, system receiver as claimed in claim 11 wherein receives described input signal from the T1 data transmission system.
18, system receiver as claimed in claim 17, wherein said T1 data transmission system comprise a plurality of cascade T1 links.
19, a kind of decision circuit comprises:
A machine readable storage media; And
Machine readable program code, it is stored in the described machine readable storage media,
Described machine readable program code has instruction and comes
Constantly calculate the value of input signal and described numerical value is kept as nonce in judgement;
Error of calculation value is amplified described error amount, and described amplified error value is kept as corrected value,
Determine that described error amount is whether in marginal range;
Determine described input signal whether be in the symbol period from just to the variation of negative state or from negative to the variation of positive status, and
Whether adjudicate described nonce should be replaced by described corrected value.
20, decision circuit as claimed in claim 19, wherein before described judgement constantly and the neighbouring sample value of described input signal afterwards be used for determining whether described input signal is in the variation.
21, decision circuit as claimed in claim 20, wherein before described judgement constantly and half period afterwards calculate the neighbouring sample value of described input signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US171201A | 2001-10-31 | 2001-10-31 | |
| US10/001,712 | 2001-10-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1611045A true CN1611045A (en) | 2005-04-27 |
| CN100525270C CN100525270C (en) | 2009-08-05 |
Family
ID=21697445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB028265270A Expired - Fee Related CN100525270C (en) | 2001-10-31 | 2002-10-30 | Error correction method and apparatus for data transmission system |
Country Status (3)
| Country | Link |
|---|---|
| CN (1) | CN100525270C (en) |
| AU (1) | AU2002363157A1 (en) |
| WO (1) | WO2003039090A2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769587A (en) * | 2012-07-09 | 2012-11-07 | 广东威创视讯科技股份有限公司 | Method and devices for enhancing PCI-E (Peripheral Component Interconnect - Express) data transmission stability |
| CN105897629A (en) * | 2016-06-15 | 2016-08-24 | 晶晨半导体(上海)有限公司 | Signal decision device and signal decision method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3760282A (en) * | 1972-03-29 | 1973-09-18 | Ibm | Data recovery system |
| WO1988005235A1 (en) * | 1987-01-12 | 1988-07-14 | Fujitsu Limited | Discrimination timing control circuit |
| EP0594246B1 (en) * | 1992-10-22 | 1998-03-04 | Koninklijke Philips Electronics N.V. | Data processing circuit |
| US5436589A (en) * | 1994-01-31 | 1995-07-25 | Motorola, Inc. | Demodulator for frequency shift keyed signals |
-
2002
- 2002-10-30 CN CNB028265270A patent/CN100525270C/en not_active Expired - Fee Related
- 2002-10-30 WO PCT/US2002/034961 patent/WO2003039090A2/en not_active Application Discontinuation
- 2002-10-30 AU AU2002363157A patent/AU2002363157A1/en not_active Abandoned
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769587A (en) * | 2012-07-09 | 2012-11-07 | 广东威创视讯科技股份有限公司 | Method and devices for enhancing PCI-E (Peripheral Component Interconnect - Express) data transmission stability |
| CN105897629A (en) * | 2016-06-15 | 2016-08-24 | 晶晨半导体(上海)有限公司 | Signal decision device and signal decision method |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2003039090A2 (en) | 2003-05-08 |
| AU2002363157A1 (en) | 2003-05-12 |
| CN100525270C (en) | 2009-08-05 |
| WO2003039090A3 (en) | 2003-07-10 |
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