CN1611030A - Timing recovery with variable bandwidth phase locked loop and non-linear control paths - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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Abstract
A timing recovery system includes a phase locked loop with a variable bandwidth loop filter, several data dependent gain units, and three proportional paths with non-linear control. The system provides excellent jitter tolerance with a wide variation in data density and large amplitude jitter with a wide frequency range. The gain of both an included loop filter and a phase detector may be varied with both frequency and data density. Direct, unfiltered adjustments may be made to phase based on the sign of the first differential of an accumulator output during long strings of zeros to help maintain tracking even with a very low data density.
Description
Technical field
Present invention relates in general to solve wide variation, the shake significantly in the big frequency range and the communication system of imperfection equilibrium, for example the T1 network of packing density.More specifically, the present invention relates to a kind of timing recovery system, it comprises linear phase-locked loop (" PLL ") with bandwidth varying loop filter and three ratio paths with nonlinear Control.
Background technology
Flourish along with the purposes of the network that is utilized in the large-scale calculations environment and variation, it is very general that network application has in recent years become.Correspondingly, in order to improve the quality of these network systems, a lot of progress in correlation technique, have been obtained.For example, the fully-integrated transceiver and the application of Integrated Service Digital Network primary rate interface that are used for T1 CSU (CSU) have been well known in the art, and at present commercial available.These equipment are very useful for the network application that the timing in the T1 network system for example recovers such.But, exist the obstacle that hinders this system that better jitter toleration and desirable quality are provided in communication network and other network application.These obstacles comprise the wide variation of king-sized amplitude jitter, packing density, a large amount of cable attenuation and incomplete equilibriums.
Shake is to be used for being described in communication system departs from its distortion that causes with reference to the variation of timing position owing to signal generic term.In idealized system, bit arrives when the incremental time of the integer multiple that equals the bit repetition time.But in the system of reality, the time that data pulse arrives has been departed from these integer multiples.This departing from may cause occurring in the transfer of data mistake, and be particularly all the more so when with high speed transmission data.This variation that departs from or change amplitude, time, frequency or the phase place that may be data.The generation of shake may come from multiple reason, comprises difference on the frequency, noise between intersymbol interference, reflector and the receiver clock, and the non-ideal characteristic of receiver and reflector clock generating circuit.
Because following several reasons, shake is the problem of particular importance in digital communication system.At first, shake causes sampling to the received signal at non-optimum sampling point.The signal to noise ratio that this problem can reduce receiver takes place, thereby has limited information rate.The second, in the system of reality, each receiver all must extract its reception sampling clock from input data signal.Shake makes this task become more difficult.The 3rd, in having used the distance transmission system that is present in a plurality of transponders in the link, shake will be accumulated.
Usually measure jitter amplitude with unit gap (" UI "), wherein 1UI equals the one-period of bit repetition time.For example, in the T1 network, 1UI equals 648 microseconds, and in the E1 network, 1UI equals 488 microseconds.The normal range (NR) of shake may alter a great deal according to application-specific.For the T1 system, be restricted to for the chattering frequency input jiffer between 10Hz and the 40KHz usually and be approximately the 5UI peak-to-peak value, and for the chattering frequency between 8KHz and the 40KHz, input jiffer will be restricted to the 0.1UI peak-to-peak value.But, the T1 receiver usually must can allow between 10KHz and 100KHz for amplitude up to 0.4UI, and big to the such sinusoidal jitter of 28UI when 300Hz so that realization network interoperability.
Therefore, need a kind of timing recovery system that improved jitter toleration can be provided, particularly for those wide variation in must management data density and the system of shake significantly in the big frequency range.
Description of drawings
Figure 1A and 1B illustrate the calcspar according to the DPLL digital phase-locked loop with three non-linear ratio's paths of the embodiment of the invention;
Fig. 2 illustrates the calcspar according to first non-linear ratio's path of the embodiment of the invention;
Fig. 3 illustrates an eye pattern, has described the operation of non-linear ratio's path of Fig. 2;
Fig. 4 illustrates the calcspar according to second non-linear ratio's path of the embodiment of the invention;
Fig. 5 illustrates the flow chart according to the machine readable program sign indicating number of the embodiment of the invention;
Fig. 6 illustrates the acceptor circuit according to the embodiment of the invention.
Embodiment describes
In one embodiment of this invention, provide a kind of timing recovery system.This system comprises that one has PLL, several data dependent gain units and three ratio paths with nonlinear Control of bandwidth varying loop filter.Even exist under the situation of shaking significantly in the packing density wide variation and in the wide range of frequencies scope, system also can provide improved jitter toleration.The included loop filter and the gain of phase detectors can be along with frequency and packing densities and are changed.Can come phase place is carried out direct, unfiltered adjusting according to received data pattern and phase error amplitude, to reduce the loop stand-by period and to make the instantaneous and quick raising of loop gain of PLL.Also can phase place be carried out direct, unfiltered adjusting, thereby help under the situation of timely low-down packing density, also can keep following the tracks of according to the symbol of first differential term of accumulator during long zero string output.
In another embodiment of the present invention, provide a kind of method of improving the jitter toleration in the communication network.A kind of communication network with three non-linear paths and a PLL is provided.Data are input to this communication network.According to from the data sampling at the center of the data eye (data eye) of input data with from the phase sample in the input data of half-wave after the special time, evaluation phase error.Then this phase error is associated with the recovered data symbol.Phase error after then this being associated multiply by a gain.Thereby utilize loop filter that this is multiplied each other and be associated after phase error filter and produce an output.This output and output from non-linear paths are produced an accumulative total output mutually.At last, should add up output and be converted to clock phase information.
System preferably realizes PLL, and this PLL can be the PLL of any suitable order.For example, second order PLL can be used for a plurality of embodiment of the present invention.PLL is a kind of feedback control system, is used to lock the phase of a local clock to phase of input signals.PLL generally includes phase detectors, and the difference between the output phase of the output of these phase detectors and input phase and included voltage controlled oscillator (" VCO ") or numerically-controlled oscillator (" DCO ") is proportional; One loop filter, the output of this loop filter be entered as ratio but have the frequency characteristic of some hope; And VCO or DCO, its output phase and the input voltage behind the integration are proportional.
The element of PLL can be embodied as the analog or digital circuit.In operation, the phase detectors error of calculation (that is, between input and the local phase place poor) is utilized loop filphase locking that error is filtered then and is provided it to VCO, and this VCO correspondingly changes the output phase of himself.Because comprehensive degenerative cause, thus PLL to trend towards error signal drives be zero, thereby force the output phase of VCO to equal input phase.
The order of PLL depends on the number of times of wherein included integration operation.VCO or DCO provide an integration.Therefore, the PLL that does not comprise integrator in loop filter has an order.The second order PLL that may comprise in the embodiment of the invention comprises an integrator in loop filter.
PLL can provide good jitter toleration for a lot of the application.But some is used, and for example the timing in the T1 system recovers and need can provide good jitter toleration when very significantly shaking in existence, and this is shaken significantly may be at 300Hz in the frequency range of 100KHz.In addition, these systems must be able to solve the wide variation in the packing density, a large amount of cable attenuations and incomplete equilibrium.The combination of these obstacles makes the design that regularly recovers PLL become very difficult.The another kind of obstacle that in based on the system of digital signal processor techniques, also exists, i.e. sampling all the time and the stand-by period between the output that regularly recovers may be very big.
For system with these obstacles, can improve the performance of regularly recovering by increase a plurality of non-linear ratio's paths for PLL, these non-linear ratio's paths are also referred to as speed changer.Preferred timing recovery system 100 shown in Figure 1 comprises three such paths 1,2 and 3.This system comprises data density detector 4, and it monitors packing density and linear adjustment gain 102 and the phase detector gain 9 that receives, thereby keeps constant gain and bandwidth when packing density changes.This system also comprises a frequency detector 5, and this frequency detector 5 detects the frequency of incoming timing shake and the bandwidth of regulating PLL, thereby maximizes jitter toleration in wider frequency.
With reference to Fig. 3 this operation is described, Fig. 3 illustrates an eye pattern.Those skilled in the art should know that eye pattern is usually as the method for the signal to noise ratio of the random signal that is used for estimating communication system.Eye pattern is by when the track that sends random data and all are received overlaps each other, and with fixed clock (usually and tranmitting data register synchronous) desired signal being sampled produces.People can estimate the possibility that occurs mistake in bit decision (bit decision) by observing this eye pattern.
For example, as shown in Figure 3, when timing recovery system proper operation of the present invention, sampled point 304 is just in time at the center of eyes, and judgment threshold (+/-0.5V) and the distance between the signal maximum.May trigger first and second conversions 301 and 302 of first speed changer 1 is indicated by plus phase error 305 and phase sample 306 with data sampling respectively.Suppose to be designed to provide reasonable pulse shape (promptly with the equilibrium of reflector, thereby the similar shape that has minimum radius at the integral multiple place of bit rate to raised cosine pulse), then the threshold value by selecting data sampling to compare with it advisably can select to trigger the required amount of phase error of this speed changer.Preferably, the threshold value of first speed changer 1 in the native system is about 0.27V.Each time the phase adjusted amount that is provided is provided set by speed changer 1 yield value.
Fig. 1 a and 1b show the calcspar of preferred timing recovery system 100.The core of this system is a digital PLL, and this digital PLL can comprise phase detectors 6, proportional pulse integration loop filter (101,102,103,104,105,106) and numerically controlled oscillator 112.This loop filter shown in the figure comprises accumulator (104,105,106) and linear gain device 102, integrator path gain device 103 and first summing junction 101.This accumulator can comprise also that integration summing junction 105, delay element 106, integrator leak (integrator leakage) element 104.Here, this numerically controlled oscillator 112 can be a digital to analog converter (" DAC ") 112.
This preferred timing recovery system 100 can also comprise speed changer 1 and 3 gain variables 15 and 12 separately respectively; Speed changer 1,2 and 3 multiplier 16,18 and 22 separately; Speed changer 1 and 2 threshold value 13 and 14 separately; The booster element 21 of speed changer 3 and comparator 23.Preferably, system 100 also comprises phase error comparator 17, summing junction 19, output terminal of clock 20, differentiator summing junction 24, delay element 25 and summing junction 26.
In operation, phase detectors 6 preferably come the evaluation phase error according to two samplings of input signal, and these two are sampled as: from the data sampling 7 at the center of data eye with at the phase sample 8 of half baud after the time.Phase error can be associated with the symbol of the data that are resumed, and multiply by gain 9, and is filtered by loop filphase locking at first summing junction 101.The output of linear filter can be in summing junction 26 and other output additions from non-linear paths 1,2 and 3, and utilize DAC 112 to be converted to clock phase information.The gain of linear PLL and bandwidth preferably change according to the density and the input jiffer frequency that receive data.In the non-linear paths 1,2 and 3 each is preferably triggered by different initial conditions groups, and designed to be able to the effective ratio path gain of raising under said circumstances.First speed changer 1 is preferably based on the data pattern that receives; Second speed changer 2 is preferably based on the amplitude of data sampling; The 3rd speed changer 3 is preferably based on continuous zero service cycle or number.
Fig. 2 illustrates the calcspar of first speed changer 1, and it is operated based on pattern.This circuit can receiving phase sampling 8, data sampling 7 and data 10, and search the back with a plurality of character strings of zero that plus or minus one is arranged.Preferably, comprise absolute value function module 201 and 202 and logic greater than functional module 203 and 204, so that help the location of this information.The most preferably, when the absolute value of data sampling 7 during greater than speed changer 1 threshold value 13, logic returns one for really exporting greater than functional module 203.Similarly, when the absolute value of data sampling 7 during greater than phase sample 8, logic preferably returns one for really exporting greater than functional module 204.These data are utilized the multiplier 16 of speed changer 1 to multiply by the gain 15 of speed changer 1 and are outputed to sum block 19 then.First speed changer 1 shown in Fig. 2 is searched four zero character string, and this is because of the cause comprising three delay elements (205,206 and 207).In other embodiments, by changing the number of delay element, first speed changer 1 can be designed to search zero of any proper number.
Preferably, second speed changer 2 shown in Figure 4, be triggered when the amplitude of data sampling 7 is lower than the second speed changer threshold value 14 of appointment, this threshold value 14 preferably is set to about 0.7V, and what judged result and sampled point shown in Figure 3 303 were indicated is plus or minus one like that.This situation may very low at packing density (that is, not having a lot of phase informations) and jitter amplitude occur when very big.Under these circumstances, PLL may not have enough phase informations realizing correctly following the tracks of input jiffer, but thereby therefore accumulated phase error makes data sampling begin to reach decision level.Therefore big fast jump may appear on the phase error direction.Though not shown in Figure 4, by increase the size that gain can be easy to change this phase step in multiplier 18 back.
Second speed changer 2 shown in Figure 4 can receive data sampling 7, data 10 and phase detectors output 405.Preferably, comprise absolute value function module 401 and 402 and logic less than functional module 403.Most preferably, when the absolute value of data sampling 7 during less than speed changer 2 threshold values 14, logic returns one for really exporting less than functional module 403.Most preferably, control phase detector output 405 by phase error comparator 17, and utilizes multiplier 18 to multiply by the absolute value of data 10 and the logic logical AND less than the output of functional module 403 by speed changer 2 Be Controlled, and exports sum block 19 to.
From understanding the operation of the 3rd non-linear paths 3 shown in Fig. 1 a and the 1b.The 3rd non-linear paths or speed changer 3 are counters, and this counter increases progressively when when the data 10 that receive being zero, and work as data 10 for being reset for the moment.When counter reaches the value that sets in the dominated variable 11 service cycle and---wherein in the most preferred embodiment this value is set at 10---, preferably output is set at height, and on the symbol direction of first differential of this accumulator output, makes immediately and jumping.This operation can help to reduce the phase error of the accumulation when existing long null string and packing density very low.In this case, may not have enough one to provide enough phase error informations, direction that therefore must this accumulative total phase error of estimation to loop filter.But, because the bandwidth of loop filter is relatively very low, so the phase place of accumulator nearly 45 degree of substantial phase error that may lag behind.Like this, the phase error direction is carried out best estimation not necessarily.First differential term of accumulator has been indicated the change direction of phase error and may has been better estimation under this condition.
In non-linear paths of the present invention, also may comprise the delay counter (not shown).These counters can prevent from repeatedly to trigger and the corresponding potential possibility of overregulating.For example, if the 3rd speed changer 3 just has been triggered, then next time input once can causing that first speed changer 1 or second speed changer 2 also are triggered, thereby cause overcorrect.Delay counter can prevent that single speed changer from being triggered by sequence bits and prevent that any speed changer is triggered in a plurality of bits of other speed changers.
Except the nonlinear Control path, preferably also comprise two other control elements in the timing recovery system of the present invention.Shown in Fig. 1 a and 1b, data density detector 4 is followed the tracks of density and control phase detector gain 9 and the linear gain 102 that receives, and changes and variation in the system responses that causes so that minimize by packing density.
Frequency detector 5 can be estimated and can be used for regulating PLL gain the frequency of input jiffer.Frequency detector 5 also can be used for regulating the leakage and the gain of accumulator, thereby prevents high dither under the situation of not sacrificing the low frequency loop gain better.
Previous embodiment of the present invention can realize in the machine readable program sign indicating number that these codings can further be stored on the machinable medium.The flow chart of Fig. 5 shows the most preferred embodiment of this coding.Forced coding at first comprises according to from the oculocentric data sampling of data of input data with come the step of evaluation phase error from the phase sample of the input data after half baud time.This phase error can be associated with the symbol of data recovered.Phase error after being associated can multiply by a gain.Thereby the related and later phase error that multiplies each other can be utilized loop filphase locking to filter and produce an output.This output can with from the path of at least one non-linear paths output ask and add.Three such non-linear paths are most preferably arranged.At last, the output after the summation can be converted into clock phase information.
As shown in Figure 6, previous embodiment of the present invention can realize in a receiver system.Preferably, this receiver system comprises acceptor circuit 61, and this acceptor circuit 61 carries out electronic communication with antenna 63.Most preferably, timing recovery system circuit 612 also carries out electronic communication with acceptor circuit 61.Timing recovery system circuit 62 is preferably according to described in above-mentioned at least one embodiment.In a preferred embodiment, antenna 63 can receive electronic signal and this signal is sent to acceptor circuit 61.Acceptor circuit can send to electronic signal timing recovery system circuit 62 then.
Though above specific embodiment of the present invention is described, is to be understood that under the situation that does not break away from spirit of the present invention and can much revises.Accessory claim will cover all modifications that do not break away from the scope of the invention and spirit.Therefore the embodiment of current description only is used for exemplary; and be not restrictive; scope of the present invention will be limited by accessory claim, rather than be limited by aforementioned specification, and all changes in the implication of the equivalent of claim and the scope all will be within its protection range.
Claims (32)
1. method that improves the jitter toleration in the communication network comprises:
At least two non-linear paths and a phase-locked loop are provided, in the described non-linear paths first regulated the phase place of input data according to the data pattern of described input data, second basis of described non-linear paths regulated the described phase place of described input data from the amplitude of the data sampling of described input data, and described phase-locked loop locks the phase of a local clock to the described phase place of described input data;
Enter data into described communication network;
According to from the data sampling at the center of the data eye of described input data with from the phase sample of the input data of half-wave after the special time, evaluation phase error;
Described phase error is associated with the symbol of recovered data;
Thereby utilize loop filter that the phase error after described being associated is filtered and produce an output;
Described output and the output summation from described non-linear paths are exported to produce a summation;
With
Described summation output is converted to clock phase information.
2. the method for claim 1 comprises that also the frequency according to the density of described input data and input jiffer changes the gain and the bandwidth of described phase-locked loop.
3. the method for claim 1 also is included in before the phase error of utilizing after described loop filter filters described association, and the phase error after described being associated be multiply by a gain.
4. the method for claim 1 wherein provides at least two non-linear paths also to comprise to provide three non-linear paths, and in described three non-linear paths the 3rd is used to the phase error that reduces to accumulate.
5. timing recovery system that is used to receive the input data with phase place comprises:
Phase-locked loop is used to lock the phase of a local clock to the phase place of described input data, and described phase-locked loop receives described input data and produces phase-locked loop output;
The first ratio path with nonlinear Control is used for regulating according to the data pattern of described input data the phase place of described input data, and the described first ratio path receives described input data and produces the output of the first ratio path;
The second ratio path with nonlinear Control is used for the amplitude of basis from the data sampling of described input data, adjusts the phase place of described input data, and the described second ratio path receives described input data and produces the output of the second ratio path; With
System's summing junction, wherein utilize described system summing junction with described phase-locked loop export, described first ratio path output and described second ratio path output summation, thereby the summing junction output of the system of generation.
6. timing recovery system as claimed in claim 5 causes that wherein the described first ratio path adjusts the described data pattern of described input data of the described phase place of described input data, for following a null string of value one in the described input data.
7. the described timing recovery system of claim 5, wherein said phase-locked loop also comprises:
Phase detectors are used to judge that the described phase place of described input data, described phase detectors receive described input data and produce phase detectors output; With
Loop filter is used for providing additional frequency characteristic, described loop filter to receive described phase detectors output and produce described phase-locked loop to described phase detectors output and exports.
8. timing recovery system as claimed in claim 7, wherein said loop filter comprises:
Accumulator, the direction that is used to indicate phase error to change, described accumulator receives described phase detectors output and produces accumulator output; With
The loop filter summing junction, wherein said loop filter summing junction produces described phase-locked loop output with described phase detectors output and described accumulator output summation.
9. timing recovery system as claimed in claim 5, wherein said timing recovery system also comprises:
The 3rd ratio path with nonlinear Control is used to the phase error that reduces to accumulate, and described the 3rd ratio path receives described input data and produces the output of the 3rd ratio path, and wherein said system summing junction is sued for peace to described the 3rd ratio path output.
10. timing recovery system as claimed in claim 5, wherein said timing recovery system also comprises an oscillator, described oscillator receives the summing junction output of described system and produces final system output.
11. timing recovery system as claimed in claim 10, wherein said oscillator are numerically controlled oscillator (DCO).
12. the described timing recovery system of claim 10, wherein said oscillator are voltage-controlled oscillator (VCO).
13. timing recovery system as claimed in claim 10, wherein said oscillator are digital to analog converter (DAC).
14. timing recovery system as claimed in claim 8, wherein said timing recovery system also comprises:
Data density detector is used to monitor that the density of described input data, described data density detector receive described input data and produces data density detector output; With
Frequency detector is used for determining the frequency of the incoming timing shake of described input data, and described frequency detector receives described phase detectors output and produces frequency detector output.
15. timing recovery system as claimed in claim 14, wherein said loop filter also comprises:
The phase detector gain element, before described phase detectors output was imported into described loop filter summing junction, described phase detector gain element received described phase detectors output, and produced the output of phase detector gain element; With
The linear gain element, described linear gain element receives described phase detector gain element output and produces the output of linear gain element, wherein said linear gain element output is imported into described loop filter summing junction, to replace being input to its phase detectors output.
16. timing recovery system as claimed in claim 15, wherein said data density detector is adjusted described phase detector gain element and described linear gain element, thereby keep constant gain and bandwidth under the situation that described packing density changes, described frequency detector is adjusted the bandwidth of described phase-locked loop with the maximization jitter toleration.
17. timing recovery system as claimed in claim 5, at least one in wherein said first ratio path and the described second ratio path comprises at least one delay counter.
18. a timing recovery system comprises:
Machinable medium; With
Be stored in the machine readable program sign indicating number in this machinable medium, this machine readable program sign indicating number have a plurality of instructions so that:
According to from the input data data eye the center data sampling and from the half-wave spy
The phase sample of the described input data after the time, the evaluation phase error;
Described phase error is associated with the symbol of recovered data;
Utilize loop filter that thereby the phase error after being associated is filtered generation
An output;
Described output and the path output from least one non-linear paths are sued for peace to produce
Give birth to a summation output; With
The output of should suing for peace is converted to clock phase information.
19. timing recovery system as claimed in claim 18, wherein said machine readable program sign indicating number also comprises instruction, is used for changing described gain according to the density of described input data and the frequency of input jiffer.
20. timing recovery system as claimed in claim 18, wherein said machine readable program sign indicating number also comprises instruction, is used for before the phase error of utilizing after described loop filter filters described association the phase error after described being associated being multiply by a gain.
21. timing recovery system as claimed in claim 18, wherein said machine readable program sign indicating number also comprises instruction, thereby is used for described output and the output that produces summation from the path output summation of three non-linear paths.
22. a receiver system comprises:
Acceptor circuit;
Carry out the antenna of electronic communication with described acceptor circuit;
Carry out the timing recovery system circuit of electronic communication with described acceptor circuit.
23. receiver system as claimed in claim 22, described receiver system receives the input data with phase place, and described timing recovery system circuit comprises:
Phase-locked loop is used to lock the phase of a local clock to the phase place of described input data, and described phase-locked loop receives described input data and produces phase-locked loop output;
The first ratio path with nonlinear Control is used for regulating according to the data pattern of described input data the phase place of described input data, and the described first ratio path receives described input data and produces the output of the first ratio path;
The second ratio path with nonlinear Control is used for the amplitude of basis from the data sampling of described input data, adjusts the phase place of described input data, and the described second ratio path receives described input data and produces the output of the second ratio path; With
System's summing junction, wherein utilize described system summing junction with described phase-locked loop export, described first ratio path output and described second ratio path output summation, thereby the summing junction output of the system of generation.
24. the described receiver system of claim 23 causes that wherein it is a null string of following value one in the described input data that the described first ratio path is adjusted the described data pattern of described input data of the described phase place of described input data.
25. receiver system as claimed in claim 23, wherein said phase-locked loop also comprises:
Phase detectors are used for determining the described phase place of described input data, and described phase detectors receive described input data and produce phase detectors output;
Loop filter is used for providing additional frequency characteristic, described loop filter to receive described phase detectors output and produce described phase-locked loop to described phase detectors output and exports.
26. receiver system as claimed in claim 25, wherein said loop filter comprises:
Accumulator, the direction that is used to indicate phase error to change, described accumulator receives described phase detectors output and produces accumulator output; With
The loop filter summing junction, wherein said loop filter summing junction produces described phase-locked loop output with described phase detectors output and described accumulator output summation.
27. receiver system as claimed in claim 23, wherein said timing recovery system circuit also comprises:
The 3rd ratio path with nonlinear Control is used to the phase error that reduces to accumulate, and described the 3rd ratio path receives described input data and produces the output of the 3rd ratio path, and wherein said system summing junction is to described the 3rd ratio path output summation.
28. receiver system as claimed in claim 23, wherein said timing recovery system circuit also comprises an oscillator, and described oscillator receives the summing junction output of described system and produces final system output.
29. receiver system as claimed in claim 26, wherein said timing recovery system circuit also comprises:
Data density detector is used to monitor that the density of described input data, described data density detector receive described input data and produces data density detector output; With
Frequency detector is used for determining the frequency of the incoming timing shake of described input data, and described frequency detector receives described phase detectors output and produces frequency detector output.
30. receiver system as claimed in claim 29, wherein said loop filter also comprises:
The phase detector gain element, before described phase detectors output was imported into described loop filter summing junction, described phase detector gain element received described phase detectors output, and produced the output of phase detector gain element; With
The linear gain element, described linear gain element receives described phase detector gain element output and produces the output of linear gain element, wherein said linear gain element output is imported into described loop filter summing junction, to replace being input to its phase detectors output.
31. receiver system as claimed in claim 30, wherein said data density detector is adjusted described phase detector gain element and described linear gain element, thereby keep constant gain and bandwidth under the situation that described packing density changes, described frequency detector is adjusted the bandwidth of described phase-locked loop with the maximization jitter toleration.
32. receiver system as claimed in claim 23, at least one in wherein said first ratio path and the described second ratio path comprises at least one delay counter.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US333001A | 2001-10-31 | 2001-10-31 | |
| US10/003,330 | 2001-10-31 |
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| Publication Number | Publication Date |
|---|---|
| CN1611030A true CN1611030A (en) | 2005-04-27 |
| CN100413245C CN100413245C (en) | 2008-08-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB028265300A Expired - Fee Related CN100413245C (en) | 2001-10-31 | 2002-10-30 | Timing recovery with variable bandwidth phase locked loop and non-linear control paths |
Country Status (3)
| Country | Link |
|---|---|
| CN (1) | CN100413245C (en) |
| AU (1) | AU2002348098A1 (en) |
| WO (1) | WO2003039063A2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101171788B (en) * | 2005-05-06 | 2011-04-13 | 英特尔公司 | Regulating the timing between a strobe signal and a data signal |
| CN101005481B (en) * | 2006-01-20 | 2012-05-02 | 富士通半导体股份有限公司 | Demodulation circuit and demodulating method |
| CN103125073A (en) * | 2010-08-30 | 2013-05-29 | 剑桥模拟技术股份有限公司 | Nonlinear and concurrent digital control for a highly digital phase-locked loop |
| CN104579324A (en) * | 2013-10-18 | 2015-04-29 | 现代摩比斯株式会社 | FM continuous wave radar system and application method |
| CN104683056A (en) * | 2014-12-30 | 2015-06-03 | 广东大普通信技术有限公司 | Compensation method and compensation system of high-retention clock adaptive PTP (picture transfer protocol) flow |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3566480D1 (en) * | 1985-05-23 | 1988-12-29 | Itt Ind Gmbh Deutsche | Frequency synthesis circuit for the generation of an analogous signal with a digitally stepwise tunable frequency |
| US5493700A (en) * | 1993-10-29 | 1996-02-20 | Motorola | Automatic frequency control apparatus |
| US6154510A (en) * | 1999-05-03 | 2000-11-28 | Sicom, Inc. | Symbol timing recovery based on adjusted, phase-selected magnitude values |
-
2002
- 2002-10-30 WO PCT/US2002/034489 patent/WO2003039063A2/en not_active Application Discontinuation
- 2002-10-30 AU AU2002348098A patent/AU2002348098A1/en not_active Abandoned
- 2002-10-30 CN CNB028265300A patent/CN100413245C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101171788B (en) * | 2005-05-06 | 2011-04-13 | 英特尔公司 | Regulating the timing between a strobe signal and a data signal |
| CN101005481B (en) * | 2006-01-20 | 2012-05-02 | 富士通半导体股份有限公司 | Demodulation circuit and demodulating method |
| CN103125073A (en) * | 2010-08-30 | 2013-05-29 | 剑桥模拟技术股份有限公司 | Nonlinear and concurrent digital control for a highly digital phase-locked loop |
| CN103125073B (en) * | 2010-08-30 | 2016-09-07 | 剑桥模拟技术股份有限公司 | system and method for phase-locked loop |
| CN104579324A (en) * | 2013-10-18 | 2015-04-29 | 现代摩比斯株式会社 | FM continuous wave radar system and application method |
| CN104579324B (en) * | 2013-10-18 | 2018-02-23 | 现代摩比斯株式会社 | Frequency modulated continuous wave radar system and its application method |
| CN104683056A (en) * | 2014-12-30 | 2015-06-03 | 广东大普通信技术有限公司 | Compensation method and compensation system of high-retention clock adaptive PTP (picture transfer protocol) flow |
| CN104683056B (en) * | 2014-12-30 | 2018-06-22 | 广东大普通信技术有限公司 | A kind of high compensation method for keeping the adaptive PTP flows of clock and compensation system |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2003039063A2 (en) | 2003-05-08 |
| WO2003039063A3 (en) | 2004-02-12 |
| AU2002348098A1 (en) | 2003-05-12 |
| CN100413245C (en) | 2008-08-20 |
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