CN1609882A - Realizing method for ultrasonic B film playback circuit based on programable logic device - Google Patents
Realizing method for ultrasonic B film playback circuit based on programable logic device Download PDFInfo
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Abstract
The present invention is B-mode ultrasonic film replaying circuit based on programmable logic device for controlling data memory for B-mode ultrasonic film replaying. The data memory is realized with SDRAM, and the circuit is realized with one programmable logic device and consists of microprocessor interface module, memory controlling module, input fore end data recording module, output selecting module, arbitration module, and film replaying scanning line creating module. The microprocessor is matched with the circuit to control the distribution of image data in data memory and non-volatile memory. Compared with available technology, the present invention has lower hardware cost and raised integral performance of B-mode ultrasonic film replaying circuit.
Description
Technical field
The present invention relates to the Type B ultrasonic diagnostic equipment, relate in particular to real-time Type B ultrasound image data is stored in the circuit that shows in order to preservation and playback in the storer.
Background technology
Prior art relates to real-time Type B ultrasound image data is stored in the storer in order to preserve and the circuit of playback demonstration, usually adopt asynchronous dynamical random access memory (DRAM) or asynchronous static RAM (SRAM) as data-carrier store, and adopt a plurality of integrated circuit to cooperate the control of realization storer.But, DRAM exists narrow bandwidth, the slow shortcoming of access speed, then there is the shortcoming that capacity is little, power consumption is big and cost is high in SRAM, and adopts a plurality of integrated circuit to cooperate and realize that storer control also can cause cineloop circuit cost height, capacity is limited and lacks dirigibility.
Summary of the invention
The technical problem to be solved in the present invention is to avoid above-mentioned the deficiencies in the prior art part, and propose to make up that a kind of capacity is big, access speed is fast, cost is low and the method for playback memorizer control circuit that can flexible configuration.
The technical scheme that the present invention solves the problems of the technologies described above employing is, a kind of implementation method of the B ultrasonic cineloop circuit based on programmable logic device (PLD) is proposed, in order to make up the circuit that used data-carrier store in the B ultrasonic cineloop process is controlled, described data-carrier store adopts synchronous DRAM (SDRAM) to realize, described circuit adopts a programmable logic device (PLD) to realize, and the inner formation of circuit comprises: with external microprocessor microprocessor linked interface module, the SDRAM control module that is connected with storer with outside B ultrasonic cineloop, the real time scan line data recordin module that is connected with the external data input front end, select module with the output that external data input front end and data output rear end are connected, and with described Microprocessor Interface module, sdram controller, the SDRAM arbitration modules that real time scan line data recordin module and output select module all to be connected, and this arbitration modules also is connected with described output selection module by cineloop sweep trace generation module.
Compare with prior art, the present invention is based on the implementation method of the B ultrasonic cineloop circuit of programmable logic device (PLD), can save the overall performance of hardware cost, raising B ultrasonic cineloop circuit.
Description of drawings
The theory diagram based on the B ultrasonic cineloop circuit of programmable logic device (PLD) of Fig. 1 for adopting that the inventive method realizes.
Fig. 2 is the theory diagram of Microprocessor Interface module among Fig. 1.
The application illustration based on the B ultrasonic cineloop circuit of programmable logic device (PLD) of Fig. 3 for adopting that the inventive method realizes.
Embodiment
Be described in further detail below in conjunction with the most preferred embodiment shown in the accompanying drawing.
The present invention is based on the implementation method of the B ultrasonic cineloop circuit of programmable logic device (PLD), in order to make up the circuit 500 that used data-carrier store 200 in the B ultrasonic cineloop process is controlled, described data-carrier store 200 adopts SDRAM to realize, this is just fast as memory speed than adopting DRAM, and SRAM is low as memory cost, volume is little than adopting again simultaneously.The B ultrasonic cineloop circuit 500 based on programmable logic device (PLD) that adopts the inventive method to realize as shown in Figure 1 adopts a programmable logic device (PLD) to realize, its inner formation comprises: with external microprocessor (CPU) 100 microprocessor linked interface modules 510, the SDRAM control module 520 that is connected with storer 200 with outside B ultrasonic cineloop, the real time scan line data recordin module 530 that is connected with external data input front end 300, select module 540 with the output that external data input front end 300 and data output rear end 400 are connected, and with described Microprocessor Interface module 510, sdram controller 520, the SDRAM arbitration modules 550 that real time scan line data recordin module 530 and output select module 540 all to be connected, and this arbitration modules 550 also is connected with described output selection module 540 by cineloop sweep trace generation module 560.
As shown in Figure 2, described Microprocessor Interface module 510 comprises again: microprocessor block operations controlling sub 511, write SDRAM controlling sub 513, read SDRAM controlling sub 514, microprocessor generates submodule 515 and register controlled submodule 512, writes buffer memory 1 submodule 516, writes buffer memory 2 submodules 517, reads buffer memory 1 submodule 518, reads buffer memory 2 submodules 519 the SDRAM operational order; Wherein: microprocessor block operations controlling sub 511 is connected with external microprocessor 100 with register controlled submodule 512, microprocessor generates submodule 515 to the SDRAM operational order and is connected with described SDRAM arbitration modules 550 with register controlled submodule 512, microprocessor block operations controlling sub 511 is connected with 517 and writes SDRAM controlling sub 513 by writing cache sub-module 516, microprocessor block operations controlling sub 511 submodules also are connected with 519 and read SDRAM controlling sub 514 by reading cache sub-module 518, and write SDRAM controlling sub 513 and read SDRAM controlling sub 514 and all with microprocessor the SDRAM operational order is generated submodule 515 and be connected.
The function that the B ultrasonic cineloop circuit based on programmable logic device (PLD) that adopts the inventive method to realize is finished has: direct output, the real time data of real time data writes the cineloop storer, when system is in the cineloop state, reads playback of data output, CPU from the cineloop storer and directly high speed access, the cineloop storer of cineloop storer are divided under the normal mode.
Whether the division of cineloop storer is subjected to system's display mode, scan pattern and has storage mode zone etc. to influence.
Scan pattern has two kinds: the low-density pattern of 128 lines/frame and the high-density mode of 256 lines/frame.
The cineloop area dividing has two kinds: logging mode, and circulation is upgraded when B-scan, always preserves the historical echo data of up-to-date B-scan; The renewal of storage mode memory contents is controlled by CPU, freeze or playback state under, can select that the logging mode storage area is current just to deposit the storage mode storage area in the data of a frame of playback, the Type B echo data in the storage mode zone can be preserved always, unless system CPU will be removed.
The logging mode zone can be defined as single and two two kinds of mode of operations, when the logging mode zone definitions is single mode of operation, if single B scanning, current B-scan data can both be deposited in then whole logging mode zone, but when two B scan, whole logging mode zone is divided equally into two zones automatically, deposits the scan-data of B1 and B2 respectively, and promptly scan-data can only deposit its corresponding storage area in; But when the logging mode zone definitions was double working modes, whole logging mode zone was divided equally into two zones all the time, when two B scan, deposit the data of B1 and B2 respectively, but when single B scanned, scan-data can only deposit B1 or B2 in.
Used programmable logic device (PLD) in the embodiment of the invention, the field programmable gate array (FPGA) that adopts U.S. altera corp to provide, model is EP1K100, adopt fpga chip to realize originally the control task that will a plurality of again chip cooperatings could realize, on the one hand, the reliability of the volume of whole playback circuitry and power consumption, raising entire circuit can be reduced, on the other hand, the dirigibility of whole playback circuitry in configuration can be improved greatly.Each composition module about circuit 500 inside is described in more detail below:
Real time scan line data recording module 530: a real time scan line of this module buffer memory data, and start and to write the sdram operation, real time scan line data are write among the sdram; In addition, this module is also divided the cineloop storer according to system's display mode and storer partition mode.
Cineloop sweep trace generation module 560: this module generates sweep trace control timing signal, and starts and read the sdram operation, reads a sweep trace to buffer zone from sdram, and then according to the sweep trace sequential, the cineloop data is exported.
Module 540 is selected in output: this module is that real time scan line data or cineloop data are exported to the rear end according to the model selection of system.
Sdram arbitration modules 550: the Sdram transmission that this module selects which module of response to bring according to system state is applied for, and is sent application to Sdram controller module 520.
Sdram controller module 520: this module realizes the control timing of Sdram, and it is converted into the Sdram time sequential routine with the Sdram operation application of inside, and is optimized at the actual conditions of cineloop circuit application, to satisfy the requirement of high-speed data operation.Two Sdram chips 200 of these Sdram controller 520 controls.For flexibly, Sdram control circuit 500 is provided with the mode register of preserving various delay parameters, can be by outer setting, and the mode register of Sdram also can be by outer setting, and outer setting is to be realized by CPU 100 in the design.
Cpu i/f module 510: this module mainly realizes 100 communications with CPU, finishes the high speed reads write operation of 100 couples of Sdram of CPU and the CPU control to the cineloop module.For realizing high speed Sdram operation, CPU operates Sdram by read-write cache; In order further to improve operating speed, Twin Cache Architecture has all been adopted in read-write, so just can adopt the ping-pong operation mode.The structure of cpu i/f module 510 as shown in Figure 2, to it each submodule specify as follows:
CPU block operations controlling sub 511: this submodule is converted into the read-write operation of programmable logic device (PLD) block RAM with the read-write operation of cpu bus, and supports the burst operation pattern of CPU.
Write buffer memory 1 submodule 516, write buffer memory 2 submodules 517: these two submodules are used for the blocks of data of buffer memory CPU when writing Sdram, adopt the ping-pong operation mode, owing to adopt dual port RAM, the CPU operation can be different with the working clock frequency of Sdram operation, and can shield the difference on CPU and the Sdram operating speed.
Read buffer memory 1 submodule 518, read buffer memory 2 submodules 519: these two submodules are used for the blocks of data of buffer memory CPU when reading Sdram, adopt the ping-pong operation mode, owing to adopt dual port RAM, the CPU operation can be different with the working clock frequency of Sdram operation, and can shield the difference on CPU and the Sdram operating speed.
Write Sdram controlling sub 513: this submodule writes CPU the blocks of data morsel of buffer memory and writes the Sdram transmission to the application of Sdram arbitration modules, adopts the ping-pong operation mode, is used alternatingly two and writes buffer memory.
Read Sdram controlling sub 514: this submodule is read the Sdram transmission with the blocks of data morsel of CPU request to the application of Sdram arbitration modules, and writes and study in buffer memory, adopts the ping-pong operation mode, is used alternatingly two and reads buffer memory.
CPU generates submodule 515 to the Sdram operational order: the various operation applications to Sdram of the comprehensive CPU of this submodule, unification is sent application to the Sdram arbitration modules.
Register controlled module 512: this submodule is realized the control operation of CPU to circuit 500, comprising: the ping-pong operation control of CPU read-write Sdram, the initialization of Sdram, the setting of Sdram controller parameter, the control of system works pattern etc.
Below, further each intermodule interface relation in the circuit 500 is described in detail:
Real time scan line Data Input Interface:
ECHO_ST: echo sweep trace start signal occurs when each sweep trace information begins to transmit
The 320ns positive pulse.
ECHO_S[1:0]: the echo condition indicative signal
00:B type scan-line data, the last sweep trace in the non-frame
01:B type scan-line data is the last sweep trace in the frame
10:M type scan-line data
11: keep
ECHO_AD[7:0]: scanning wire size and echo data multiplex bus
ECHO_ADSEL: scanning wire size and echo data indicator signal
0:ECHO-AD[7..0] for scanning wire size
1:ECHO-AD[7..0] be echo data
CK160: the echo data clock, the 160ns synchronous clock, all above-mentioned signals are with this clock synchronization
The time scan-line data logging modle and sdram arbitration modules interface
CINE_WR_OP_REQ: echo data application operation SDRAM
CINE_WR_OP_CODE: the operational code of echo data operation SDRAM
CINE_WR_RW: echo data operation SDRAM read-write indicator signal
CINE_WR_SD_ADDR[22:0]: the SDRAM start address
SD_BUSY_N:SDRAM controller busy signal
SRC_EN: write the input of SDRAM data enable signal
CINE_WR_DO[15:0]: write the SDRAM data
Cineloop sweep trace generation module and sdram arbitration modules interface
CINE_RD_OP_REQ: cineloop application operation SDRAM
CINE_RD_OP_CODE[2:0]: the operational code of cineloop operation SDRAM
CINE_RD_RW: cineloop operation SDRAM read-write indicator signal
CINE_RD_SD_ADDR[22:0] the SDRAM start address
SD_BUSY_N:SDRAM controller busy signal
DATA_VALID:SDRAM data useful signal
CINE_RD_DI[15:0]: read the input of SDRAM data
Cineloop sweep trace generation module and sdram arbitration modules interface
CINE_LINE_START: sweep trace start signal
CINE_LINE_S[1:0]: the sweep trace state
00:B type scan-line data, the last sweep trace in the non-frame
01:B type scan-line data is the last sweep trace in the frame
10: keep
11: keep
CINE_AD[7:0]: the scan-line data address bus
CINE_ADSEL: scan-line data address indicator signal
Cpu i/f module and sdram arbitration modules interface
CPU_OP_REQ:CPU application operation SDARM
CPU_OP_CODE[2:0]: CPU operation SDRAM sign indicating number
CPU_SD_RW:CPU operation SDRAM read-write indicator signal
CPU_SD_ADDR[22:0] CPU operation SDRAM address
SD_REF_BEG sdram controller refresh counter begins count signal
SD_BUSY_N:SDRAM controller busy signal
SRC_EN:SDRAM controller data application signal
DATA_VALID:SDRAM data useful signal
CPU_SD_DO[15:0]: write the output of SDRAM data
SD_CPU_DI[15:0]: read the input of SDRAM data
Cpu bus interface
CPU_CS1_N: cineloop storer chip selection signal, low level is effective
CPU_CS2_N: the register chip selection signal, low level is effective
CPU_ADDR[23:0]: address bus
CPU_D[15:0]: data bus
CPU_TS_N: bus transfer begins indicator signal
CPU_RW: read-write control signal
CPU_TA: bus transfer corresponding signal
CPU_CLK: bus clock signal
SDRAM arbitration modules and sdram controller interface
Op_req sdram operation application signal
0 not application
1 sdram operation application (a clock width can only be arranged)
Op_code[2:0] the input bit manipulation
| 2??1??0 | Operational code |
| 0??0??0 | Keep |
| 0??0??1 | Precharge |
| 0??1??0 | Automatically refresh |
| 0??1??1 | Mode register is set |
| 1??0??0 | Activate |
| 1??0??1 | Keep |
| 1??1??0 | Keep |
| 1??1??1 | Keep |
Sd_busy_n sdram controller busy signal
0 sdram controller is busy, shielding sdram operation application
1 sdram controller idle can accept the sdram operation application
The control of Rd_wr read-write operation
0 write operation (effective simultaneously) with Op_request
1 read operation (effective simultaneously) with Op_request
Addr[22:0] sdram address or mode register sign indicating number
During read-write operation: addr22 selects the sdram chip.
bank[1:0]＝addr[21:20]
raw_addr[11:0]＝addr[19:8]
Column_addr[7:0]＝addr[7:0]
During the mode register operation: M[13:0]=addr[21:8]
Di[15:0] input of sdram write operation data
Sdram controller inside does not have data buffer, requires subscriber's line circuit to realize writing data and actual sdram
That operates is synchronous.
Src_en write operation user data ready signal
Src_en represents that effectively user logic will be ready to data at next clock
Do[15:0] output of sdram read operation data
Data_valid sdram read operation data useful signal
The SDRAM bus interface
Clk sdram work clock
Cke sdram clock enable signal
Csl_n sdram chip selection signal 1
Cs2_n sdram chip selection signal 2
Ras_n sdram orders input signal
Cas_n sdram orders input signal
We_n sdram orders input signal
Dqm[1:0] sdram data I/O enable signal
Bank[1:0] sdram bank selects signal
Sd_addr[11:0] the sdram address bus
Sd_d[15:0] the sdram data bus
The module output interface is selected in output
IMG-ST: the scanning line period indicator signal when each sweep trace information begins to transmit
Existing 320ns positive pulse
IMG-S[1..0]: the sweep trace status information
00:B type scan-line data, the last sweep trace in the non-frame
01:B type scan-line data is the last sweep trace in the frame
10:M type scan-line data
11: keep
IMG-AD[7..0]: scanning wire size and echo data multiplex bus
IMG-ADSEL: scanning wire size and echo data indicator signal
0:IMG-AD[7..0] for scanning wire size
1:IMG-AD[7..0] be echo data
The CLK160:160ns synchronous clock, all above-mentioned signals are with this clock synchronization
As shown in Figure 3, the inventive method has also adopted nonvolatile memory 600, microprocessor 100 and circuit 500 cooperatings, can control view data allocates between data-carrier store 200 and nonvolatile memory 600, promptly can be to nonvolatile memory 600 data conversion storage on the data-carrier store 200, to realize the long preservation of data, also can be to data-carrier store 200 the data readback on the nonvolatile memory 600.Adopt the sort memory configuration structure, can overcome that existing B ultrasonic view data does not dump on the nonvolatile memory 600 and the image that causes can only be done playback and shows and use, and can not be used for the further defective of analysis, and the image of just having gathered before not only can playback freezing can also playback be stored in the image on the nonvolatile memory 600.
The most preferred embodiment of the above is intended to specify the present invention's mentality of designing: adopt the data-carrier store of SDRAM as the B ultrasonic film, and adopt the control of programmable logic device (PLD) realization to SDRAM, promptly on programmable logic device (PLD), realize functional circuit parts such as cpu i/f, SDRAM control, data input front end interface and data output interface simultaneously, the SDRAM storer is controlled with realization.The present invention's mentality of designing also has: nonvolatile memory is set in order to the relevant B ultrasonic view data of long preservation in B ultrasonic cineloop circuit.In a word, the present invention's enforcement is not limited to the disclosed mode of above most preferred embodiment, all mentalities of designing based on the present invention, simply deduce and replace the implementation method of the B ultrasonic cineloop circuit that obtains, even if this implementation method is better than disclosed method, also all belong to enforcement of the present invention.
Claims (10)
1. implementation method based on the B ultrasonic cineloop circuit of programmable logic device (PLD) in order to make up the circuit (500) that used data-carrier store (200) in the B ultrasonic cineloop process is controlled, is characterized in that:
Described data-carrier store (200) employing SDRAM realizes that described circuit (500) adopts a programmable logic device (PLD) to realize, and the inner formation of circuit (500) comprises:
With external microprocessor (100) microprocessor linked interface module (510),
The SDRAM control module (520) that is connected with storer (200) with outside B ultrasonic cineloop,
The real time scan line data recordin module (530) that is connected with external data input front end (300),
Module (540) is selected in the output that is connected with external data input front end (300) and data output rear ends (400), and
The SDRAM arbitration modules (550) of selecting module (540) all to be connected with described Microprocessor Interface module (510), sdram controller (520), real time scan line data recordin module (530) and output, and this arbitration modules (550) also is connected with described output selection module (540) by cineloop sweep trace generation module (560).
2. the implementation method of B ultrasonic cineloop circuit as claimed in claim 1 is characterized in that: described Microprocessor Interface module (510) comprising: microprocessor block operations controlling sub (511), write SDRAM controlling sub (513), read SDRAM controlling sub (514), microprocessor generates submodule (515) and register controlled submodule (512), writes buffer memory 1 submodule (516), writes buffer memory 2 submodules (517), reads buffer memory 1 submodule (518), reads buffer memory 2 submodules (519) the SDRAM operational order; Wherein: microprocessor block operations controlling sub (511) is connected with external microprocessor (100) with register controlled submodule (512), microprocessor generates submodule (511) to the SDRAM operational order and is connected with described SDRAM arbitration modules (550) with register controlled submodule (512), microprocessor block operations controlling sub (511) is write SDRAM controlling sub (513) by writing the cache sub-module connection, microprocessor block operations controlling sub (511) also connects and to read SDRAM controlling sub (514) by reading cache sub-module, all with microprocessor SDRAM operational order generation submodule (515) is connected and write SDRAM controlling sub (513) and read SDRAM controlling sub (514).
3. the implementation method of B ultrasonic cineloop circuit as claimed in claim 1 is characterized in that: described output selects module (540) to export to outside data output rear end (400) in order to handle from the data of external data input front end (300) or from the data of cineloop sweep trace generation module (560).
4. the implementation method of B ultrasonic cineloop circuit as claimed in claim 1 is characterized in that: described SDRAM control module (520) can be controlled two SDRAM chips (200) that the outside connects.
5. the implementation method of B ultrasonic cineloop as claimed in claim 1 is characterized in that: comprise also in the described circuit (500) that it can carry out read-write operation by outside microprocessor linked (100) in order to preserve the mode register of various delay parameters.
6. the implementation method of B ultrasonic cineloop circuit as claimed in claim 2, it is characterized in that: described register controlled submodule (512) comprises in order to realize the control of external microprocessor (100) to SDRAM arbitration modules (550): the ping-pong operation control of external microprocessor read-write SDRAM, the initialization of SDRAM, the setting of sdram controller parameter and the control of system works pattern.
7. the implementation method of B ultrasonic cineloop circuit as claimed in claim 2 is characterized in that: the described cache sub-module of writing comprises two memory buffer (516 and 517), and the described cache sub-module of reading comprises two memory buffer (518 and 519).
8. the implementation method of B ultrasonic cineloop circuit as claimed in claim 7 is characterized in that: write memory buffer (516 and 517) and be Double Port Random Memory, and connect into the ping-pong operation structure for described two.
9. the implementation method of B ultrasonic cineloop circuit as claimed in claim 7 is characterized in that: read memory buffer (518 and 519) and be Double Port Random Memory, and connect into the ping-pong operation structure for described two.
10. as the implementation method of B ultrasonic cineloop circuit as described in arbitrary in the claim 1 to 9, it is characterized in that: described circuit (500) cooperates with microprocessor (100), allocates between data-carrier store (200) and nonvolatile memory (600) in order to control data.
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| CNB2003101119522A CN100388293C (en) | 2003-10-24 | 2003-10-24 | Realizing method for ultrasonic B film playback circuit based on programable logic device |
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| CNB2003101119522A CN100388293C (en) | 2003-10-24 | 2003-10-24 | Realizing method for ultrasonic B film playback circuit based on programable logic device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105842116A (en) * | 2016-05-26 | 2016-08-10 | 合肥工业大学 | Method for plasma density measurement of magnetic confinement nuclear fusion experiment device |
| CN113506608A (en) * | 2021-06-25 | 2021-10-15 | 青岛海信医疗设备股份有限公司 | Ultrasonic film processing method and ultrasonic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5184622A (en) * | 1990-01-24 | 1993-02-09 | Kabushiki Kaisha Toshiba | Ultrasonic diagnosing apparatus |
| CN2235688Y (en) * | 1995-06-14 | 1996-09-18 | 电子工业部第三研究所 | Portable type equipment used as B ultrasonic instrument and TV set |
| JPH0956717A (en) * | 1995-08-29 | 1997-03-04 | Toshiba Corp | Ultrasonic diagnosing apparatus |
| JPH09164139A (en) * | 1995-12-13 | 1997-06-24 | Toshiba Corp | Ultrasonic diagnosing apparatus |
| JP2003135463A (en) * | 2001-11-08 | 2003-05-13 | Olympus Optical Co Ltd | Ultrasonic diagnostic instrument |
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2003
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105842116A (en) * | 2016-05-26 | 2016-08-10 | 合肥工业大学 | Method for plasma density measurement of magnetic confinement nuclear fusion experiment device |
| CN113506608A (en) * | 2021-06-25 | 2021-10-15 | 青岛海信医疗设备股份有限公司 | Ultrasonic film processing method and ultrasonic equipment |
| CN113506608B (en) * | 2021-06-25 | 2024-03-19 | 青岛海信医疗设备股份有限公司 | Ultrasonic film processing method and ultrasonic equipment |
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