CN1609833A - System and method for access important product data - Google Patents
System and method for access important product data Download PDFInfo
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- CN1609833A CN1609833A CN 200310119806 CN200310119806A CN1609833A CN 1609833 A CN1609833 A CN 1609833A CN 200310119806 CN200310119806 CN 200310119806 CN 200310119806 A CN200310119806 A CN 200310119806A CN 1609833 A CN1609833 A CN 1609833A
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Abstract
The present invention describes system and method of accessing valuable product data (VPD). The first processing system may send one configuration write request to VPD address register; the second processing system may respond one interruption system to access one VPD data register associated with the VPD address register.
Description
Technical field
Disclosed here theme relates to processing platform.Especially, theme disclosed herein relate to processing platform in equipment or the relevant information of subsystem conduct interviews.
Background technology
Processing platform generally includes and concentrates in together to satisfy the processing resource of one or more system requirements.For example, typical processing platform can comprise equipment or the subsystem that makes this processing platform can realize system requirements.This system requirements can be associated with the one or more aspects in platform property, reliability or the validity.
Processing platform generally includes one or more ADMINISTRATION SUBSYSTEM and monitors other subsystem or equipment.Usually, ADMINISTRATION SUBSYSTEM has defined data structure, so that the information that keeps those to be associated with various field replaceable units (FPU), software or firmware in the processing platform.This information generally includes performance or the fault data that is associated with particular device or subsystem.
Description of drawings
Describe nonrestrictive, incomplete embodiment of the present invention below with reference to accompanying drawing, wherein, except as otherwise noted, otherwise identical Reference numeral is all represented identical part in each figure.
Fig. 1 has shown the synoptic diagram according to the processing platform of the embodiment of the invention.
Fig. 2 has shown according to the present invention the synoptic diagram of the processing platform of an alternative embodiment.
Fig. 3 has shown the synoptic diagram according to the I/O processor of the I/O processor of Fig. 1 or Fig. 2.
Fig. 4 has shown the synoptic diagram according to I/O companion (companion) core of I/O processor embodiment shown in Figure 3.
Fig. 5 has shown according to an embodiment and has been defined the register format that is used to hold vital product data (VPD).
Fig. 6 has shown the process flow diagram according to the processing of an embodiment, and this is handled by host processing system and carries out, so that obtain VPD from the I/O processor.
Fig. 7 has shown the processing flow chart according to an embodiment, and this is handled by the I/O processor and carries out, so that information is offered the VPD data register.
Fig. 8 has shown the processing flow chart according to an embodiment, and this is handled by host processing system and carries out, so that VPD is offered an I/O processor.
Fig. 9 has shown the processing flow chart according to an embodiment, and this is handled by the I/O processor and carries out, so that be stored in the VPD that receives on the VPD data register.
Embodiment
" embodiment " that mention in the instructions full text is meant: described in conjunction with the embodiments certain feature, structure or characteristic all comprise at least one embodiment of the present invention.Therefore, phrase " in an embodiment " or " embodiment " that diverse location occurs in the instructions might not represent identical embodiment.Can make up these special characteristics, structure or characteristic in one or more embodiments in addition.
" machine readable " instruction of here mentioning relates to can be by one or more machine perceptions in order to carry out the expression-form of one or more logical operations.For instance, machine readable instructions can comprise and can be explained in order to the instruction to the one or more operations of execution on one or more data objects by the processor program compiler.Yet this only is an example of machine readable instructions, and embodiments of the invention are not limited to this on the one hand.
" storage medium " herein mentioned relates to that those can store can be by the medium of the expression-form of one or more machine perceptions.For example, storage medium can comprise one or more memory devices that are used to store machine readable instructions or data.This memory device can comprise the storage medium such as light, magnetic or semiconductor storage medium.Yet this only is an example of storage medium, and embodiments of the invention are not limited to this on the one hand.
" logical circuit " mentioned relates to the structure that those are used to carry out one or more logical operations herein.For example, logical circuit can comprise the circuit that one or more output signals are provided according to one or more input signals.Sort circuit can comprise the finite state machine that receives the numeral input and numeral output is provided, and the circuit of one or more analog output signals perhaps is provided in response to one or more analog input signals.Sort circuit can provide in a special IC (ASIC) or field programmable gate array (FPGA).Logical circuit can also comprise the machine readable instructions that is stored in the storage medium, in conjunction with treatment circuit so that carry out this machine readable instructions.Yet these only are the example of structure that logical circuit can be provided, and embodiments of the invention are not limited to this on the one hand.
" disposal system " of Lun Shuing relates to the combination of the hardware and software resource that is used to finish calculation task herein.Yet this only is an example of disposal system, and embodiments of the invention are not limited to this on the one hand." host processing system " relates to those and is suitable for the disposal system of communicating by letter with " peripherals ".For example, a peripherals can the application processing on host processing system provide input or handle reception output from this application.Yet these only are the examples of host processing system and peripherals, and embodiments of the invention are not limited to this on the one hand.
" vital product data " herein mentioned (VPD) relates to the information that those represent processing platform equipment or subsystem.For example, VPD can be the description about system hardware, software or microcode element.VPD can provide and field replaceable unit (FRU), part number, relevant information or the out of Memory of sequence number.VPD can also provide the status information relevant with equipment or subsystem, for example performance data or fault data.Yet these only are the examples of VPD, and embodiments of the invention are not limited to this on the one hand.
" data bus " herein mentioned relates to the circuit that is used for transmitting data between equipment.For example, data bus can transmit data between host processing system and peripherals.Data bus can be according to Peripheral Component Interconnect (PCI) local bus specification Rev.2.3, and on March 29th, 2002 (PCI local bus specification hereinafter) or PCI-X 2.0 protocol specifications (PCI-X 2.0 protocol specifications hereinafter) form.Yet these only are the examples of data bus, and embodiments of the invention are not limited to this on the one hand.
" bridge (bridge) " can be coupled to disposal system by " general data bus ".This bridge also can be coupled to " low priority data bus ", so that at bridge and be coupled between the equipment of low priority data bus and send data.Therefore, described bridge can send data from the equipment that is coupled to less important bus to disposal system via main bus.Equally, the bridge data that can will be received from disposal system on main bus send to the equipment that those and less important bus are coupled.Yet these only are bridges and the example of main, the low priority data bus that is coupled to bridge, and embodiments of the invention are not limited to this on the one hand.
" storer " herein mentioned relates to a system that is used for searchable format memory data.For example, storer can comprise a kind of storage medium that comprises the array of storage locations that is used to store data.This memory location can be associated with " storage address ", so that can retrieve the data of storing on this memory location.Yet these only are the examples of storer and storage address, and embodiments of the invention are not limited to this on the one hand.
Handle or entity can be on storage address in " visit " storer or the data in the storer part for one.For example, processing can reference-to storage, so that data are write the position that is associated with this storage address in this storer, or reading of data therefrom.Data can be stored in position in the sort memory in predefined data register.
" configuration header " herein mentioned relates to those memory locations that is associated with the equipment that is coupled to data bus, and these positions can be visited in being addressed to the bus events of this equipment.For example, an equipment can provide configuration header with the form of formative data, and these formative data comprise having the data field of information of resource requirement that identifies one or more functions of this equipment and/or this equipment in response to a request.Yet this only is an example of configuration header, and embodiments of the invention are not limited to this on the one hand.
Data bus protocol can define one " configuration read request ", and it can be addressed to the function of equipment or an equipment, so that the one or more fields in visit and the configuration header that equipment or function are associated.In response to a configuration read request, the data in one or more configuration header fields can be offered a request entity.Data bus protocol can also define one " configuration writes request ", and it can be addressed to an equipment, so that write data in the register of one or more configuration header.Data in one or more configuration header fields can be written in response to a configuration writes request, or are modified.Yet these only are the examples that configuration read request and configuration write request, and embodiments of the invention are not limited to this on the one hand.
" the VPD data register " herein mentioned relates to the predetermined storage location of the VPD that storage is associated with equipment or subsystem.Can write the VPD data register that request visits the PCI configuration header of the equipment of being arranged in by configuration read request or the configuration that is addressed to this equipment.Yet this only is an example of VPD data register, and embodiments of the invention are not limited to this on the one hand.
" the VPD address register " herein mentioned relates to and is used to store the predetermined storage location that makes the information that equipment or subsystem be associated with VPD information.Can write the VPD address register that request visits the PCI configuration header of the equipment of being arranged in by configuration read request or the configuration that is addressed to this equipment.The information that provides in the VPD address register can be used for locating the VPD information that is associated with particular device or subsystem.Yet this only is an example of VPD address register, and embodiments of the invention are not limited to this on the one hand.
" look-at-me " herein mentioned relates to the processing or the entity that are used on disposal system and notifies certain incident that the signal of certain situation has taken place or existed.In response to look-at-me, disposal system can be taked the behavior of an appointment.For example, disposal system can be suspended the execution of a processing temporarily, so that relevant incident or the situation of response.Yet this only is the example of look-at-me, and embodiments of the invention are not limited to this on the one hand.
" Interrupt Service Routine " or " interrupt handling routine " mentioned relate to this processing herein: disposal system is carried out this processing, so that take action in response to a look-at-me.For example, disposal system can be carried out an Interrupt Service Routine or an interrupt handling routine from instruction, and this instruction is stored in storer on this Interrupt Service Routine storage address.Therefore, in response to a look-at-me, disposal system can be suspended the execution current task and sequentially execute instruction from an instruction beginning that is positioned at the Interrupt Service Routine storage address.Yet these only are the examples of Interrupt Service Routine or interrupt handling routine, and embodiments of the invention are not limited to this on the one hand.
In brief, one embodiment of the invention relates to the system and method for visit VPD information.First disposal system can be initiated a configuration to vital product data (VPD) address register and write request.Second disposal system can visit a VPD data register that is associated with the VPD address register in response to a look-at-me.Yet this only is an embodiment, and other embodiments of the invention are not limited to this on the one hand.
Fig. 1 has shown the synoptic diagram of processing platform 10 according to an embodiment of the invention.The primary processor 12 that is coupled via core logic circuit 26 and system storage 28 can provide a host processing system, so that serve as the main frame of operating system and application program.I/O (I/O) processor 14 can be coupled with host processing system and one or more peripherals 16.Described I/O processor 14 can serve as the main frame of operating system and application program, so that control is for the visit and the management peripherals 16 of peripherals 16.
According to data bus protocol, data bus 24 can communicate I/O processor 14 with host processing system, and data bus 18 can communicate I/O processor 14 with peripherals 16.I/O processor 14 can comprise an internal bridge (not shown), and this internal bridge is defined as main bus 24 with data bus 24, and data bus 18 is defined as less important bus.According to an embodiment, can form main bus 24 and less important bus 18 according to pci data bus structure or PCI-X2.0 protocol specification, wherein the pci data bus structure can be the pci data bus structure of for example describing in the PCI local bus specification.Yet these only are bus-structured examples, and it can be used in the data bus, so that send data between equipment, and embodiments of the invention are not limited to this on the one hand.In addition, can form internal bridge according to the PCI-to-PCI bridge construction standard (" PCI-to-PCI " bridge gauge model hereinafter) of Rev.1.1 on Dec 18th, 1998.Yet this only is how to realize in processing platform that bridge forms mainly, an example of low priority data bus, and embodiments of the invention are not limited to this on the one hand.
Fig. 2 has shown the synoptic diagram according to the processing platform 100 of an alternative embodiment of the present invention, and this processing platform 100 comprises one or more peripherals 116.The peripherals 16 that is different from Fig. 1 embodiment, described peripherals 116 is directly coupled to I/O processor 114 and core logic circuit 126 by data bus 124, and irrelevant with intervention (intervening) bridge.Therefore, data bus 124 can make the host processing system that comprises primary processor 112 and system storage 128 and the functions of the equipments of peripherals 116 or peripherals 116 communicate, and and the intervention bridge that is coupling between data bus 124 and the peripherals 116 irrelevant.
In other embodiments, the I/O processor can by be provided on July 16th, 2002 Rev.1.0 PCI represent in the basic norm (hereinafter " PCI represents standard ") that a PCI who describes represents " root assembly " (the root complex) in the environment and is coupled to a host processing system as one " end points ".For example, the I/O processor can be coupled to the downstream port of " switch ", and the peripherals with other downstream port that is coupled to switch communicates simultaneously.In addition, the I/O processor can be coupled with peripherals by the data bus that forms according to PCI local bus specification or PCI-X 2.0 protocol specifications.In another example, the I/O processor can be coupled to a upstream port of second switch, so that communicate with the peripherals of the downstream port that is coupled to second switch.Yet how these are coupled so that represent the example that the peripherals in the environment communicates with host processing system and a PCI to the I/O processor, and embodiments of the invention are not limited to this on the one hand.
In this one exemplary embodiment, peripherals 16 or 116 can comprise any one in some exterior I/O equipment, for example has the equipment of the I/O interface that the variation of the small computer system interface of formulating according to the national information technology standardization council (NCITS) (SCSI) forms.Yet this only is can be by an example of the I/O interface of peripheral unit control, and can form other I/O interface, for example Fibre Channel, SSA, IBA, serial ATA or Ethernet according to different-format.The I/O interface can be suitable for some I/O equipment in any one directly or via switch communicate, for instance, described equipment can comprise storage system, communication port, server, client or other the storage system such as redundant array of inexpensive disk (RAID) (not shown).This RAID system can comprise such as the such memory device of data storage disk.
According to an embodiment, any peripherals 16 or 116 can comprise the logical circuit of detection case or incident, and the relevant one or more aspects of resource availability that provide or control with the performance of peripherals or reliability, by peripherals may be provided for described situation or incident.The loading or the application of equipment failure or functional deterioration, task may be represented in these aspects.Peripherals can be sent to a disposal system (for example, in bus events message or the outer message of band) to the information that relates to these situations or incident, so that the VPD information that conduct is associated with peripherals and being stored in the nonvolatile memory.In an example, peripherals can comprise a host bus adaptor (HBA) card, and this host bus adaptor (HBA) is blocked those information stores relevant with detected situation or incident in a nonvolatile memory.Peripherals can also be stored the information (relevant situation or incident) that this and one or more field replaceable units (FRU) are associated.Yet these only are the examples how peripherals stores those information relevant with situation or incident, and embodiments of the invention are not limited to this on the one hand.
Fig. 3 has shown the synoptic diagram according to the I/O processor 300 of the I/O processor 114 of the I/O processor 14 of Fig. 1 or Fig. 2.I/O companion core 304 can comprise the logical circuit of the bridge that has formed main, the less important bus of being coupled, and simplify core processor 302 with such as the logical circuit of communicating by letter between SDRAM308 and flash memory 306 these class memory devices.For example, I/O companion core 304 can comprise the 80312 I/O companion chips that Intel is sold.Yet this only is an example of logical circuit core, and this logical circuit core can be used for promoting the communication between the resource in the I/O processor, can be used for also promoting and communicating by letter that a host processing system is carried out that embodiments of the invention are not limited to this on the one hand.
Core processor 302 can comprise any one in some common treatment cores that can respond look-at-me, for example an i960 selling of Intel
Perhaps XScale
Handle core.In other embodiments, core processor 302 can comprise by ARM
In the heart any one of several process nuclear of the licensee of company limited design.For example, core processor 302 can be suitable for receiving and response look-at-me, for example IRQ or FIQ look-at-me.Yet this only is the example that can respond the common treatment core of interruption, and embodiments of the invention are not limited to this on the one hand.
Core processor 302 and I/O companion core 304 are to form in the independent semiconductor equipment that the request bus that communicates between these two equipment by an energy is coupled.As selection, can in single integrated semiconductor device, form core processor and I/O companion core 304.Yet these only are how integrated core processor and I/O companion core are to form the example of I/O processor, and embodiments of the invention are not limited to this on the one hand.
Fig. 4 has shown the synoptic diagram according to the I/O companion core 400 of an embodiment of I/O companion core 304 shown in Figure 3.According to PCI-PCI bridge gauge model, a PCI-PCI bridge 402 can be coupled main bus 424 and less important bus 418.A processor core (not shown) can visit memory device by core interface unit 406 and memory controller 404.
According to an embodiment, in response to receive the data bus event request on general data bus 424, companion's core 400 can trigger a look-at-me to core processor.Address translator (ATU) 420 can comprise logical circuit, and described logical circuit sends a look-at-me to core processor, and the interruption status position relevant with removing is set in an interrupt status register.In response to the bus events that is addressed to the I/O processor (for example, a memory I/O who is addressed to the bae address register (BAR) of distribution read or writing events or addressing configuration header in a configuration of register read or writing events), ATU 420 can be associated the incident that receives (for example with a destination register, BAR in a memory I/O event request or the configuration header register in a configuring request), and send look-at-me to core processor.Yet this only is the example how look-at-me of disposal system is triggered in response to the reception of data bus event request, and embodiments of the invention are not limited to this on the one hand.
Fig. 5 has shown according to an embodiment for holding register 500 forms that vital product data (VPD) defines.Register 500 can format (for example, the initial 256 byte parts after configuration header) in as the selectable VPD expansion of the PCI configuration header that illustrates in PCI local bus specification the 6.5th part and appendix 1.With in PCI local bus specification the 3rd chapter, describe the same, according to the embodiment of I/O processor 300 shown in Figure 3, the register in the PCI configuration header can in response to the configuration on the general data bus 424 that is addressed to I/O processor 300 read and configuration write the request and obtain the visit.Therefore, VPD address register 504 and VPD data register 506 can be accessed in response to the configuration read request that is addressed to the I/O processor from host processing system or configuration write request.
In the illustrated embodiment, in response to receiving a configuration on the I/O processor of VPD address register 504 and write request being addressed to, can produce a look-at-me to the core processor of I/O processor.This configurable write request can be provided with or remove a marker bit 502 of VPD address register 504.In response to look-at-me, core processor can be carried out an Interrupt Service Routine, so that write data from VPD data register 506 sense datas or to VPD data register 506, and the state of modification marker bit 502 is indicated the processing of having finished the situation of interrupting.
According to an embodiment of register 500, Fig. 6 shown by host processing system and carried out so that obtain the process flow diagram of VPD information processing 600 from the I/O processor, and Fig. 7 has described in response to handling 600 and the processing 700 carried out by the I/O processor.Piece 602,606 and 608 behavior can be controlled or be carried out by the machine readable instructions in the system storage that is stored in host processing system.At piece 602, host processing system is sent a configurable write incoming event to the VPD address register 504 of a configuration header of I/O processor.The data (writing in the request in configuration) that offer VPD address register 504 can comprise the data that for example are associated with certain peripherals of being controlled by the I/O processor or monitoring or subsystem.In response to this configurable write incoming event, can remove marker bit 502, be uncertain so that indicate request about the VPD data.
In case received the configurable write incoming event that is addressed to VPD address register 504, then the core processor to the I/O processor produces a look-at-me.In response to look-at-me, piece 702 to 708 can be carried out by an Interrupt Service Routine that provides in the firmware that is loaded into system storage, and this system storage can be by the I/O processor access.At piece 702, the I/O processor can write the data load that receives the request to VPD address register 504 from configuration with those.At piece 704, the I/O processor can be loaded into those VPD address register 504 in piece 702 data be stored in the VPD information in the memory location and be associated.This VPD information can comprise: for example, relate to the situation of one or more aspects of the performance of the peripherals that influences I/O processor control or monitor or reliability or the information of incident.For instance, the storer of this storage VPD information can be arranged in flash memory device (flash memory 306 for example shown in Figure 3), also can be positioned at random access memory (SDRAM 308 for example shown in Figure 3).Yet this only is the example how the I/O processor stores the VPD information that is associated with the VPD address information, and embodiments of the invention are not limited to this on the one hand.
At piece 706, the I/O processor can be retrieved the VPD information that those are associated with the VPD address information in the memory location, and the information that retrieves is loaded into VPD data register 506 in the I/O processor configuration header.At piece 708, the I/O processor can be provided with VPD address register 504 marker bit 502 of (requested data have been held in indication in VPD data register 506), and removes an interruption status position that is set up in response to look-at-me.At diamond 606, host processing system can be checked marker bit 502 (for example, by regular configuration read request) by regularly reading VPD address register 504, so that inquiry I/O processor, thereby determine whether to have finished request.When host processing system detects when being provided with mark 502, at piece 608, host processing system can be extracted the VPD data (for example, reading incident by the configuration of initiating the one or more I/O of being addressed to processor configuration header) of being asked from VPD data register 506.
An embodiment according to register 500, Fig. 8 has shown one to handling 800 process flow diagrams that are described, described processing is carried out by a host processing system, so that VPD information is offered an I/O processor, and Fig. 9 has described a processing 900 of being carried out by the I/O processor in response to processing 800, and the behavior of piece 802 to 810 can be controlled or be carried out by the machine readable instructions in the system storage that is stored in host processing system.At piece 802, host processing system can be initiated first configuration to the VPD data register 506 of the configuration header of I/O processor and write request.For instance, the data that offer VPD data register 506 can comprise certain peripherals or the relevant VPD information of subsystem with control of I/O processor or monitoring.At piece 804, host processing system can be sent second configuration to VPD address register 504 and write request, writes the information-related information of VPD that is provided to VPD data register 506 in the request so that provide with first configuration.Configuration at piece 804 writes in the request, marker bit 502 can be arranged to the wait request of indicating to be used to store VPD information.
In case received the configurable write incoming event that is addressed to VPD address register 504, then the core processor to the I/O processor produces a look-at-me.In response to described look-at-me, piece 902,904,906 and 908 can be carried out by the Interrupt Service Routine that provides in the firmware that is loaded into system storage, and wherein said system storage can be by the I/O processor access.The core processor of I/O processor arrives VPD address register 504 by disposing the data load that writes request (piece 804) at piece self-routing in 902 future to second of VPD address register, and dispose the VPD data load that writes request (piece 802) at piece self-routing in 904 future to first of VPD address register and arrive VPD data register 506, respond described look-at-me.
At piece 906, the I/O processor can be associated with position in the storer be loaded into the data of VPD address register 504 in piece 902, and described storer will be stored those by the control of I/O processor or the particular device that monitors or the VPD information data of subsystem.For instance, sort memory can (for example, flash memory 306 as shown in Figure 3) provide in flash memory device, also can provide in random access memory (for example, SDRAM 308 as shown in Figure 3).Then, the I/O processor can the VPD information stores that is loaded into VPD data register 506 in the piece 904 in the storer be loaded into the position that VPD address register 504 data are associated.Yet this only is the example how the I/O processor stores VPD information, and embodiments of the invention are not limited to this on the one hand.
At piece 908, the I/O processor can be removed an interruption status position, this interruption status position is in response to the look-at-me of sending and is provided with when receiving the second configurable write incoming event, and be provided with VPD address register 504 (indication the VPD information that piece 802 offers VPD data register 506 be stored in can storer by the I/O processor access in) marker bit 502.At rhombus 808, host processing system can be checked mark 502 by configuration read request by regularly reading VPD address register 504, inquires about the I/O processor so that determined whether to finish the request of storage VPD information.At piece 810, removed marker bit 502 in case detect, then host processing system can confirm: this I/O processor has suffered the VPD information stores at storer.
Though illustrated at present and described the content that is considered as example embodiment of the present invention, it will be appreciated by those skilled in the art that can make various other modification and equivalences under the prerequisite that does not depart from true scope of the present invention replaces.In addition, under the prerequisite that does not depart from center as described herein inventive concept, can make many modifications, so that concrete condition adapts to instruction of the present invention.Therefore, this means that the present invention is not limited to disclosed specific embodiment, but mean and the present invention includes all embodiment that those fall into the accessory claim scope.
Claims (32)
1. method comprises:
Initiate the configurable write incoming event from first disposal system to vital product data (VPD) address register that is associated with second disposal system; And
Write the VPD data register and responded detecting second disposal system, initiated configuration to the VPD data register that is associated with second disposal system and read incident.
2. according to the method for claim 1, described method also comprises: determine according to the part of VPD address register whether second disposal system has write the VPD data register.
3. method comprises:
The configuration that reception is addressed to vital product data (VPD) address register writes request; And
In response to look-at-me, the VPD data register that visit is associated with address in the VPD address register.
4. according to the method for claim 3, described method also comprises: received a configuration that is addressed to the VPD data register and write request before look-at-me.
5. according to the method for claim 4, described method also comprises: in response to look-at-me, the data storage that will come from the VPD data register is to the memory location that is associated with address in the VPD address register.
6. according to the method for claim 5, described method also comprises: after depositing the data in the VPD address register in memory location, revise a part of data in the VPD address register.
7. according to the method for claim 3, described method also comprises: in response to look-at-me,
The position visit VPD data that from storer, are associated with the data that are provided to the VPD address register; And
The VPD data are write the VPD data register.
8. according to the method for claim 7, wherein said method also comprises:
After the VPD data are write the VPD data register, revise the part of VPD address register.
9. article comprise:
Stored the storage medium of machine readable instructions on it, described machine readable instructions is used for:
Initiate the configurable write incoming event from first disposal system to vital product data (VPD) address register that is associated with second disposal system; And
Write the VPD data register and responded detecting second disposal system, initiated configuration to the VPD data register that is associated with second disposal system and read incident.
10. according to the article of claim 10, wherein, described storage medium also comprised storage thereon, be used for determining according to the part of VPD address register whether second disposal system has write the VPD data machine readable instructions of VPD data register.
11. article comprise:
Stored the storage medium of machine readable instructions on it, described machine readable instructions is used for:
The configuration that reception is addressed to vital product data (VPD) address register writes request; And
In response to look-at-me, the VPD data register that visit is associated with the VPD address register.
12. according to the article of claim 10, wherein, described storage medium also comprise storage thereon, be used for before look-at-me receiving the machine readable instructions that the configuration that is addressed to the VPD data register writes request.
13. according to the article of claim 12, wherein, described storage medium also comprise be stored thereon, be used for the machine readable instructions in the memory location that is associated to address from the data storage of VPD data register with the VPD address register.
14. according to the article of claim 13, wherein, described storage medium also comprises the machine readable instructions that is stored thereon, be used for revising a part of data of VPD address register after will depositing the memory location in from the data of VPD address register.
15. according to the article of claim 11, wherein, described storage medium also comprises the machine readable instructions that is stored thereon, described machine readable instructions is used for coming in response to look-at-me:
From the memory location visit VPD data that are associated with the data that offer the VPD address register; And
The VPD data are write the VPD data register.
16. according to the article of claim 15, wherein, described storage medium also comprises the machine readable instructions that is stored thereon, be used for revising the part of VPD address register after the VPD data are write the VPD data register.
17. a disposal system comprises:
Be used to initiate to be addressed to the logical circuit of the configurable write incoming event of vital product data (VPD) address register that is associated with the I/O processor; And
Be used for having write the VPD data register and responding, initiate the logical circuit that incident is read in configuration to the VPD data register that is associated with the I/O processor to detecting the I/O processor.
18. according to the disposal system of claim 17, wherein, described disposal system also comprises and is used for determining according to the part of VPD address register whether the I/O processor has write the VPD data logical circuit of VPD data register.
19. an I/O processor comprises:
Be used for receiving the logical circuit that the configuration that is addressed to vital product data (VPD) address register writes request; And
Be used for visiting the logical circuit of the VPD data register that is associated with the VPD address register in response to look-at-me.
20. according to the I/O processor of claim 19, described I/O processor also comprises and was used for before look-at-me receiving the logical circuit that the configuration that is addressed to the VPD data register writes request.
21. according to the I/O processor of claim 20, described I/O processor also comprises the logical circuit that is used in response to look-at-me memory location that the data storage from the VPD data register is associated to the address with the VPD address register.
22. according to the I/O processor of claim 21, described I/O processor also comprises the logical circuit that is used for revising a part of data of VPD address register after the data that obtain from the VPD data register accesses are stored.
23. according to the I/O processor of claim 19, described I/O processor also comprises:
Be used for visiting from the memory location that is associated with the data that are provided to the VPD address register logical circuit of VPD data in response to look-at-me; And
Be used for the VPD data being write the logical circuit of VPD address register in response to look-at-me.
24. according to the I/O processor of claim 23, described I/O processor also comprises: the logical circuit that is used for revising the part of VPD address register after the VPD data are written to the VPD data register.
25. a system comprises:
Be coupled to the host processing system of first data bus;
Be coupled to one or more peripherals of second data bus; And
The I/O disposal system comprises:
Be coupling in first and second bridges between the data bus;
Be used for receiving the logical circuit that the configuration that is addressed to the VPD address register writes request from host processing system; And
Be used for visiting the logical circuit of the VPD data register that is associated with the VPD address register in response to look-at-me.
26. according to the system of claim 25, wherein, one or more peripherals comprise at least one Ethernet compatible equipment.
27. according to the system of claim 25, wherein, one or more peripherals comprise at least one serial ATA compatible equipment.
28. according to the system of claim 25, wherein, one or more peripherals comprise at least one Fibre Channel compatible equipment.
29. according to the system of claim 25, wherein, one or more peripherals comprise at least one Infiniband compatible equipment.
30. according to the system of claim 25, wherein, one or more peripherals comprise at least one SSA compatible equipment.
31. according to the system 25 of claim, wherein at least one peripherals comprises the logical circuit that is used to control for the visit of one or more memory disks.
32. a system comprises:
Host processing system;
Be coupled to one or more peripherals of data bus, described one or more peripherals comprise and are used for writing data or from least one controller of mass-memory unit reading of data to mass-memory unit; And
Be coupled to the I/O disposal system of described one or more peripherals via data bus, described I/O disposal system comprises:
Be used for receiving the logical circuit that the configuration that is addressed to the VPD address register writes request from host processing system; And
Be used for visiting the logical circuit of the VPD data register that is associated with the VPD address register in response to look-at-me.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200310119806 CN1609833A (en) | 2003-10-24 | 2003-10-24 | System and method for access important product data |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200310119806 CN1609833A (en) | 2003-10-24 | 2003-10-24 | System and method for access important product data |
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| Publication Number | Publication Date |
|---|---|
| CN1609833A true CN1609833A (en) | 2005-04-27 |
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| CN 200310119806 Pending CN1609833A (en) | 2003-10-24 | 2003-10-24 | System and method for access important product data |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110704334A (en) * | 2019-09-25 | 2020-01-17 | 苏州浪潮智能科技有限公司 | Method, system and equipment for important product data management |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110704334A (en) * | 2019-09-25 | 2020-01-17 | 苏州浪潮智能科技有限公司 | Method, system and equipment for important product data management |
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