CN1604294A - Integrated circuit chips visual aligning method - Google Patents

Abstract

It is an integration circuit chip vision aligning method belonging to integration circuit chip seal method, which comprises the following steps: to select sample from the lead wire frame and chip; to get the sample measurement coordinates by image process and to measure the defect chip by image constant moment; to get the chip position transformation parameters to get the coordinates; to get the sample non-linear error by minus measurement coordinates from computation coordinates till the error is within the permitted value; finally to transform the bonding arranged coordinates into bonding workbench displacement coordinates.

Description

Integrated circuit (IC) chip vision alignment methods

Technical field

The invention belongs to the method for packing of integrated circuit (IC) chip, be specifically related to the vision alignment methods of chip, be applicable to bonding apparatus, means for correcting, the checkout gear of chip, in modern manufacturing industries such as semiconductor equipment, LCD, film magnetic head, will be widely adopted.

Background technology

In IC and HIC manufacturing industry, the intraconnection of chip and lead-out wire connect technology and mainly contain technologies such as thermocompression bonding, Si-Al wire ultrasonic bonding, gold ball bonding bonding, flip chip bonding, carrier band weldering.Wherein gold ball bonding technology is widely used in the inner lead and lead-out wire interconnection process of large scale integrated circuit and extensive thick film hybrid integrated circuit as one of main bonding technology; In circuit with the wiring of high reliability request, gold copper-base alloy, to use more extensively, its processing quality directly influences overall product quality and reliability.Along with making rapid progress of designs level and manufacturing technology especially packaging technology, require to have than higher in the past precision, productivity ratio, reliability as the bonding apparatus of the nucleus equipment of IC production line later process.In recent years, each renowned company of the world such as K﹠amp; S, ASM etc. greatly develop and have released below the solder joint positioning accuracy 2.5 μ m, and bonding wire speed is greater than the automatic gold wire bonder of 12 lines/s, as K﹠amp; The U-TEK of S, the ENGLE-60 of ASM etc., wire bond pitch has also reached 40-30 μ m." real packing technique " Vol.18 in 2002, the No.3 report, it is the techniques of mass production of the gold bonding lead-in wire (superfine gold thread) of 10 μ m that Tanaka Electronics Industry Company has developed diameter.The development of large scale integrated circuit, para-linkage technology is also had higher requirement.Automatic Alignment System and detent mechanism are carried out the error analysis of system, be not only the prerequisite of improving bonding technology, also be successfully the basis of positioning table and bonding head.

Different bonding machine vision alignment methods in period adopt different technology.Adopt artificial naked eyes identification the beginning of the seventies; After the end of the seventies,, begin to introduce image recognition because the integrated scale of circuit constantly enlarges.Wherein Imamura people such as (1977) proposed the elder generation with specialized circuitry the substrate draw-foot image is carried out preliminary treatment, the method of discerning with microcomputer again and locating (Application ofmicro-computer to fully-automatic die-bonder.In:NationalTechnical Report, 1977; 23 (6): 1102 ~ 1111); Hsieh, Y.Y. and Fu, k.s. (1979) etc. have then been designed grader according to pattern recognition theory and are come substrate image is classified, utilize the ballot technology to discern and locate then, hardware then adopts parallel processing technique to deal with a large amount of calculating (Method for automatic ic chip alignment and wirebonding.In:Proceedings-IEEE Computer Society Conference onPattern Recognition and Image Processing, 1979:101 ~ 108); KawatoS. (1979) and Doemens G. people such as (1982) then use this respect in microcomputer identification and have done unremitting exploration; Negin (1985) has designed independently picture recognition module, the main network calculations that adopts is carried out pattern matching (Image processing/computer vision work station.In:1985 IEEE Microprocessor Forum:Design Productivity ThroughEngineering Workstations, 1985:99 ~ 105).Fazekas people such as (1987) has then carried out optimizing (Fast algorithm for thecomputation of moment invariants, Pattern Recognition1987,20:639 ~ 643) at the picture contrast algorithm of template matches.Between 1992 ~ nineteen ninety-five, ESEC SA has developed image identification system ESWIS for the Wire Bonder 3006 of oneself, remain and adopt template matching algorithm to discern substrate draw-foot, process range is confined to the image of very little square region, the time that on the computer of CPU68020, needs 40S, after the employing DSP preliminary treatment, also need the time of 4S, further optimized Algorithm and simplify template just reaches the realistic scale of 0.08S.The same period, the Lin Junbai of China (1991) etc. has also carried out the research that replaces industrial camera with projecting apparatus: since substrate at diverse location to the reflection of light difference, so the reflection of available photo Darlington induction projecting apparatus realizes identification and location.After this, the substrate draw-foot image recognition develops towards the template matches direction based on the statistical model recognition technology always, Ye, Q.Z. (2000), Wang Mao-JIUN J. (2002) etc. are carrying out big quantity research (A stereo vision system for the inspectionof IC bond-wire.International Journal of Imaging Systems andTechnology 2000 aspect raising recognition speed and the precision; 11 (4): 254～262).

At present, the bonding machine mainly adopts the vision alignment methods.The various alignment algorithms that shorten the aligning time also emerge in an endless stream, and the inferior pixel alignment algorithm in gray scale edge, method of fuzzy cluster analysis, the neural network image that mainly contain spatial moment are discerned alignment algorithm etc.Below they are done brief description and analysis.

1, the inferior pixel alignment algorithm in the gray scale edge of spatial moment

Rim detection in the gray level image and be positioned with many classic algorithm, wherein great majority are Pixel-level.The method that obtains the inferior pixel positioning accuracy in edge in the bianry image generally has two kinds: a kind of is superposition by the dither image sequence; Another kind of then be to reach inferior pixel precision with the some alignment by union edge on the continuous boundary.Inferior pixel measure in the gray level image can reach inferior pixel positioning accuracy on the marginal point of single-frame images.Inferior pixel edge localization method commonly used has: rise a regional interpolate value of falling a liter in gradient and determine the position; Utilize the square of marginal point neighborhood intensity profile to estimate the match edge; The Hilbe that area data is transformed to 9 parameters looks for appearance and the location of space with the check edge; LoG template associating facet Model Calculation zero is worn.Set up the edge model of spatial moment operator and the inferior pixel parameter of deriving, the worst case precision analysis is carried out in marginal point, edge line and straight edge zone, improve the precision of tolerance and aligning by the selected shape parameter with the analysis result that minimizes this error.

2, method of fuzzy cluster analysis

The method of fuzzy cluster analysis key step is as follows, at first carries out initial segmentation, and raw video is divided into two big (or a plurality of) zones.In order to obtain final segmentation result, adopt the FCM algorithm further in two big zones, to classify.In conjunction with initial segmentation result, obtain brightness floor, the zone of saturation image of the original image signal in two general objective districts.Calculate gray average, variance, Law energy template and the saturation characteristic value of each pixel then, form the matrix of forming by pixel and characteristic value.Calculate the degree of membership and the cluster centre of each pixel again.If the number of categories that adopts is 2, two cluster centres are arranged then.Each pixel is calculated two class degrees of membership, pixel is sorted out, when degree of membership is got minimum value, obtain final segmentation result according to the size of degree of membership.The elevation information of chip and lead frame can carry out initial segmentation to raw video, by pixel is sorted out, extracts characteristic area, calculates offset deviation, realizes accurately aiming at.

3, neural network image identification alignment algorithm

Key step is as follows, at first chooses the substrate draw-foot image with rotation translation invariant characteristic; In addition, background and pin gray scale difference also should be bigger in the image.Set up artificial nerve network model then, the model of artificial neural net is a lot, and different application can be adopted different models.Gather the learning training sample again, with the method training network that has the tutor to train, the network that final acquisition has recognition capability.At last, the process of identification is actual is exactly the feedforward part of network training process.After software receives image from CCD, start " feature extraction " module automatically, obtain the characteristic vector of substrate draw-foot image; Vector is imported into the network of having trained then, according to feedforward arithmetic, obtains an output valve between 0 and 1 as recognition result.In order to reduce mistake identification, improve the reliability of software, can in software, set judgement: when output valve greater than 0.6 the time, represent that recognition image comprises standard pin; When output valve less than 0.4 the time, the expression recognition image does not comprise standard pin; All the other situations require the user to assist to provide judgement then to user report, so that guiding software is further learnt, the weights of corrective networks and threshold value make it to be more suitable for the production actual conditions.Simultaneously, differentiation and correction result all will be stored in the journal file, and corresponding substrate draw-foot image also will be numbered preservation, as the foundation of recognition effect research, also can be used as the sample of network training.

As theory analysis, above algorithm has proposed some useful alignment algorithms, but does not combine closely with concrete production process, and the chip that brings in the paster technique and the position error of lead frame have been left in the basket.Simultaneously, above-mentioned algorithm only applies to single alignment mark, if single marking has bigger local deformation or measure error, still uses it as alignment mark, and alignment precision is significantly reduced.Comprise the ink dot mark in the whole alignment procedures, collapse the limit cut, the rejecting of defective chip such as hollow sheet, the front algorithm mainly adopts the calculation process of serial, computational speed is restricted.

Summary of the invention

The invention provides a kind of integrated circuit (IC) chip multiple labeling vision alignment methods, limitation at above-mentioned existing vision alignment methods, even realize being marked with individually the non-linear site error that causes because of local deformation or measure error, each bonding point is aimed at fast and accurately with the precalculated position.

A kind of integrated circuit (IC) chip multiple labeling vision alignment methods of the present invention, order comprises the steps:

(1) lead frame that will post chip places workbench, with the feature holes central point at four angles on the standard wire framework and four angle points of standard chips as the design sample point, be stored in the computer earlier together with bonding point coordinate on standard wire framework and the standard chips, utilization comprises that the image vision system of light source and infrared camera CCD obtains the picture signal of actual chips and lead frame, picture signal to the CCD input is carried out preliminary treatment, obtains the pel array that reflects that characteristics of image is required;

(2) carry out the image chip edge fitting, try to achieve the four edges boundary line of chip on the lead frame, try to achieve 4 intersecting point coordinates of described boundary line again;

When (3) above-mentioned steps 2 is carried out, carry out the lead frame image characteristics extraction, provide four gauge point coordinates on the lead frame;

(4) store the chip image of standard in the computer in advance, converter torque ratio is not to utilize the gray scale correlation technique that actual chips is carried out chip image, if check out the ink dot mark, collapse the limit cut, defective chip such as hollow sheet, then return step (1), carry out next chip to aim at; Otherwise carry out next step;

(5) carry out the calculating of six transformation parameter a～f:

A=Rx, b=-Rx (W+ θ), c=Ry θ, d=Ry, e=Ox, f=Oy; Wherein wafer rotates residual error angle θ, and stage coordinates is quadrature error W, the linear extendible error Rx and the Ry of wafer, and center wafer coordinate offset amount Ox and Oy,

Utilize equation

$\left[\begin{array}{c}X\\ Y\end{array}\right]=\left[\begin{array}{cc}a& b\\ c& d\end{array}\right]\left[\begin{array}{c}x\\ y\end{array}\right]+\left[\begin{array}{c}e\\ f\end{array}\right]$

Get known be stored in the main memory 8 design sample point coordinates (x, y), substitution equation the right; Four gauge point coordinates of 4 intersection points of the chip boundary line that step (2), (3) draw and lead frame, obtain altogether 8 mark coordinates (X, Y), best least square solution is tried to achieve on the substitution equation left side, obtains six transformation parameters;

(6) with six transformation parameter a～f be stored in the computer 8 design sample point coordinates and take back the described equation of step (5), the coordinates computed of 8 gauge points;

(7) difference of the measurement coordinate that draws of coordinates computed and step (2), (3) image processing constitutes the nonlinearity erron vector, obtains the nonlinearity erron vector of each sample point;

(8) nonlinearity erron vector compares with permissible value, if the nonlinearity erron vector greater than permissible value, is selected on lead frame and the adjoining feature holes of sample point sample point as an alternative, returns step 6; Otherwise carry out next step;

(9),, calculate the bonding head stage coordinates value of bonding point on actual leads framework and the actual chips by the linear transformation of the described equation of step (5) with bonding point coordinate figure on six transformation parameter a～f, standard wire framework and the standard chips;

(10), drive bonding head by bonding head control system drive motors and realize the lead-in wire bonding according to the bonding head stage coordinates value that calculates.

Described alignment methods, it is characterized in that: stage coordinates system determine to start in system at every turn the time, the platform upper left corner and the lower right corner find a job, mid point with the lower left corner and lower right corner line is the absolute coordinate initial point, with on lead frame and the chip coordinate of totally eight design sample points be stored in the main memory earlier.

Described alignment methods, it is further characterized in that: when asking chip four edges boundary line and their intersection point, utilize the method at the least-squares estimation match edge of marginal point neighborhood intensity profile, getting near the pixel of gray scale intermediate value is sample point, in the formula that the substitution square is estimated, obtain the boundary line again.

The present invention adopts a plurality of signatures, has overcome the influence of the local deformation of single marking to alignment precision.On the other hand, by on framework and chip, choosing mark respectively, can revise the error of bringing in the paster technique.And will reject bad chip and coordinate Calculation parallel processing, improve production efficiency, realize the aligning of precise and high efficiency.

Characteristics of the present invention mainly show following several respects:

1, response has splendid linearity and sensitivity because CCD is for luminosity, therefore adopts line array CCD that the edge is aimed at and can obtain very high alignment precision;

2, this scheme adopts and substitutes the bigger mark of nonlinearity erron vector, has reduced measure error;

3, various errors between chip and framework have been considered to be present in the paster technique to the influence of lead key connection quality;

4, adopt gray level image not bending moment can reject defective chip fast;

5, many signatures have guaranteed the accuracy of result of calculation, have improved lead-in wire bonding precision;

6,, improved the production efficiency of lead-in wire bonding by simple and effective mathematical statistics and numerical computation method;

7, this scheme is to the multilead number, and production in enormous quantities has obvious superiority.

Description of drawings

Fig. 1 is a FB(flow block) of the present invention;

Fig. 2 is the physical structure schematic diagram of the image vision system of the inventive method;

Fig. 3 is the control system calcspar of image collecting device among Fig. 2;

Fig. 4 is the intensity profile of chip boundary pixel;

Fig. 5 has flawless intensity profile and contrast for chip under the various situations;

Fig. 6 arranges and the boundary line for the sample point that obtains with alignment methods of the present invention;

Fig. 7 A has shown the nonlinearity erron vector of each sample point among Fig. 6 for example;

Fig. 7 B has shown the alternative nonlinearity erron vector that calculates each sample point of back.

Embodiment

The present invention is further described below in conjunction with accompanying drawing.

Fig. 2 has shown the image vision system that applies to alignment methods of the present invention.The light that emits from coaxial lights 1 is after oval shape mirror 2 reflections, and ruddiness passes filter 3.Light forms the collimated light beam vertical with optical axis through even mating plate 4 then, through spectroscope 5, and the chip surface of vertical irradiation to the workbench 15, this light path is the coaxial lights light path.It can produce best contrast to smooth uniform figure.Except that coaxial lights 1, above workbench 15, also be fixed with 4 side lamps of forming by the light-emitting diode group of red brightness 8, they are installed in around the coaxial lights, and at a certain angle according to chip, side lamp rugged place, 8 pairs of surfaces and edge can produce best contrast.In order further to obtain the tangible image of contrast, the brightness of coaxial lights 1 and side lamp 8 can be regulated by master control system 16 as required.

Image extraction system among Fig. 2 is by constituting with the lower part, the light of the strong contrast that coaxial lights 1 and side lamp 8 produce is reflected on chip, enter object lens 6, then by spectroscope 5 reflections, make vertical light become horizontal light, pass field stop 9 again, be imaged on the CCD target surface 10, the big I of the target surface of formation is regulated by field stop 9.So just obtain the pel array of 256 grades of gray scales.In order to reach pinpointed focus, adjust the height of object lens 6 by controller 7.

Then pel array is carried out preliminary treatment, utilize multiple labeling alignment algorithm of the present invention then, obtain the bonding head stage coordinates value of each bonding point, drive linear electric motors 13 by master control system 16, drive bonding head workbench 12 and move along X, Y, Z direction, last ultrasonic wave drives chopper 11 and realizes the lead-in wire bonding.

Calcspar is described the control system of image collecting device among Fig. 2 among Fig. 3.Wherein, master control system 16 comprises Lighting Control Assembly 21, and image pick-up card 22 is aimed at computing unit 23, main memory 24, intensity contrast system 25, main control computer 26, object lens regulating system 27, bonding head control system 28, monitor 29.

Among Fig. 3,22 pairs of picture signals from CCD10 of image pick-up card are carried out preliminary treatment, form 256 grades of gray scale 768 * 576 pel arrays, the data parallel that obtains output, and one the tunnel exports to intensity contrast system 25, through the gray scale correlation computations, judges that chip has zero defect.Just notifying main control computer 26 to enter next chip as the fruit chip defectiveness aims at, does not have defective then to continue the calculating of back.Obtain 4 alignment marks on the framework simultaneously, coordinate figure is imported main memory 24, the aligning that is used for the back calculates.Another circuit-switched data is input to aims at computing unit 23, utilizes the least-squares estimation of marginal point neighborhood intensity profile to carry out match to the border.And obtain intersection point, and in conjunction with 4 marks of front, adopt the multiple labeling alignment algorithm, obtain the coordinate position of each bonding point, by main control computer 26 coordinate figure is outputed to bonding head control system 28 at last, drive linear electric motors 13 bonding that goes between.Monitor 29 is used for amplifying demonstration bonding process and initial alignment.

Describe the specific implementation process of this alignment algorithm in detail below with reference to Fig. 1.At first, the lead frame that will be posted chip by master control system 16 places on the workbench 15, stage coordinates system determine to start in system at every turn the time, find a job the platform upper left corner and the lower right corner are the absolute coordinate initial point with the mid point of the lower left corner and lower right corner line.Fig. 6 has shown the position of chip on lead frame, and we select 4 angle points of chip as alignment mark.Each mark is near 90 ° of arrangements like this, and indicia distribution is also very even.On framework, select other 4 alignment marks in the same way owing to there is feature holes around on the framework, with the feature holes central point at four angles of lead frame also as the design sample point.Before aiming at, their coordinate must be stored in earlier in the computer main memory 24, in order to using later on.

In 101 steps of Fig. 1, the picture signal of CCD10 input is carried out preliminary treatment.Obtain the pel array that reflects that characteristics of image is required.Next divide two-way to carry out, in 102 steps, carry out chip boundary match, 103 steps and ask the boundary line intersection point; In 104 steps, carry out the lead frame image characteristics extraction.

See the edge fitting in 102 steps earlier, Fig. 4 has shown the intensity profile of chip boundary pixel.We can see that the gray scale difference of chip and lead frame is very big.(Xsi, Ysi), they should be dispersed near the theoretical regression straight line Ys=m+nXs as sample point to select n pixel on the boundary line L1 in Fig. 4.The different die size of what of pixel can be different, 40-60 all can, for example the chip of 10 * 10mm is chosen 50 pixels.

Will find straight line now, (Xsi is Ysi) to the quadratic sum Q minimum of the y deviation of directivity of straight line to make each sample point.Promptly

$Q(m,n)=\underset{i=1}{\overset{n}{\mathrm{\Σ}}}{[\mathrm{Ysi}-(m+\mathrm{nXsi})]}^2---\left(1\right)$

Ask Q about the partial derivative of m, n and make them equal zero, just obtain the estimated value of m, n

$\hat{n}=\frac{\mathrm{\Σ}(\mathrm{Xsi}-\stackrel{\‾}{X}s)\×(\mathrm{Ysi}-\stackrel{\‾}{Y}s)}{\mathrm{\Σ}{(\mathrm{Xsi}-\stackrel{\‾}{X}s)}^2}---\left(2\right)$

$\hat{m}=\stackrel{\‾}{Y}s-\hat{n}\stackrel{\‾}{X}s---\left(3\right)$

Xs, Ys are respectively sample average in the following formula, so we try to achieve boundary line equation L1 are $\hat{Y}s=\hat{m}+\hat{n}\mathrm{Xs},$ Same boundary line has 4, adopts above-mentioned same quadrat method, gets other three boundary line L2, L3, L4 among Fig. 6.103 the step in, utilize 102 the step 4 linear equations, 103 the step by simple computation try to achieve they 4 intersection points (X1, Y1)～(X4, Y4), these 4 the signature points that are on the chip.

In 104 steps, provide four sample points on the lead frame, its essence is the pattern recognition problem of a two dimensional image.We utilize the matching process based on provincial characteristics, extract representative region and chip area in the image lead frame.From the structure of lead frame, there are representative region and chip area on the lead frame.Owing to have feature holes around on the lead frame, and the gray scale in the feature holes and the gray scale at its edge have saltus step on gradient.According to this feature, can detect potential feature holes image border with the LoG operator to entire pixel array, to the classification of feature holes marginal point, form the feature holes central point by gradient operator as the seed point.To the seed spot scan, still press the gray value difference, when the gray scale of scanning area does not have saltus step, just think that scanning area is exactly the representative region that we will look for, chip area is also determined by same mode, the gray scale of chip area and the gray scale of its lead frame have saltus step on gradient, can detect potential chip area image border with the LoG operator to whole area pixel array.Ranks coordinate to representative region compares, and obtains four sample points of feature holes central point conduct on lead frame at four angles of lead frame.Calculate the area of all representative regions, wherein the zone of area maximum is exactly a chip area.

In 105 steps, utilize chip image not converter torque ratio detect defective chip, its main purpose is identification ink dot mark, collapses defectives such as limit cut, hollow sheet, essence is that chip is carried out images match.Store the chip image of standard in the computer, with the chip image figure and the test pattern coupling of gathering.Because bending moment can fully not reflect characteristics of image, we calculate the not bending moment of chip image.When the not bending moment of the chip area that calculates and the not bending moment that is stored in the chip image in the memory compare, when the not bending moment of the chip area that calculates be stored in memory chips image bending moment does not equate the time, we think that chip is intact, and when the not bending moment of the chip area that calculates does not wait with the not bending moment that is stored in the chip image in the memory, think the chip defectiveness.Chip area image f (m, not bending moment n) is defined as:

$J_{\mathrm{pq}}=\underset{m}{\mathrm{\Σ}}\underset{n}{\mathrm{\Σ}}{m}^p\·n^q\·f(m,n)$

P wherein, q are the exponent number of bending moment not, get second order and calculate; M, n are the chip area image pixel, and obviously bending moment and zone are not to concern one to one.

Fig. 5 has shown the chip of various defectiveness situations, and during the chip defectiveness, operation moved towards for 106 steps, carried out next chip and aimed at; For intact chip, obtained 8 sample point P1～P8 as shown in Figure 6, wherein P1～P4 point is the chip angle point, they can be fixed on chip on the framework fully.Mark P5～P8 is from the sample point on the framework, the position of representational framework on workbench.The measurement coordinate figure of sample point P1～P8 is stored in order to next step use.

In 107 steps, carry out (the calculating of a～f) of six transformation parameters.Why have six transformation parameters? because by theoretical chip is regular arrangement on lead frame.But in fact because nonlinearity erron can appear in underlying cause.

(1) wafer rotation residual error angle θ;

(2) stage coordinates is quadrature error W;

(3) the linear extendible error Rx and the Ry of wafer;

(4) center wafer coordinate offset amount Ox and Oy;

According to top four error amounts six transformation parameters (a～f) is just arranged.To solve now be utilize these six parameters (a～f) will arrange coordinate (x, y) be transformed to bonding head worktable displacement coordinate (X, Y), we represent just like drag:

$\left[\begin{array}{c}X\\ Y\end{array}\right]=\left[\begin{array}{cc}a& b\\ c& d\end{array}\right]\left[\begin{array}{c}x\\ y\end{array}\right]+\left[\begin{array}{c}e\\ f\end{array}\right]---\left(4\right)$

Its concrete derivation is as follows:

$\left[\begin{array}{c}X\\ Y\end{array}\right]=\left[\begin{array}{cc}\mathrm{Rx}& 0\\ 0& \mathrm{Ry}\end{array}\right]\left[\begin{array}{cc}\cos \mathrm{\θ}& -\sin \mathrm{\θ}\\ \sin \mathrm{\θ}& \cos \mathrm{\θ}\end{array}\right]\left[\begin{array}{cc}1& -\tan W\\ 0& 1\end{array}\right]\left[\begin{array}{c}x\\ y\end{array}\right]+\left[\begin{array}{c}\mathrm{Ox}\\ \mathrm{Oy}\end{array}\right]$

$=\left[\begin{array}{cc}\mathrm{Rx}\cos \mathrm{\θ}& -\mathrm{Rx}(\cos \mathrm{\θ}\tan W+\sin \mathrm{\θ})\\ \mathrm{Ry}\sin \mathrm{\θ}& \mathrm{Ry}(-\sin \mathrm{\θ}\tan W+\cos \mathrm{\θ})\end{array}\right]\left[\begin{array}{c}x\\ y\end{array}\right]+\left[\begin{array}{c}\mathrm{Ox}\\ \mathrm{Oy}\end{array}\right]$

Because rotation side-play amount θ (by the decision of silicon chip prealignment precision) and orthogonality deviation ω (by the decision of work stage precision) are always very small, therefore above-mentioned nonlinear equation can be simplified to following first-order linear equation (if require higher precision, then can be reduced to the second order or the equation of higher order):

$\left[\begin{array}{cc}\mathrm{Rx}& -\mathrm{Rx}(W+\mathrm{\θ})\\ \mathrm{Ry\θ}& \mathrm{Ry}\end{array}\right]=\left[\begin{array}{cc}a& b\\ c& d\end{array}\right]\left[\begin{array}{c}X\\ Y\end{array}\right]=\left[\begin{array}{cc}\mathrm{Rx}& -\mathrm{Rx}(W+\mathrm{\θ})\\ \mathrm{Ry\θ}& \mathrm{Ry}\end{array}\right]\left[\begin{array}{c}x\\ y\end{array}\right]+\left[\begin{array}{c}\mathrm{Ox}\\ \mathrm{Oy}\end{array}\right]$

Order

$\left[\begin{array}{cc}\mathrm{Rx}& -\mathrm{Rx}(W+\mathrm{\θ})\\ \mathrm{Ry\θ}& \mathrm{Ry}\end{array}\right]=\left[\begin{array}{cc}a& b\\ c& d\end{array}\right];\left[\begin{array}{c}\mathrm{Ox}\\ \mathrm{Oy}\end{array}\right]=\left[\begin{array}{c}e\\ f\end{array}\right]$

Just obtain top model equations (4).Wherein

a＝Rx，b＝-Rx(W+θ)，c＝Ryθ，d＝Ry，e＝Ox，f＝Oy；

Utilize best least square method can obtain six transformation parameters (a～f).8 sample point P1～P8 at first by on the chip lead framework, selecting, the arrangement coordinate that obtains designing (x1, y1)～(x8, y8), substitution model equations (4) the right.Secondly, have 8 sample points that the front draws according to image processing the bonding head stage coordinates (X1, Y1)～(X8, Y8).Best least square solution is tried to achieve on substitution model equations (4) left side, obtains six transformation parameters (a～f).Then, with six transformation parameters (a～f) inverse iteration is gone into model equations (4), utilize to arrange coordinate (xi, yi), obtain sample point coordinates computed (XMi, YMi).

In 108 steps, (Xi, (XMi YMi) just obtains the nonlinearity erron vector Lai of this point of various kinds Yi) to deduct the coordinates computed of trying to achieve in 107 steps with the bonding head stage coordinates.In ensuing 109 steps, whether the absolute value of judging nonlinearity erron vector Lai is greater than predetermined permissible value Lc.Because the minimum diameter of present gold bonding lead-in wire is 10 μ m, consider amount of calculation and guarantee precision, we get the predetermined permissible value of its 10-1% as the nonlinearity erron vector, for example we to get Lc be 0.5 μ m.If the nonlinearity erron absolute value of a vector is less than or equal to permissible value Lc, promptly | Lai|≤Lc sets up, and we think that the nonlinearity erron of sample point is less, meet the demands.If the nonlinearity erron absolute value of a vector is greater than permissible value Lc, promptly | Lai|＞Lc sets up, and we weed out this sample point Pi.Operation turning to for 112 steps, selected the alternative sample point as Pi with the adjoining feature holes PBi of sample point Pi.Operation turned to for 107 steps, and the coordinate figure substitution model equations (4) that substitutes coordinate figure and meet the demands is recomputated parameter (a～f), judge the size of nonlinearity erron vector again.

Fig. 7 A has shown the nonlinearity erron vector of the sample point P1～P8 of the amplification that obtains for example in 108 steps.Sample point Pi is represented by nonlinearity erron vector Lai.The starting point of Lai is represented the sample point coordinate figure (XMi of 108 steps calculating, YMi), end points is represented the sample point bonding head stage coordinates (Xi that records, Yi), express the nonlinearity erron vector of other sample point successively, the nonlinearity erron vector that two sample point P1, P6 are arranged among Fig. 7 A is greater than permissible value.Therefore the P1 point is weeded out, select the some PB6 adjacent with P6 as an alternative again, Fig. 7 B has shown the alternative nonlinearity erron vector that calculates the back sample point, can see that its nonlinearity erron obviously diminishes.

By above calculating, six transformation parameters (a～f) to the end.In 110 steps,, calculate the bonding head stage coordinates value of each pin by the setting coordinate figure of model equations (4) and pin.The whole aligning of so just having finished the lead-in wire bonding calculates.In 111 steps, drive bonding head and realize the lead-in wire bonding by bonding head control system drive motors.

The present invention is except above application, can also be used for scanning-exposure apparatus, correcting chip figure at means for correcting, monitor the equipment of the modern manufacturing industries such as supervising device of graphics chip.And the position of the area arrangement on the chip, sample point number, sample point, the position of selecting replacement point, maximum permissible value can be as the case may be and different.

Claims (3)

1. an integrated circuit (IC) chip vision alignment methods comprises the steps: in proper order

(1) lead frame that will post chip places workbench, with the feature holes central point at four angles on the standard wire framework and four angle points of standard chips as the design sample point, be stored in the computer earlier together with bonding point coordinate on standard wire framework and the standard chips, utilization comprises that the image vision system of light source and infrared camera CCD obtains the picture signal of actual chips and lead frame, picture signal to the CCD input is carried out preliminary treatment, obtains the pel array that reflects that characteristics of image is required;

(2) carry out the image chip edge fitting, try to achieve the four edges boundary line of chip on the lead frame, try to achieve 4 intersecting point coordinates of described boundary line again;

When (3) above-mentioned steps 2 is carried out, carry out the lead frame image characteristics extraction, provide four gauge point coordinates on the lead frame;

(4) store the chip image of standard in the computer in advance, converter torque ratio is not to utilize the gray scale correlation technique that actual chips is carried out chip image, if check out the ink dot mark, collapse the limit cut, defective chip such as hollow sheet, then return step (1), carry out next chip to aim at; Otherwise carry out next step;

(5) carry out the calculating of six transformation parameter a～f:

A=Rx, b=-Rx (W+ θ), c=Ry θ, d=Ry, e=Ox, f=Oy; Wherein wafer rotates residual error angle θ, and stage coordinates is quadrature error W, the linear extendible error Rx and the Ry of wafer, and center wafer coordinate offset amount Ox and Oy,

Utilize equation

$\left[\begin{array}{c}X\\ Y\end{array}\right]=\left[\begin{array}{cc}a& b\\ c& d\end{array}\right]\left[\begin{array}{c}x\\ y\end{array}\right]+\left[\begin{array}{c}e\\ f\end{array}\right]$

Get known be stored in the main memory 8 design sample point coordinates (x, y), substitution equation the right; Four gauge point coordinates of 4 intersection points of the chip boundary line that step (2), (3) draw and lead frame, obtain altogether 8 mark coordinates (X, Y), best least square solution is tried to achieve on the substitution equation left side, obtains six transformation parameters;

(6) with six transformation parameter a～f be stored in the computer 8 design sample point coordinates and take back the described equation of step (5), the coordinates computed of 8 gauge points;

(7) difference of the measurement coordinate that draws of coordinates computed and step (2), (3) image processing constitutes the nonlinearity erron vector, obtains the nonlinearity erron vector of each sample point;

(8) nonlinearity erron vector compares with permissible value, if the nonlinearity erron vector greater than permissible value, is selected on lead frame and the adjoining feature holes of sample point sample point as an alternative, returns step 6; Otherwise carry out next step;

(9),, calculate the bonding head stage coordinates value of bonding point on actual leads framework and the actual chips by the linear transformation of the described equation of step (5) with bonding point coordinate figure on six transformation parameter a～f, standard wire framework and the standard chips;

(10), drive bonding head by bonding head control system drive motors and realize the lead-in wire bonding according to the bonding head stage coordinates value that calculates.

2. vision alignment methods as claimed in claim 1, it is characterized in that: stage coordinates system determine to start in system at every turn the time, the platform upper left corner and the lower right corner find a job, mid point with the lower left corner and lower right corner line is the absolute coordinate initial point, with on lead frame and the chip coordinate of totally eight design sample points be stored in the main memory earlier.

3. vision alignment methods as claimed in claim 1 or 2, it is characterized in that: when asking chip four edges boundary line and their intersection point, utilize the method at the least-squares estimation match edge of marginal point neighborhood intensity profile, getting near the pixel of gray scale intermediate value is sample point, in the formula that the substitution square is estimated, obtain the boundary line again.

Images