CN1604089A - Side-based reversed order tree scanning line algorithm optimized layer domain checking technology - Google Patents
Side-based reversed order tree scanning line algorithm optimized layer domain checking technology Download PDFInfo
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Abstract
It is a method to lower the difficulty of grade layout technique with computation VLSI based on inverse layout tree scanning line computation, which is characterized by the following steps: it uses limbic scanning line computation and VLSI layout validation local principle and introduces concepts of inverse layout tree and halo element and invents two types of ILT, which are exist state and non-exist state when in limbic computation and analyzes and compute the layout through the combination of the projection method and inverse tree scanning line method.
Description
Technical field (body matter)
A kind of reversed order tree scan-line algorithm based on the limit is optimized layer domain checking technology and is belonged to layout verification technical field in integrated circuit CAD (IC CAD) field, especially the IC cad tools
Background technology (body matter)
The later stage of integrated circuit (IC) design comprises layout design and layout verification, and these two functions are the important steps in the eda tool; Layout verification is the geometric design rules according to layout design, the logical relation of electricity rule and original input is carried out accuracy verification to layout design and can be passed through circuit and Parameter Extraction, the input file that produces breadboardin carries out the back simulation, checks electric property to advance one one.
Present stage, the design scale of integrated circuit just changed to great scale (GSI) by ultra-large (VLSI), manufacturing process is then changed to the nanometer amount utmost point by sub-micro (VDSM), along with the rapid expansion of domain scale, traditional territory verification method is in the demand that all lags behind the user aspect computing velocity and the internal memory use.
Recently, domain level verification technique becomes the key content of VLSI verification technique research in the current IC cad tools.It can utilize the characteristics of domain level, reduces unnecessary operation and computing but does not also have a kind of ten minutes system and complete level domain treatment technology at present, is applicable to the hierarchical relationship of form of ownership.The evolution process of its implementation can divide following several stages substantially:
● all domain is broken up, and all repetitive patterns are all wanted repetitive operation.
● identical unit is only handled once, and remaining element may repetitive operation.
● the subregional figure in middle part, unit is identical, only handles once, and all the other regional figures may repetitive operation.Here the zone of indication generally is a rectangle.
● layer different in the unit consider respectively, if a certain layer figure is identical, only handle once, and all the other layer consider that the figure on these layer may repetitive operation at the territory that rezones.
● whether the foundation that repeats in the unit further refine to each figure and repeats, and the figure that repeats is only handled once, only different graphic is handled respectively.
● notice that figure is made up of the limit, if most of limit of different graphic is identical, still can be the limit as judging the foundation that repeats, thus reduce the operation that repeats the limit.
Above step from top to bottom, the number of times of re-treatment is fewer and feweri, and the difficulty that level is handled is increasing.Main difficulty is that same unit is called repeatedly, and its transfer environment is often incomplete same, but difference is very trickle again.Different just repeatedly iff transfer environment with the whole unit re-treatment because of the unit, obvious inefficiency; And how to handle these different cell call environment to make in the unit other identical figure only handle once be a very thorny difficult problem.Industry member does not all have complete, the rigorous treatment method of a cover in theory at present.
Subsequently under the incomplete situation of theoretical system, the exploitation of many domain level verification tools has been adopted heuristic and technical method incremental development, promptly run into the different situation of domain level at every turn, just in algorithm, increase a kind of processing mode, if things go on like this, make that the scale sharp increase of IC cad tools software, the quality of software can not get guaranteeing.
Graphic operation in layout verification is handled at present sciagraphy, and its important thought is: no matter which upper unit the environment figure derives from, as long as in the frame scope of this unit, completely these environment are projected in this unit.When but problem is to operate in the unit in the future, how to distinguish because the difference of environment causes the different of operating process and operating result.The thought the earliest of sciagraphy comes from document " The haloAlgorithm-An Algorithm for Hierarchical Design Rule Checking of VLSI circuits ", IEEE trans.on CAD, CAD-12, No.2, pp 265-272,1993.
Summary of the invention (body matter)
The objective of the invention is to propose a kind of new technical method, " based on the level domain reversed order tree scanning Beam Method on limit " can be suitable for the layout verification under any level situation; General thought of the present invention: utilize based on the scan-line algorithm on limit and the principle of locality of vlsi layout checking, creatively introduce the notion of domain reversed order tree (ILT:Inverse Layout Tree) and projection element (halo element: in the inside, unit from the figure of other cell projections), the principle of using sciagraphy is the graphic projection of mutual operation relation being arranged in subelement with subelement in the figure of father unit, in subelement, handle these figures, propose " existence " with " existence not " two types ILT and the repeated figure behaviour who overcomes sciagraphy does the not high technological deficiency of this execution efficient.
The present invention defines two notions earlier before understanding detailed process of the present invention:
Definition 1: when adopting sciagraphy, this figure is called projection limit (halo element) if certain figure of inside, unit comes from the projection rule of other unit.If figure is represented with trapezoidal, then a trapezoidal projection element (halo element) that calls.Halo element abbreviates halo as.
Definition 2: when adopting sciagraphy, certain figure of inside, unit then calls former initial line (primitive element) to this figure if not the projection that derives from other unit.If figure is represented with the limit, then a limit is called a former initial line (primitive element).If figure is represented with trapezoidal, then a trapezoidal former initial line (primitive element) that calls.Primitive element abbreviates primitive as.And the sciagraphy treatment step is:
1. level pre-service
Whether figure has the overlapping part with the frame of subelement in each unit of top-down searching, if having, then has the part of overlapping to cut in the subelement it and subelement.Simultaneously, in subelement, write down this graphical source in which father unit.
2. respectively each bar order is operated
Owing to all comprised graphical information in each unit from different fathers unit, can not handle the figure in the unit according to common non-level disposal route, must handle respectively coming the figure in the different fathers unit, result can not all be placed in the active cell, and the figure relevant with the father unit should be put in the father unit.
The invention is characterized in and comprise following key step:
One. the halo element of each unit of top-down formation:
A) to the frame of each unit, whether calculate the father unit has figure and cell borders overlapping, lap is designated as projection limit (halo element), and formation domain reversed order tree (ILT), write down its source, these projection limits (halo element) can be inherited by its subelement, form the domain reversed order tree (ILT) of subelement.
B) situation of overlapping relation is arranged for subelement and subelement, need the figure recursive projection of one of them subelement in another subelement, form projection limit (halo element).A plurality of projections limit (halo element) of a unit only is designated as a projection limit (halo element) if repeating part is arranged, and its ILT has write down separate sources simultaneously.
Two. bottom-up the unit is operated
When the projection limit of each unit (halo element) form finish after, the figure in each unit is similar to comprises descriptive geometry computing (GOA), DRC (DRC), the operation that the net table extracts (NE) respectively.
1) the bottom-up employing scan-line algorithm in each unit is handled.On sweep trace the ordinate ordering is pressed on all limits, vertical edges does not participate in computing.The fundamental purpose of ordering is to prepare for next step state that calculates the limit.Among the program that is implemented in the in detail SCscan.cpp of step 2.
2) the bottom-up state that calculates every limit one by one on the sweep trace, state value adopts a plurality of ILT to represent, the record of state is divided into two classes, is respectively: the ILT state (NonExistStatusILT) when the ILT state (ExistStatusILT) when this limit exists and this limit do not exist.Wherein ExistStatusILT adopts a plurality of ILT storages according to different state values, and NonExistStatusILT also adopts a plurality of ILT storages according to different state values.Among the program that is implemented in the in detail UTedge.h of step 3.
As: the NOT command operation among the GOA (descriptive geometry computing) embodies the combined situation of halo element:
NOT?X?Y
It is respectively h1 and h2 that two projection limits (halo element) are arranged among the B.H1 represents the supplementary set of domain reversed order tree (ILT); Obtain the domain reversed order tree of h1* h2, h1*h2, h1* h2 respectively:
A) h1*h2 represent under the simultaneous situation of h1 and two projection limits of h2 (halo element) with unit B in former initial line (primitive) figure carry out intersection operation, operating result is a projection limit (haloelement), and its domain reversed order tree structure is identical with h1*h2.
B) h1* h2 representative exists in unit B as figure h1, but figure h2 in unit B under the non-existent situation with unit B in original (primitive) figure operate, operating result is a projection limit (halo element), and its domain reversed order tree result is the result of h1* h2 just.Judge and work as whether the front is former initial line (primitive)
Three. whether one side state is single state before fixed
I) be, then when state in front also be single numerical value, state+1 on its state value=last limit (when direction in front for just) or subtract 1 (when direction in front for bearing).
Ii) deny, then also be made up of a plurality of ILT when state in front, the ILT existence on it and last limit is in full accord, but status number will add 1 or subtract 1.
Is a. the state of judging last limit a plurality of ILT states?
I) be, then also form when state in front that its ILT existence is exactly to work as projection in front limit, when the non-ILT existence in front supplementary set that is projection limit (halo) by ILT one by one.
Ii) deny that then the ILT state " AND " on ILT existence=last limit of also forming it by a plurality of ILT when state in front is when projection in front limit (halo); The ILT state " NOT " on its non-ILT existence=last limit is when projection in front limit (halo);
Four]. utilize the boundary scan algorithm, come from document " " Time Efficient VLSIArtwork Analysis Algorithms in GOALIE2 ", 25 based on the scan-line algorithm on limit
ThDesign Automation Conference, 1988, pp.471-475. " carry out the linearization processing of geometrical edge operation in conjunction with the strategy of sciagraphy;
By last limit existence and ILT and this limit ILT of existence do not do logic " subtract " computing obtains the non-existent state in this limit.
This limit not existence on last the limit of ILT=of existence " subtracts " halo+ on this limit
The not existence on last limit " subtracts " halo on this limit
This limit is the status values on the numerical value of existence=last limit (no matter the direction on this limit is a plus or minus) not.
Among the program that is implemented in the in detail SC status.cpp of step 6
Concerning GOA operation, based on the scan-line algorithm on limit, only with to face the limit mutually relevant, i.e. combination between the halo element is at most relevant with two current limits, n for the state on each geometric operation limit
1≤ 2, n
2≤ 2, n
3≤ 2, Λ, n
k≤ 2, the number of combinations of all halo element is by 2
nReduce to
Be that number of combinations becomes linear growth by exponential increase.For DRC, the operation on every limit may be relevant with several limits on every side, but number of combinations still is a linear growth.
Five. utilize the principle of locality of domain, all first initial lines (primitive) are only handled once, when halo element participates in computing, the various combination situations of halo element all will be calculated one time, these figures that need multi-pass operations only are the subranges of halo element, rather than all other figure.Based on the scan-line algorithm on limit, only to the halo limit and because double counting is carried out on the limit that the influence on halo limit causes other state to change.
Experimental results show that it has reached intended purposes.
Description of drawings
Fig. 1 unit C synoptic diagram
Typical domain level of Fig. 2 calls
Fig. 3 call relation of tree presentation graphs 2
The Inverse Layout Tree of Fig. 4 unit C correspondence
Halo element synoptic diagram among Fig. 5 unit C
The ILT synoptic diagram of the halo element of Fig. 6 unit C
Fig. 7 level scan-line algorithm example
Limit operation chart on Fig. 8 sweep trace
ILT on Fig. 9 sweep trace on the signature on all limits and every the limit is figure as a result
Figure 10 ILT presentation graphic or figure as a result
Figure 11 inverted order is counted boundary scan method schematic flow sheet
Concrete implementation step:
Thereby the call graph of domain structure is arranged the reflection unit with the form of inverted order and by which upper unit is called, and has just formed unit ILT structure, and record projection limit (halo element) projection comes source unit, adopts the storage of domain inverted order tree structure.The concrete diagram of ILT is please referring to description of drawings, as unit C among Fig. 1 three figures are arranged, one of them active area figure and polycrystal layer figure form a metal-oxide-semiconductor, another active area figure is the figure that isolates, if have the polycrystalline figure of upper unit and its to intersect, could form metal-oxide-semiconductor, whether second step need derive from this unit to the metal-oxide-semiconductor that forms judges.The transfer environment of supposing unit C as shown in Figure 2, the call relation of the tree of Fig. 3 reflection Fig. 2 is that unit C is called by the instance of which unit; Fig. 4 arranges the figure that calls of domain structure with the form of inverted order, just formed the ILT structure of unit C; Fig. 5 then represents projection limit (halo element) synoptic diagram of unit C, and the ILT tree structure on C projection limit, unit (haloelement) is represented by Fig. 6.Among Fig. 6, the unit instance of each leaf node has a state T or F, indicates the direct sources of this halo element.T represents that halo element is directed to this instance, and F represents not to be direct sources.(sign of T or F only is for convenience of description, and in actual applications, the state that can only draw in ILT tree is the leaf node of T, and state is that the node of F does not draw and gets final product.)
How this section adds the strategy of sciagraphy in conjunction with a concrete example explanation in based on the scan-line algorithm on limit, the operating process step can be referring to accompanying drawing 11 of the present invention:
Fig. 7 represents to suppose two layer pattern X, and Y is respectively dash area and colourless part, does geometric operation " ORX Y Z ", all figures in the unit B all are the projections that comes from unit A, not (first initial line) primitive of unit B, (describe for convenient, the primitive of unit B ignores).
As Fig. 8, shown in 9, choose wherein all limits on the sweep trace, these limits are operated.These limits are designated as: a, b, c, d, e, f, g, h.Along sweep trace is bottom-up these limits are operated, the essence of operation is that the state of opposite side counts, forward limit status number adds 1, the negative-going edge status number is constant, but make the state on next bar limit subtract 1 simultaneously, at last in all limits status number be 1 limit be exactly " or " the result, status number be 2 limit be exactly " with " the result.The detailed process of operation is as follows:
(1) state to a counts:
The limit of a is the forward limit, and status number adds 1, and its ILT is:
Simultaneously, the state when obtaining a and not existing, as intermediate variable, for next step is prepared, intermediate variable is not exported simultaneously.
(2) state of b numeration:
B has 2 states, is respectively that its ILT is as follows when the state that a1 exists or a2 exists:
(state=1+1=2)
Simultaneously, the state when obtaining b and not existing as intermediate variable, for next step is prepared, notices that intermediate variable is not exported.
(3) state of c numeration:
C has 4 states, is respectively to work as b1, b2, and b3, the state that b4 exists, its ILT is as follows:
ILT
C2=ILT
B2* ILT
c=empty set deletes.
ILT
C3=ILT
B3* ILT
c=empty set deletes the c3 state.
Simultaneously, the state when obtaining c and not existing as intermediate variable, for next step is prepared, notices that intermediate variable is not exported.
(4) the 4th steps, to the numeration of the state of d:
D has 4 states, is respectively to work as c1, c2, and c3, the state that c4 exists, its ILT is as follows:
(status number=2-1+1=2)
ILT
D3=ILT
C3* ILT
d=empty set deletes.
ILT
D3=ILT
C4* ILT
d=empty set deletes.
Simultaneously, the state when obtaining d and not existing as intermediate variable, for next step is prepared, notices that intermediate variable is not exported.
(status number=0)
(5) the 5th steps are to the state numeration (with 3,4 method unanimities) of e.
(6) the 6th steps are to the state numeration (with 3,4 method unanimities) of f.
(7) the 7th steps are to the state numeration (with 3,4 method unanimities) of g.
(8) the 8th steps are to the state numeration (with 3,4 method unanimities) of h.
At last, the limit of all status numbers=1 is chosen, be exactly figure or the result, concrete outcome is Figure 10
The hardware that the present invention uses is the Enterprise 450-type workstation of a Sun Microsystems; Use UNIX operating system
This shows, the tight verification technique of optimization level domain that employing of the present invention combines based on reversed order tree scan-line algorithm and the sciagraphy on limit, its advantage mainly contain following some:
1. utilize the principle of locality of vlsi layout data and based on the characteristics of the scan-line algorithm on limit, The algorithm complex of ILT computing drops to linear degree, the execution efficient that has improved sciagraphy from And reduced data processing amount, the programming scale is compressed.
2. utilize the principle of locality introducing reversed order tree of domain and the concept of projection element to avoid repeating figure The operation amount of calculation on limit is promoted the domain processing speed, and the program scale of software is able to Compression.
3. the present invention proposes the data structure of domain reversed order tree with based on the level scan-line algorithm on limit Knot and thought and proposed the state area on halo limit is divided into existence and does not have a shape Attitude two class ILT, thus can directly utilize the state value on forerunner limit to obtain the state value on this limit. So that sciagraphy can be simplified solution " because the difference of environment causes graphic operation process and behaviour Make result's difference " this problem, make domain process effect and be improved.
Claims (8)
1. the layout verification technology based on the reversed order tree sweep trace relates to level and handles the classification of judging the limit in the limit and the state that calculates the limit, and concrete steps are as follows:
(1) level pre-service
In each unit, form the ILT (domain reversed order tree) of all figure corresponding sides.The process that forms ILT adopts the step of the top-down projection of domain hierarchical structure, projection operation is divided into: situation that figure overlaps with the Instance frame and Instance and Instance have situation two classes of intersection, when wherein Instance and Instance have intersection, utilize the method for recursive projection, seek all and have overlapping figure.Among the program that is implemented in the in detail DPgoa.cpp and UTcell.cpp of step 1.
(2) the bottom-up employing scan-line algorithm in each unit is handled.On every sweep trace, opposite side is according to the size ordering of Y coordinate, and vertical edges does not participate in computing.The fundamental purpose of ordering is to prepare for next step state that calculates the limit.Among the program that is implemented in the in detail SCscan.cpp of step 2.
(3) the bottom-up state that calculates every limit one by one on the sweep trace, state value adopts a plurality of ILT to represent, the record of state is divided into two classes, be respectively: the state (NonExistStatusILT) when the state existence (ExistStatusILT) when this limit exists or not with this limit. wherein ILT existence (ExistStatusILT) adopts a plurality of ILT storages according to different state values, and NonExistStatusILT also adopts a plurality of ILT storages according to different state values.Among the program that is implemented in the in detail UTedge.h of step 3.
(4) state value on every halo limit only depends on its direct precursor limit, and is irrelevant with the state on other limit.This be because, the ILT detail record of state correspondence the existence and the non-existent situation on all limits before it.
(5) by last limit existence and not existence ILT and the halo on this limit do logic " with " computing obtains the existence on this limit.
The existence (ExistStatusIL) on last limit of the ILT=of this limit existence " with " halo+ on this limit
The not existence (NonExistStatusIL) on last limit " with " halo on this limit
Status values+1 on the numerical value of this limit existence=last limit (if this edge direction for just).
The status values-1 on the numerical value of this limit existence=last limit (if this edge direction is for negative).
Among the program that is implemented in the in detail SCstatus.cpp of step 5
(6) by last limit existence and ILT and this limit ILT of existence do not do logic " subtract " computing obtains the non-existent state in this limit.
This limit not ILT existence (ExistStatus) on last the limit of ILT=of existence " subtracts " halo on this limit
The non-ILT existence (NonExistStatus) on last limit " subtracts " halo on this limit
This limit is the status values on the numerical value of existence=last limit (no matter the direction on this limit is a plus or minus) not.
Among the program that is implemented in the in detail SCstatus.cpp of step 6
(7) result of state computation only needs the state value of the ILT correspondence of judgement existence when distinguishing inner edge, outside, needn't consider the not ILT of existence.Among the program that is implemented in the in detail SClayer.cpp of step 7
2. the level domain inverted order based on the limit according to claim 1 is counted the boundary scan method, and it is characterised in that step realizes in detail by program DPgoa.cpp and UTcell.cpp.
3. the level domain inverted order based on the limit according to claim 1 is counted the boundary scan method, and it is characterised in that step (2) realizes in detail by program SCscan.cpp.
4. the described level domain inverted order based on the limit of claim 1 is counted the boundary scan method, and it is characterised in that step (3) comes specific implementation by program Utedge.h.
5. follow according to the described level domain inverted order based on the limit of claim 1 and count the boundary scan method, it is characterised in that step (5) comes specific implementation by program SCstatus.cpp.
6. any algorithm that combines with level scan-line algorithm of the data structure of reversed order tree and Software tool (step 2, the 3) permission that should obtain the inventor based on the limit.
7. in the level scan-line algorithm based on the limit, when calculating the state on limit, utilize the logical operation of adjacent edge ILT directly to obtain the specific implementation step of this limit state, require to obtain patent protection.
8. during the state on limit, distinguish existence and not the thought of existence two class ILT and step (the step 6) requirement obtains patent protection.
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| US5956257A (en) * | 1993-03-31 | 1999-09-21 | Vlsi Technology, Inc. | Automated optimization of hierarchical netlists |
| US6045584A (en) * | 1997-10-31 | 2000-04-04 | Hewlett-Packard Company | Multilevel and beveled-corner design-rule halos for computer aided design software |
| US5974243A (en) * | 1997-10-31 | 1999-10-26 | Hewlett-Packard Company | Adjustable and snap back design-rule halos for computer aided design software |
| WO2003021499A1 (en) * | 2001-08-29 | 2003-03-13 | Morphics Technology Inc. | Integrated circuit chip design |
| JP2003196333A (en) * | 2001-12-28 | 2003-07-11 | Nec Electronics Corp | Method for designing system lsi (large scale integration) and recording medium in which the same in stored |
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| CN102890730A (en) * | 2011-07-20 | 2013-01-23 | 北京华大九天软件有限公司 | Validation method of rectangular containing rule in layout verification of integrated circuit |
| CN102890730B (en) * | 2011-07-20 | 2016-08-10 | 清华大学 | In a kind of integrated circuit layout verification, rectangle comprises the verification method of rule |
| CN104573149A (en) * | 2013-10-17 | 2015-04-29 | 北京华大九天软件有限公司 | Repetitive error report removing method for DRC (design rule checking) of FPD (flat panel display) |
| CN106649897A (en) * | 2015-10-28 | 2017-05-10 | 北京华大九天软件有限公司 | Subunit array splicing pretreatment method of very large scale integrated circuit layout hierarchy comparison tool |
| CN106649897B (en) * | 2015-10-28 | 2019-11-15 | 北京华大九天软件有限公司 | One seed units array splices preprocess method |
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