CN1595662A - Polycrystalline SiTFT of multi-grid double-channel structure - Google Patents
Polycrystalline SiTFT of multi-grid double-channel structure Download PDFInfo
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- CN1595662A CN1595662A CN 200410010983 CN200410010983A CN1595662A CN 1595662 A CN1595662 A CN 1595662A CN 200410010983 CN200410010983 CN 200410010983 CN 200410010983 A CN200410010983 A CN 200410010983A CN 1595662 A CN1595662 A CN 1595662A
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Abstract
The invention relates to silicon polycrystal film transistor with multi-gate tow-channel structure, comprising insulating substrate (1) , SiO2 cushion layer (51), gate electrode insulating layer (53), two top gate electrodes (24) in gate electrode insulating layer (53) , drain region (3) and source region (4), gate electrode insulating layer (52) on SiO2 cushion layer (51), bottom gate electrode (23) on gate electrode insulating layer (52), bottom gate electrode (23) and top gate electrode (24) are connected by linking hole of gate electrode (25), and channel (6) formed by silicon polycrystal film on gate electrode insulating layer (52). The invention of TFT component has the same extent of close drain current of TFT made in the same condition, besides, it has more advantages such as open current increased by one time, better drive capability for load than TFT which has the same ratio of width and length, smaller area in integration matrix when supplies the same current, and increasing opening rate.
Description
Technical field
The invention belongs to technical field of semiconductors, be specifically related to a kind of driving array of polysilicon (Poly-Si) active organic electroluminescent display screen (Active Matrix Organic Light Emitting Diode is called for short AMOLED) and polycrystalline SiTFT (TFT of peripheral drive array of can be used for, Thin FilmTransistor), the driving array and the peripheral drive array polycrystalline SiTFT (P-Si TFT) that also can be used for polysilicon active matrix liquid crystal display panel (AM LCD).
Background technology
The TFT structure that is used for Poly-Si AM OLED has had multiple, modal as: autoregistration (Self-align) structure, grid skew (Off-set) structure, drain electrode light dope (LDD) structure and double grid (dual-gate) structure etc. all have the advantage and the scope of application separately.Realize that OFF leakage current is bigger although be simple and easy on the self-alignment structure technology; Although the grid off-set construction can reduce OFF leakage current effectively, ON state current also has obvious reduction; A kind of new structure of LDD structure Ceng Zuowei, more preceding two kinds of structures have bigger advantage: ON state current is bigger, and off-state current is less, compare with other two kinds of structures, the LDD structure is a kind of structure of on-off ratio maximum, and this point is even more important concerning active driving array, but its technology is complicated; The double-gate structure manufacture craft is simple and on-off ratio is bigger, also is to use more a kind of structure.The OFF leakage current of the TFT of double-gate structure (as shown in Figure 11) is very little, through checking theoretical and experiment, but its ON state current also reduce also thereupon confirm by experiment that (detailed content is seen document: High-Performance Poly-Si TFTs WithMultiple Selectively Doped Regions in The Active Layor, in-Cheol Lee, Juhn-Suk Yoo, Kee-Chan Park, Sang-Hoon Jung, Min-Koo Han, and Hyun-Jae Kim, Mat.Res.Soc.Symp.Proc.Vol.621,2000 Materials Research Society).Because it is few that ON state current reduces, and OFF leakage current has significant decline, so on-off ratio is significantly improved.
Display screen develops to big information content, high-resolution direction, requires TFT that littler size and the mobility of Geng Gao are arranged.The pixel-driving circuit of OLED is different from LCD, will have two TFT could drive the luminous dot matrix of active OLED at least, realize better display effect, and just four of needs even more TFT form the pixel-driving circuit of OLED.Will realize that in addition high gray shows that less OFF leakage current is extremely important, same ON state current also will reach predetermined requirement.The OFF leakage current of the TFT of LDD structure and double-gate structure is all less, but will reach the needed electric current of driving OLED, just must increase breadth length ratio, and this is conflicting with the high-resolution requirement of OLED.Therefore, press for a kind of P-Si TFT, when it was applied in the AM OLED array, existing less OFF leakage current had higher ON state current again, and TFT will have less breadth length ratio simultaneously.
Summary of the invention
The purpose of this invention is to provide a kind of polycrystalline SiTFT (P-SiTFT) with multiple-grid double channel structure, when the TFT of this structure is applied to the pixel drive of AM OLED and peripheral drive, can be for OLED provide enough big drive current, also enough little of off-state current simultaneously.
Shown in accompanying drawing 10 (a), 10 (b), the polycrystalline SiTFT of multiple-grid double channel structure of our design, by insulating material substrate 1, in substrate the SiO of growth in turn
2 Resilient coating 51, grid electrode insulating layer 53, two top gate electrodes 24 in grid electrode insulating layer 53, drain region 3, source region 4 are formed, and it is characterized in that: SiO
2Growth has one deck grid electrode insulating layer 52 on the resilient coating 51, and bottom gate thin film 23 is arranged in grid electrode insulating layer 52, and bottom gate thin film 23 is connected by gate electrode connecting hole 25 with top gate electrode 24; The raceway groove 6 and the a-Si resilient coating 62 of on grid electrode insulating layer 52, growing and having polysilicon membrane to form successively again, when gate electrode is added with voltage, inversion layer appears in the surface of insulating barrier 53 and following insulating barrier 52 simultaneously on raceway groove 6 is pressed close to, and realizes two paths of electric current, i.e. the double channel structure; The bottom in drain region 3 and source region 4 contacts with raceway groove 6.
Insulating material is adopted in the substrate 1 of the polycrystalline SiTFT of the multiple-grid double channel structure of our design, but as the material of any growing polycrystalline silicons such as glass, quartz, silicon chip and flexible substrate;
Bottom gate thin film 23, top gate electrode 24, gate electrode connecting hole 25, drain region 3, source region 4 material therefors can be polysilicon, Mg, Al, Mo or metal or alloy electrode materials such as MoW, MoAlMo, and general thickness is that hundreds of arrives several thousand dusts;
Grid electrode insulating layer 52,53,54 material therefor can be SiO
2, SiN
xOr SiO
2With SiN
xAlternating growth (decide according to concrete technological requirement, as long one deck SiO by concrete succession
2, long layer of sin
x, long again one deck SiO
2) insulating barrier, thickness is that hundreds of arrives several thousand dusts;
The P-Si TFT of this new structure that we design can form double-deck channel structure up and down.Compare with the P-Si TFT that obtains under identical or close process conditions, though the more self aligned P-Si TFT of ON state current is smaller, OFF leakage current has the same order of magnitude with double grid P-Si TFT.This result is confirmed by analog simulation (simulation that the model that extracts according to the experimental data of the N type of the single grid done and double grid and P type TFT carries out): the two ditch TFT of p type that adopt the processing line of Korea S PT-PLUS company to make relatively see Fig. 8 with single grid structure TFT ON state current of same breadth length ratio, and the two ditch TFT of p type relatively see Fig. 9 with single grid structure TFT off-state current of same breadth length ratio.The breadth length ratio of TFT is 11/10 among Fig. 8, Fig. 9, I
SingleThe electric current of representing single grid structure TFT, I
DualThe electric current of the two groove structure TFT of expression double grid.
The test data that above analog result provides according to Korea S PT-PLUS company obtains with Aim-Spice software, and very high at lithographic accuracy, under the good situation of process conditions, the switch current ratio of TFT can reach 10
8
As shown in figure 10, because the top grid and the bottom gate of single tube link together, so general designation gate electrode 2, resilient coating 51,52,53,54 is referred to as insulating barrier 5, the voltage that adds enough unlatchings on gate electrode 2 is (according to the technology difference, cut-in voltage is several lying prostrate between several volts at zero point) time in channel region 6, press close on the surface of insulating barrier 53 and following insulating barrier 52 inversion layer (double channel) appears simultaneously, thereby two paths of realization electric current make ON state current increase and are twice.When on the gate electrode 2 not during making alive, because after the device preparation is finished, the pass step response of TFT is just determined, the TFT of this new construction only just is equivalent to than the multi-gate structure under the equal process conditions (as Figure 11,) TFT many a bottom gate, but the upper and lower interface of raceway groove does not all have to change, so the multi-gate structure TFT that makes under OFF leakage current and the process conditions on an equal basis is identical.
This shows, when multiple-grid TFT has the same order of magnitude under the P-Si TFT OFF leakage current of the multiple-grid double channel structure that we propose and the same process conditions, ON state current doubles, this just makes the driving load capacity of the TFT that breadth length ratio is more identical increase, provide under the situation of same electric current and in the middle of integrated matrix, account for littler area, improve aperture opening ratio effectively.
Following structure accompanying drawing elaborates to device architecture of the present invention and preparation method.
Description of drawings
Fig. 1: preparation technology's flow chart of TFT of the present invention;
Fig. 2: the vertical view of TFT making step 3 back devices;
Fig. 3: the vertical view of TFT making step 7 back devices;
Fig. 4: the vertical view of TFT making step 9 back devices;
Fig. 5: the vertical view of TFT making step 11 back devices;
Fig. 6: the vertical view of TFT making step 15 back devices;
Fig. 7: the vertical view of TFT making step 17 back devices;
Fig. 8: breadth length ratio is 11/10 two ditch TFT of p type and the comparison of single grid structure TFT ON state current;
Fig. 9: breadth length ratio is 11/10 two ditch TFT of p type and the comparison of single grid structure TFT off-state current;
Figure 10 (a): after element manufacturing is finished along the A-A ' cutaway view of Fig. 7;
Figure 10 (b): after element manufacturing is finished along the B-B ' cutaway view of Fig. 5;
Figure 11: existing double grid TFT structure diagram.
Shown in Figure 10 (a) and (b), the name of each several part is called: substrate 1; Gate electrode 2 (Figure 10 only is a schematic diagram, and in fact the metal of top grid is can shape different, comprises bottom gate thin film 23 and top gate electrode 24); Drain region 3; Source region 4 (drain region and source region are the same, can exchange); Insulating barrier 5 (comprises SiO
2 Resilient coating 51, grid electrode insulating layer 52,53,54); Raceway groove 6; A-Si resilient coating 62.
As shown in figure 11, the name of each several part is called: substrate 71; SiO
2 Resilient coating 72; Drain region 73; Source region 77 (drain region and source region are the same, can exchange); Insulating barrier 74; Raceway groove 75; Gate electrode 76 (the same Figure 10 of the insulating barrier of continued growth and source-drain electrode)
As shown in Figure 1, be the manufacture craft flow chart with polycrystalline SiTFT (P-SiTFT) of multiple-grid double channel structure of the present invention, its each step is described as follows:
1. in substrate 1, be the SiO of hundreds of nanometers with plasma enhanced chemical vapor deposition (PECVD) method (also can be methods such as LPCVD) deposit one layer thickness
2(or SiN
xWait the material of other bottom gate thin film layer 21 that is fit to grow thereon) resilient coating 51, insulating material is adopted in substrate 1, but as the material of any growing polycrystalline silicons such as glass, quartz, silicon chip and flexible substrate;
2. at SiO
2Deposit one deck hundreds of is to the bottom gate thin film layer 21 (with PECVD method or other attainable methods) of several thousand dusts on the resilient coating 51, bottom gate thin film layer 21 material therefor can be polysilicon, Mg, Al, Mo or metal or alloy electrode materials such as MoW, MoAlMo, and general thickness is that hundreds of arrives several thousand dusts;
3. with the method photoetching bottom gate thin film layer 21 of dry etching or wet etching, middle part at device forms bottom gate thin film 23, the size of gate electrode is by concrete device application conditional decision (as the breadth length ratio of device, lithographic accuracy etc.), and the vertical view of device as shown in Figure 2 after the photoetching;
4. at SiO
2Deposit one deck hundreds of is to the grid electrode insulating layer 52 (with PECVD method or other attainable methods) of several thousand dusts again on resilient coating 51 and the bottom gate thin film 23, and grid electrode insulating layer 52 material therefor can be SiO
2, SiN
xOr SiO
2With SiN
xAlternating growth (decide according to concrete technological requirement, as the long one deck SiO of elder generation by concrete succession
2Long again layer of sin
x) insulating barrier;
5. chemico-mechanical polishing makes device surface smooth, and the thickness of the insulating barrier 52 that bottom gate thin film 23 keeps is above wanted to play insulating effect, is not less than the hundreds of dust;
6. on the grid electrode insulating layer 52 after the polishing, arrive the a-Si layer 61 of several thousand dusts with PECVD method growth hundreds of, and convert it into polysilicon membrane, this step is the core of whole TFT, the quality of the quality of polysilicon membrane directly has influence on this transistorized performance, the size of crystallite dimension in the polysilicon, intercrystalline density of defects, and surface state etc. all directly influence the performance such as mobility, on-off ratio of TFT.Realize that a-Si has multiple to the method that polysilicon transforms, topmost have two kinds: quasi-molecule laser annealing is (as document 1. " Advanced excimer laser crystallization technique; L.Mariucci; A.Pecora; et.al., Thin Solid Films, 2001; Vol.383, pp39 "; 2. the employing excimer laser heating a-Si film of being reported in " Effect of excimerlaser annealing on the structural and electrical properties of polycrystalline siliconthin-film transistors; C.T.Angelis and C.A.Dimitriadis; J.APPL.PHYS.; (1999); Vol.86; pp4600 ", annealing crystallization then), metal inducement is (as document 1. " Polycrystalline silicon prepared by metalinduced crystallization; Jong Hyun Choi; Do Young Kim; Seung Soo Kim, SeongJin Park, Jin Jang; Thin Solid Films; (2003), Vol.440, pp.1 "; 2. metal inducement (the MIC described in " Low-temperature crystallization of hydrogenated amorphous silicon induced by Nickelsilicide formation; Yunosuke KAWAZU; et al.; Jpn.J.Appl.Phys.; (1990), Vol.29, pp.2698 ", Metal Induced Crystallization), said method all can be met the polysilicon membrane of requirement;
7. carve the silicon island on the polysilicon layer that forms, make raceway groove 6, the requirement of photoetching is with step 3, and the vertical view of device as shown in Figure 3 after the single tube photoetching;
8. deposit one deck a-Si resilient coating 62 again on raceway groove 6 and the grid electrode insulating layer 52 that exposes, with PECVD method or other attainable methods, this layer general thickness can be tens to the hundreds of dust;
On a-Si resilient coating 62 deposit one deck grid electrode insulating layer 53 (preparation method and edge layer require same step 4), carve gate electrode connecting hole 25, directly carve to bottom gate thin film 23, purpose is when the gate electrode layer 22 of growth top, and top grid and bottom gate are linked together, and is convenient to add the control of grid voltage, the requirement of photoetching is with step 3, after the single tube photoetching vertical view of device as shown in Figure 4, the gate electrode connecting hole connects bottom gate thin film 23 and top gate electrode 24, and with raceway groove 6 insulation;
10. deposit one deck top gate electrode layer 22 after the photoetching, it can fill gate electrode connecting hole 25, and the requirement of this layer is with step 2;
11. photoetching forms the top gate electrode 24 of gate electrode, this layer photoetching is extremely important, be about to the requirement that the ion that carries out injects according to following, polysilicon membrane will be separated by intrinsic region and heavily doped region, and the ratio of their width will influence on-off ratio to a great extent, and (labor is seen document " High-PerformancePoly-Si TFTs With Multiple Selectively Doped Regions in The Active Layor; in-Cheol Lee; Juhn-Suk Yoo; Kee-Chan Park; Sang-Hoon Jung; Min-Koo Han, and Hyun-Jae Kim, Mat.Res.Soc.Symp.Proc.Vol.621,2000 Materials ResearchSociety), the requirement of photoetching is with step 3, and the vertical view of device as shown in Figure 5 after the photoetching;
12. further carry out photoetching, until being carved into a-Si resilient coating 62;
13. (doping type is decided according to the type of TFT in ion implantation doping, the P type mixes boron etc., the N type mixes phosphorus etc.), carry out hydrogenation treatment (according to different requirements after mixing, hydrogenation treatment also can be carried out in any step after the polysilicon membrane of having grown), purpose is the defect state density that reduces in the polysilicon membrane, to improve the performance of poly-Si TFT, as reducing threshold voltage, improve mobility, reduce OFF leakage current; The method of hydrogenation has a lot, mainly contains a. ion implantation, this method controllability and better repeatable, but cause lattice damage easily; B. plasma hydrogenation, method commonly used, but need the long period; C. plasma injects, newer hydrogenation, and hydrogenation time is short, helps enhancing productivity, and is fit to the preparation of large tracts of land display matrix;
14. depositing metal insulating barrier 54 is (with 53, because of the priority difference of growth, so appointed sequence number in addition; In Figure 10, both unifications are labeled as 53), preparation method and edge layer require with step 4;
15. photoetching is to raceway groove 6, thus formation drain contact hole, source, the requirement of photoetching is with step 3, and the vertical view of device is as shown in Figure 6 after the photoetching of single tube double grid;
16. metal 34 is leaked in the deposit source, the requirement of this layer is with step 2;
17. make source-drain electrode by lithography, the vertical view of device as shown in Figure 7 after the photoetching of single tube double grid;
18. packaging and testing.For single tube, to make the fairlead of gate electrode again by lithography, just can test,, can unify packaging and testing if this transistor is used for matrix.
Embodiment
Preparation embodiment 1:
1) at first using the PECVD method on the silicon substrate under 300 ℃ condition, obtains the SiO of 5000
2
2) on substrate, use LPCVD method (air pressure 0.3Torr, SiH
460sccm, speed is per second 25 ) (amorphous silicon is with SiH for the a-Si of precipitation 2000
4Decomposition obtains a-Si as source of the gas, and underlayer temperature is 200 ℃ during deposition, and base vacuum is 2 * 10
-4Pa, chamber pressure 80Pa) and carry out ion implantation doping (energy 45KeV, concentration 5 * 10
15Cm
-2), utilize plasma etch process (dry etching) photoetching figure as shown in Figure 2 to form bottom gate 23 afterwards;
3) precipitation 2500 SiNx as bottom gate insulating barrier, the growth of this layer film utilizes PECVD at SiH equally
4And NH
3Down growth of mixed atmosphere, underlayer temperature remains on 270 ℃, chamber pressure is 30Pa;
4) adopt the LPCVD technology to precipitate the a-Si film of 500 , condition is with step 2.And the a-Si film carried out BF
2Inject and mix.The energy that injects is for being 40～50KeV, and concentration is 4 * 10
15Cm
-2
5) deposition one layer thickness is the SiNx layer of 500 on the a-Si film, and as metallic spacer, the growth of this layer film utilizes PECVD at SiH equally
4And NH
3Down growth of mixed atmosphere, underlayer temperature remains on 290 ℃, chamber pressure is 30Pa;
6) sample is put into magnetic control platform growth one deck and induced metal, the thickness of this layer is 1nm, uses metal Ni as inducing metal, and underlayer temperature is 130 ℃ during growth, and base vacuum is 2 * 10
-4Pa, chamber pressure is 0.1Pa during sputter;
7) adopt the process conditions identical with the 3rd step then the layer thickness of growing on the sample be the SiNx layer of 500 as metal on diffusion layer;
8) utilize quick anneal oven annealing in process 10 hours under 520 ℃ temperature, pass to N therebetween
2As protective gas;
9) after annealing is finished, utilize plasma etch process (dry etching) at CF
4Carve diffusion layer SiNx on the metal under the atmosphere, then erode remaining metal Ni with watery hydrochloric acid, last using plasma etching technics is at CF
4Carve metallic spacer SiNx (,, influencing the performance of this layer insulating) under the atmosphere because there is the residual of metal Ni its inside though this layer can not carved as the grid electrode insulating layer, the polysilicon layer that stays, and photoetching figure as shown in Figure 3 forms the silicon island;
10) with method 2 deposit a-Si resilient coatings 50 ;
11) adopting the process conditions identical with the 3rd step layer thickness of then growing on sample is that the SiNx layer of 1000 is as the grid electrode insulating layer;
12) as this routine step 9 figure gate electrode connecting hole as shown in Figure 4 at quarter;
13) vacuum evaporation of aluminum 1500 , vacuum is 2 * 10
-7Pa;
14) as this routine step 9 figure as shown in Figure 5 at quarter as the top gate electrode;
15) carry out ion implantation doping as this routine step 4;
16) adopt that to go on foot the identical process conditions layer thickness of growing with this routine step 3 be that the SiNx layer of 3000 is as insulating barrier;
17) figure that carves as shown in Figure 6 as this routine step 9 leaks as the source
18) as step 13 evaporation of aluminum 3400 ;
19) carve as shown in Figure 7 figure as source-drain electrode as this routine step 9;
20) carve as shown in Figure 4 figure as the gate electrode wiring hole as this routine step 9;
21) test input-output characteristic curve etc.
Though the above form that the present invention's employing is given an example has been carried out concrete description, but one of ordinary skill in the art should be understood, these disclosed contents under the premise without departing from the spirit and scope of the present invention, can be done many changes just as an example on the details of each several part.
Claims (6)
1, the polycrystalline SiTFT of multiple-grid double channel structure, by insulating material substrate (1), in substrate in turn the growth SiO
2Resilient coating (51), grid electrode insulating layer (53), two the top gate electrodes (24) in grid electrode insulating layer (53), drain region (3), source region (4) are formed, and it is characterized in that: SiO
2Resilient coating (51) is gone up growth one deck grid electrode insulating layer (52), and bottom gate thin film (23) is arranged in grid electrode insulating layer (52), and bottom gate thin film (23) is connected by gate electrode connecting hole (25) with top gate electrode (24); Go up the raceway groove (6) that growth has polysilicon membrane to form at grid electrode insulating layer (52); The bottom of drain region (3) and source region (4) contacts with raceway groove (6).
2, the polycrystalline SiTFT of multiple-grid double channel structure as claimed in claim 1, it is characterized in that: gate electrode (23) is when being added with voltage, inversion layer appears in the surface of pressing close to go up insulating barrier (53) and following insulating barrier (52) at raceway groove (6) simultaneously, realize two paths of electric current, i.e. the double channel structure.
3, the polycrystalline SiTFT of multiple-grid double channel structure as claimed in claim 1 or 2 is characterized in that: also growth has a-Si resilient coating (62) on raceway groove (6).
4, the polycrystalline SiTFT of multiple-grid double channel structure as claimed in claim 1 or 2 is characterized in that: insulating material substrate (1) is glass, quartz, silicon chip or flexible substrate material.
5, the polycrystalline SiTFT of multiple-grid double channel structure as claimed in claim 1 or 2, it is characterized in that: bottom gate thin film (23), top gate electrode (24), gate electrode connecting hole (25), drain region (3), source region (4) material therefor are polysilicon, Mg, Al, Mo metal or MoW, MoAlMo alloy electrode material, and the thickness of layer is that hundreds of arrives several thousand dusts.
6, the polycrystalline SiTFT of multiple-grid double channel structure as claimed in claim 1 or 2 is characterized in that: grid electrode insulating layer (52), (53), (54) material therefor are SiO
2, SiN
xOr SiO
2With SiN
xAlternating growth, thickness are that hundreds of arrives several thousand dusts.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1866540B (en) * | 2005-05-20 | 2012-06-06 | 株式会社半导体能源研究所 | Semiconductor device and manufacturing method thereof |
| CN102709316A (en) * | 2012-05-30 | 2012-10-03 | 北京大学 | Three-dimensional (3D) oxide semiconductor thin film transistor and preparation method thereof |
| CN104952879A (en) * | 2015-05-05 | 2015-09-30 | 深圳市华星光电技术有限公司 | Dual-gate TFT (thin-film transistor) substrate structure using COA (color filter on array) technique |
| CN105633136A (en) * | 2016-01-05 | 2016-06-01 | 京东方科技集团股份有限公司 | Thin-film transistor and drive method thereof, array substrate and display device |
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| JPS6054470B2 (en) * | 1978-08-15 | 1985-11-30 | 松下電工株式会社 | How to manufacture downpipes |
| KR100372820B1 (en) * | 1999-06-29 | 2003-02-20 | 주식회사 하이닉스반도체 | Double silicon mosfet and method of manufacturing the same |
| CN101800243B (en) * | 2000-03-17 | 2012-11-07 | 通用半导体公司 | Manufacture method of trench dmos transistor having a double gate structure |
| US6383904B1 (en) * | 2000-10-16 | 2002-05-07 | Advanced Micro Devices, Inc. | Fabrication of self-aligned front gate and back gate of a field effect transistor in semiconductor on insulator |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1866540B (en) * | 2005-05-20 | 2012-06-06 | 株式会社半导体能源研究所 | Semiconductor device and manufacturing method thereof |
| CN102646600B (en) * | 2005-05-20 | 2015-01-14 | 株式会社半导体能源研究所 | Semiconductor device and manufacturing method thereof |
| CN102709316A (en) * | 2012-05-30 | 2012-10-03 | 北京大学 | Three-dimensional (3D) oxide semiconductor thin film transistor and preparation method thereof |
| CN102709316B (en) * | 2012-05-30 | 2015-02-18 | 京东方科技集团股份有限公司 | Three-dimensional (3D) oxide semiconductor thin film transistor and preparation method thereof |
| CN104952879A (en) * | 2015-05-05 | 2015-09-30 | 深圳市华星光电技术有限公司 | Dual-gate TFT (thin-film transistor) substrate structure using COA (color filter on array) technique |
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| CN105633136A (en) * | 2016-01-05 | 2016-06-01 | 京东方科技集团股份有限公司 | Thin-film transistor and drive method thereof, array substrate and display device |
| WO2017118103A1 (en) * | 2016-01-05 | 2017-07-13 | 京东方科技集团股份有限公司 | Thin-film transistor, driving method therefor, array substrate, and display device |
| US10236393B2 (en) | 2016-01-05 | 2019-03-19 | Boe Technology Group Co., Ltd. | TFT, method for driving the same, array substrate and display device |
| WO2020019606A1 (en) * | 2018-07-24 | 2020-01-30 | 深圳市华星光电半导体显示技术有限公司 | Tft array substrate and manufacturing method thereof |
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