CN1591318A - Binary complement and non-symbolic quantity format data multiplier - Google Patents
Binary complement and non-symbolic quantity format data multiplier Download PDFInfo
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- CN1591318A CN1591318A CN 03158108 CN03158108A CN1591318A CN 1591318 A CN1591318 A CN 1591318A CN 03158108 CN03158108 CN 03158108 CN 03158108 A CN03158108 A CN 03158108A CN 1591318 A CN1591318 A CN 1591318A
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Abstract
The present invention uses a two's complement multiplier and combines it with an additional circuit element to provide a multiplier. Said multiplier can make two operands represented by any combination of two's complement (with sign) or signless quantity format be multiplied, and is compared with the multiplier of two operands represented by identical format, and the size of the multiplier can not be increased. Said invention can provide independent reverse control for left column of multiplier array and partial product elements in bottom end line and can control to that the carry signal of carry propagation adder executing partial product final addition is produced to implement its addition capacity.
Description
Technical field
The present invention relates to be used to carry out tape symbol (two's complement) multiplication, no symbol weight multiplication, and a circuit that is tape symbol (two's complement form) and another for the multiplication of two operands of no symbol weight form.
Background technology
Many DSP algorithms need not have the multiplication of 32 of symbols and 16 of tape symbols.This operation can use 32 multipliers to carry out, and still, the high power of 32 multipliers and area cost make and comprise that on chip 32 multipliers are irrational.Therefore, this operate typical ground is carried out on 16 multipliers that are used for every other 16 bit DSPs calculating.In order except that standard 16 bit DSPs calculate, also to carry out this operation, 16 multipliers must all be that the number of no symbol weight and two's complement form multiplies each other with two, and are that two's complement form and another are that two operands of no symbol weight form multiply each other with one.
The multiplication of the operand of two's complement and no symbol weight form is also required by some application, Video signal processing for example, wherein the luminance component of vision signal is represented with no symbol weight form, and with the multiplication of representing with the two's complement form.
Multiplier as known in the art or accept the no sign multiplication device of two no symbolic operands, or accept the signed multiplication device of two tape symbol operands.No symbolic operand has 0～2
n-1 value, wherein n is the length of the position of operand.Tape symbol two's complement operand has-2
N-1～2
N-1-1 value.
The commonsense method of structural belt sign multiplication device comprises that using the Baugh-Wooley method will not have the character array multiplier converts Binary Complement Array Multiplier to.This multiplier is still accepted two n positional operands, and changes and increase certain logic in multiplier, represents the situation of negative value to handle one or two operand.This logic comprises the position supplement with the product of input operand or input operand, and additional totalizer is to be added to constant in the final product.
Initial Baugh-Wooley method comprises increases by three full adders (each receives three, and produces summation position and carry digit).This method is than the technology that had before been proposed by Pezaris and to need to receive and produce the other technologies of another kind of form unit of full adder of negative summation of weighted bits simple.Thereby a kind of modification of Baugh-Wooley method can reduce the length that the maximum column height reduces critical path, is preferred therefore.
Any no symbol n figure place can be expressed as tape symbol two's complement n+1 figure place as highest significant position by increasing by zero.Any tape symbol n figure place can be expressed as tape symbol n+1 figure place by one of sign extended.The commonsense method that the operand that is used for mixing multiplies each other, otherwise wherein multiplier be signed and multiplicand be signless or, be that two operands are extended to the n+1 position and use signed n+1 to take advantage of the multiplier of n+1, as shown in fig. 1, wherein by register 22 and 23 16 positional operand A and the B that supply with, have highest significant position (MSB), and in 17 * 17 multipliers 10, multiply each other, produce 34 product by parts 20 and 21 appointments.Then, this product shortens into 2n (32) position.Therefore, 17 take advantage of 17 signed multiplication device to be used for two 16 number is multiplied each other, and one is signed and another is signless, and product shortens to 32.
But, use bigger (n+1) position multiplier to increase the power consumption of multiplier.And it causes the increase by the critical path of multiplier, and this may influence the frequency of operation of chip.Square being directly proportional of the area of array multiplier and multiplier width.Worst case power also with square being directly proportional of multiplier width, and delay and the linear ratio of width by array multiplier.Therefore, use (n+1) position multiplier to replace n position multiplier to cause power to increase 2/n (((n+1) approximately relatively
2-n
2)/n
2=2/n+1/n
2) and postpone to increase relatively 1/n (((n+1)-n)/n=1/n).Detailed simulation can illustrate, use 17 multipliers replace 16 multipliers can cause power consumption increase up to 12% and critical path delay increase up to 8%.
Therefore, need a kind of multiplier, it can multiply each other the number of two's complement and no symbol weight form, comprises the combination in any of two kinds of forms, compares with the multiplier that is used for tape symbol or does not have a symbolic operand, and power overhead is few, and size has increase slightly.
Summary of the invention
The present invention relates to be used to carry out tape symbol (two's complement) multiplication, no symbol weight multiplication, and one be another circuit for the multiplication of two operands of no symbol weight form of two's complement form.
One of the present invention the symbol that provides partial product element, this element controllably to reverse its partial product is provided.
Of the present invention another is characterised in that the form of operation response number produces the n that will be increased to product, the position in (n+1) individual and 2n position.
Description of drawings
Fig. 1 shows total figure of prior art multiplier.
The mode that Fig. 2 partly illustrates with partial illustration shows according to multiplier of the present invention.
The mode that Fig. 3 partly illustrates with partial illustration shows first embodiment of the present invention.
The expression and the truth table of the element of Fig. 4 displayed map 3 embodiments.
The mode that Fig. 5 partly illustrates with partial illustration shows second embodiment of the present invention.
The expression and the truth table of the element of Fig. 6 displayed map 5 embodiments.
The expression and the truth table of the add ons of Fig. 7 displayed map 5 embodiments.
Embodiment
The principle of work of the parts that the operand of representing with two's complement and no symbol weight can be multiplied each other is based on following Fundamentals of Mathematics.
Hereinafter, term " tape symbol operand " will be used to refer to the operand that provides with the two's complement form, and term " no symbolic operand " will be used to refer to the operand that provides with no symbol weight form.Make x power of p (x) expression 2, x more than or equal to 0 (for example, p (0)=1, p (1)=2, p (2)=4, or the like).Make a[n] ..., a[1] and do not have n position, the wherein a[n of the unsigned number A of symbol weight form for using the normal binary representation to represent] be highest significant position.
The numerical value of A equals:
A＝a[1]p(0)+a[2]p(1)+…+a[n]p(n-1)
＝∑
i＝1，…，n(a[i]p(i-1))。
Make b[n] ..., b[1] and represent n position, the wherein b[n of (representing) signed number B for using normal binary complementary binary representation with the two's complement form] be highest significant position.The numerical value of B equals:
B＝b[1]p(0)+b[2]p(1)+…+b[n-1]p(n-2)-b[n]p(n-1)
＝-b[n]p(n-1)+∑
i＝1，…，n-1(b[i]p(i-1))
The product of A and B equals:
AB＝-b[n]p(n-1)(∑
i＝1，…，n(a[i]p(i-1)))
+(∑
i＝1，…，n-1(b[i]p(i-1)))(∑
i＝1，…，n(a[i]p(i-1)))
＝∑
i＝1，…，n(-b[n]a[i]p(n-2+i))+∑
j＝1，…，n-1(∑
i＝1，…，n(a[i]b[j]p(i+j-2)))。
In order to use simple adder unit to realize multiplication algorithm effectively, must there be subtraction in the superincumbent expression formula.Do not have subtraction in order only to have addition, we use b[n] a[i] two's complement, it equals (1-b[n] a[i]), and writes product AB with following form:
AB＝∑
i＝1，…，n((1-b[n]a[i])p(n-2+i))-∑
i＝1，…，n(p(n-2+i))+
∑
i＝1，…，n(∑
i＝1，…，n-1(a[i]b[j]p(i+j-2)))
The discipline ∑
I=1 ..., n(p (n-2+i)) equals: p (n-1)+p (n)+... + p (2n-2)
＝p(2n-1)-1-(p(n-1)-1)
＝p(2n-1)-p(n-1)
Last formula, the situation when being tape symbol for A for no symbol B is:
(1)AB＝∑
i＝1，…，n-1(∑
j＝1，…n-1(a[i]b[j]p(i+j-2))) (1a)
+∑
j＝1，…，n-1(a[n]b[j]p(n-2+j)) (1b)
+∑
i＝1，…，n-1((1-a[i]b[n])p(n-2+i)) (1c)
+(1-a[n]b[n])p(2n-2) (1d)
+p(n-1) (1e)
-p(2n-1) (1f)
Similarly analyze explanation, if A is a tape symbol and B is no symbol, so:
(2)AB＝∑
i＝1，…，n-1(∑
j＝1…，n-1(a[i]b[j]p(i+j-2))) (2a)
+∑
j＝1…，n-1((1-a[n]b[j])p(n-2+j)) (2b)
+∑
i＝1，…，n-1(a[i]b[n]p(n-2+i)) (2c)
+(1-a[n]b[n])p(2n-2) (2d)
+p(n-1) (2e)
-p(2n-1) (2f)
When operand A and B were tape symbol, we had:
(3)AB＝∑
i＝1，…，n-1(∑
i＝1，…，n-1(a[i]b[j]p(i+j-2))) (3a)
+∑
i＝1，…，n-1((1-a[n]b[j])p(n-2+j)) (3b)
+∑
i＝1，…，n-1((1-a[i]b[n])p(n-2+i)) (3c)
+a[n]b[n]p(2n-2) (3d)
+p(n) (3e)
-p(2n-1) (3f)
And when operand A and B were no symbol, we had at last:
(4)AB＝∑
i＝1，…，n(∑
i＝1，…，n(a[i]b[j]p(i+j-2)))
＝∑
i＝1，…，n-1(∑
i＝1，…，n-1(a[i]b[j]p(i+j-2))) (4a)
+∑
i＝1，…，n-1(a[n]b[j]p(n-2+j)) (4b)
+∑
i＝1，…，n-1(a[i]b[n]p(n-2+i)) (4c)
+a[n]b[n]p(2n-2) (4d)
With reference now to Fig. 2,, it describes two operand wise multiplication and the array of the single bit position product that obtains.Two operand A and B show schematically that at the top of figure wherein concerning this figure, each can be tape symbol or signless for operand A and B.The array of partial product comprises main array 10 and three special arrays-20,30 and 40.
The array 20 that is called a MSB array comprise among the A first with B in the partial product of position of (except that MSB), i.e. A[n] B[j], the highest significant position of index [n] expression operand wherein, and j is the index of 1～n-1.The array 30 that is called the 2nd MSB array comprise among the B first with A in the appropriate section product of position of (except that MSB), i.e. B[n] A[j], the highest significant position of index [n] expression operand wherein, and j is the index of 1～n-1.The array 40 that is called the 3rd MSB array comprises the product of two MSB, i.e. A[n] B[n].In the bottom, total product is shown in array 80.On array 80, increase position 50,60 as described below and 70 is to handle the tape symbol operand.
First (1a) in the top formula (1) is corresponding to not comprising array 20, the addition of all partial products in 30 and 40 the piece 10, promptly do not consider those (arrays 20 and 40) of multiplying each other corresponding to the position of the highest significant position of operand A and operand B, and corresponding to all partial products of highest significant position with operand A those (arrays 30 and 40) that multiply each other of operand B.Noting, is tape symbol if not A for no symbol B, and we will handle A is tape symbol and B is a no symbol (2a), and A and B are tape symbol (3a), and perhaps A and B are no symbol (4a), and this first (1a) maintenance is identical.This of expression formula is identical with the similar expression formula that occurs in standard multiplication device (wherein two operands are all represented with the two's complement form or all represented with no symbol weight form).This 1a can use in the prior art multiplier employed any traditional structure to realize.The 3rd (1c) in the top formula (1) corresponding to the multiply each other addition of (array 30) the corresponding product of inversion section of the position of the highest significant position of operand B and operand A, suppose that operand A is a tape symbol for no symbol operand B.If operand A is a tape symbol and operand B is no symbol, the multiplying each other of corresponding second (2b) in (2) so corresponding to the position of the highest significant position of operand A and operand B.These (1c and 2b) are similar to the expression formula that occurs in normal binary complement code Baugh-Wooley multiplier.
A main difference is, in algorithm disclosed by the invention, one in two groups of partial products 20 and 30 must be inverted, when an operand is that tape symbol and another operand are during for no symbol.In order to carry out two all is the multiplication of signed operand, partial product 20 and 30 all will be inverted (3b, 3c), partial product 40 (it multiplies each other corresponding to the highest significant position of the highest significant position of A and B) nonreversible (3d) simultaneously.At last, all be the multiplication of signless operand in order to carry out two, partial product is all nonreversible.Which partial product eyes front, the truth table among Fig. 4 C and the 7A specify to be inverted.Described result passes through to be element 20 according to the present invention, 30 and 40 partial product generator is equipped with the device that can independently control counter-rotating, and be provided for (based on the multiplier control input of the required multiplication type of indication) and produce three independently logics of reverse control signal: one is used for partial product 20, one is used for partial product 30, and one is used for element 40, carries out.
Item (1e) in the top formula (1) (p (n-1)) is corresponding in that n position (60) adds ' 1 ' to finant product from the right side.This is different from two's complement Baugh-Wooley multiplier, and the Baugh-Wooley multiplier need be in that n+1 position (70) adds ' 1 ' to finant product (that is, adding p (n) rather than p (n-1)) from the right side.
Two all is that the multiplication of the operand of two's complement form still need be in that n+1 position (70) adds ' 1 ' to finant product from the right side.
At last, all be the multiplication of the operand of no symbol weight form in order to carry out two, need additionally not add ' 1 ' and arrive product in n or n+1 position.This result according to the present invention by providing a kind of device to realize, this device (being called a generation device 18 in Fig. 3) depends on the multiplier control input of the required multiplication type of indication, controllably produces in n and (n+1) individual position and treats that (by the position feeder apparatus that can conveniently locate) is added to the position of finant product.
Item (1f) in the top formula (1) (p (2n-1)) is corresponding to deducting p (2n-1).Similar terms in it and the two's complement Baugh-Wooley multiplier is identical.Deduct this highest significant position (50) that is equivalent in 2n position result and add ' 1 ' to finant product, it is interpreted as having the tape symbol two of negative weights.When two of multiplier operations all are the operand of no symbol weight form, and only have at this moment, ' 1 ' need be forbidden to add this.This result realizes that by the position feeder apparatus this feeder apparatus depends on multiplier and controllably adds ' 1 ' in 2n position result's highest significant position (50).
Fig. 3 shows the preferred realization of using the inventive method integrated circuit that same hardware multiplies each other the number of two's complement and no symbol weight form.
The multiplier hardware of first preferred embodiment is by comprising first according to the present invention, the second and the 3rd MSB array 20,30 and 40 partial product generator array 90, partial product is simplified network 17, net result totalizer 19, position, counter-rotating controll block 15, the 2n positions (tape symbol) generator 16, and position, (n+1)-n position generator (mixed format position generator 18) is formed.This multiplier has two original inputs in n position that are used for input operand A and B, is used for the original output in 2n position (61) of multiplication result, and the control that the form of input operand A and B is encoded is imported 12.Control input 12 is encoded into four types multiplying order: 1) operand A and B are used as the number of representing with no symbol weight form; 2) operand A is used as the number of representing with the two's complement form, and operand B is used as the number of representing with no symbol weight form; 3) operand B is used as the number of representing with the two's complement form, and operand A is used as the number of representing with no symbol weight form; And 4) operand A and B are used as the number of representing with the two's complement form.Any coding of this information can be used for control input 12.Can be by random some that omit in four kinds of combinations of system designer.
Partial product generator array 90 produces the individual partial product of n^2 (n square) of Ai*Bj forms, and i and j are 1～n.Each partial product is produced by partial product generator unit 2 or 3.
All partial product generator unit, except those in left column (left column is to produce A[n] * B[j] row of partial product of form, A[n wherein] be the highest significant position of operand A, and j is the index of 1～n, represented as array among Fig. 2 20 and 40) and those on footline (footline is to produce A[j] * B[n] row of partial product of form, B[n wherein] be the highest significant position of operand B, and j is the index of 1～n, represented as array among Fig. 2 30 and 40), use the AND door as shown in Fig. 4 a to realize.' 2 ' are appointed as in these partial product generator unit in Fig. 3, and are grouped in the subarray 10 among Fig. 3.
By convention, represented the arranging of partly illustrating with partial illustration among multiplier such as Fig. 2 of form.The order that one skilled in the art will appreciate that multiplication can be exchanged, and array layout is preferred rather than sin qua non.Therefore, in claims, term " left column " will refer to those partial products (group 20 and 40 among Fig. 2) that multiply each other corresponding to the highest significant position of operand A and operand B, and term " footline " will refer to those partial products (group 30 and 40 among Fig. 2) that multiply each other corresponding to highest significant position and the operand A of operand B.And term " a MSB array " refers to the array 20 among Fig. 2, and " the 2nd MSB array " refers to the array 30 among Fig. 2, and " the 3rd MSB array " refers to the array 40 among Fig. 2; (and the respective sets in other embodiments or array).
The partial product generator unit of getting rid of in the paragraph in front (those in array left column and the footline) is appointed as 3 in Fig. 3.Being implemented among Fig. 4 b of they shows.Partial product generator unit 3 has two operand input a and b and counter-rotating control input i.The counter-rotating control input of these unit is connected to the counter-rotating controll block 15 among Fig. 3.The truth table of the form display part product generator 3 among Fig. 4 b, and gate leve figure shows the gate leve realization of suggestion.Also can use in accordance with any other door or the transistor of truth table and realize.
Fig. 4 c shows the truth table and the sketch map of counter-rotating controll block 15.Its input is connected to the control input 12 of multiplier, and its output is connected to the input i of the left column of array among Fig. 3 and the partial product generator unit 3 in the footline.The output 21 partial product generator unit that are connected on the left column are except partial product generator unit 40.The output 22 partial product generator unit 40 that are connected in partial product generator array 90 lower left corners.The output 23 partial product generator unit 30 that are connected on the footline are except partial product generator unit 40.Truth table among Fig. 4 c shows the realization of counter-rotating controll block 15.The specific implementation of the door of counter-rotating controll block depends on the coding of control input 12.Can use and realize truth table among Fig. 4 c, the door of any combination that realizes easily by those skilled in the art.Those skilled in the art can easily revise counter-rotating controll block 15 and have the partial product generator unit 3 of counter-rotating control, when the reverse control signal 21,22 or 23 that uses inverted version (all in them or arbitrarily).
Fig. 4 d shows the truth table and the sketch map of the position generator 16 of 2n position.Its input is connected to the control input 12 of multiplier, and its output 50 is connected to the input of the highest significant position position of totalizer 19.Truth table among Fig. 4 d shows the realization of the position generator 16 of 2n position.The specific implementation of the door of circuit depends on the coding of control input 12.Can use the door of realizing any combination of truth table among Fig. 4 d.
The truth table and the sketch map of the position generator 18 of Fig. 4 e explanation (n+1)-n position.Its input is connected to the control input 12 of multiplier, and its output 60 and 70 is connected to the input of simplifying network 17.Output 70 is connected to the input that (begins to count) position, (n+1) position from the right side from the least significant bit (LSB) position of simplifying network 17.Output 60 is connected to the input that (begins to count) position, n position from the right side from the least significant bit (LSB) position of simplifying network 17.Truth table among Fig. 4 e shows the realization of the position generator 18 of (n+1)-n position.The specific implementation of the door of circuit depends on the coding of control input 12 among Fig. 2.Can use the door of realizing any combination of truth table among Fig. 4 e.
Partial product among Fig. 3 is simplified the simplification tree that network 17 can be embodied as the well-known any traditional prior art of multiplier those skilled in the art.Depend on realization, it may have the many outputs (shown in the line 53 of Fig. 3) that least significant bit (LSB) is put that are arranged in that do not need to enter final totalizer, and the many outputs (51-52 is represented by number) that the finant product highest significant position is put that are positioned at that are connected to final totalizer input.
If the consideration cycle is required, the multiplier of Fig. 3 can become two or more multistage by flowing water.In the streamline of multiplier was realized, latch was inserted in that to simplify network 17 inner and at the output 51-52 place of simplifying network.These latchs in Fig. 3 such as dotted line 17 ' and 54 signal show.The position generator 16 and 18 of 2n and (n+1)-n position is therefore flowing water also, makes output delay proper number cycle of these pieces.Use two groups of latchs, multiplier is divided into three grades, makes three groups of operands to handle simultaneously.Can use the well-known any streamline mechanism of those skilled in the art.Concerning claims, latch, delay circuit and control circuit will be called flow-line equipment jointly.
Depend on required functionally, the multiplier among Fig. 3 can have many additional controls inputs, is used for controlling the additional functional of the well-known multiplier of DSP algorithm field technician, for example has the multiplication of saturation degree, has the multiplication of displacement etc.Disclosed method is irrelevant among these features and the present invention.Those skilled in the art can easily combine disclosed method in the functional and this patent that adds.
Fig. 5 shows the optional realization of the multiplier integrated circuit of invention.There is not the element of variation with designated with the embodiment of Fig. 3.In addition, in the reference number presentation graphs 6 among Fig. 5 or the element of appointment in the text.According to the multiplier hardware of the embodiment of the present invention by the partial product generator array 90 that is organized into array multiplier, net result totalizer 19, the position generator 16 of counter-rotating controll block 15, the 2n positions, and carry generator 18 is formed.This multiplier has two the n positions input that is used for input operand A and B, is used for the 2n position output (Fig. 3 61) of multiplication result, and with the control input 12 of the form coding of input operand A and B.Control input 12 is encoded into as four types multiplying order among Fig. 3.
Partial product generator array 90 produces the n of Ai*Bj form
2(n square) individual partial product, i and j are 1～n.Each partial product produces by one in partial product generator unit 2,3,4,5 or 6.The input and output of partial product generator connect according to the well-known array multiplier traditional scheme of those skilled in the art.In first trip, the output of unit generator is delivered to next line by line 71.On second row, the output of unit generator 3 is transmitted by line 72, and carry digit transmits by line 73.For the third line and row subsequently, the output of unit generator 4 is by line 74,76,78 transmission such as grade, and carry digit is by line 75,77,79 transmission such as grade similarly.Use different generator 2,3 and 4 optional, but save the space.
All partial product generator unit except those and on footline those in left column, (are the unit 2 among Fig. 5,3 and 4), multiplier unit according to the well-known conventional array multipliers of those skilled in the art realizes that an one example shows among 6b and the 6c at Fig. 6 a.In the subarray (the main array of partial product generator) 10 of these unit packet in Fig. 5.AND door 91. these partial product generator unit that unit on first row is embodied as shown in Fig. 6 a are appointed as 2 in Fig. 5.Unit 3 on second row is embodied as the half adder that has AND door 91 in an one input, as shown in Fig. 6 b.Unit 4 on the residue row of Fig. 5 neutron array 10 is embodied as the full adder that has AND door 91 in an one input, as shown in Fig. 6 c.Fig. 6 a, the circuit among 6b and the 6c is traditional, and is well-known to those skilled in the art.
Specify with numeral 5 in Fig. 5 partial product generator unit in array 90 left columns (a MSB array 20 ').Being implemented among Fig. 6 d of they shows.Partial product generator unit 5 has two operand input a and b and counter-rotating control input i.The counter-rotating control input of these unit is connected to the output 21 of the counter-rotating controll block 15 among Fig. 5.Figure among Fig. 6 d shows the gate leve realization.Also can use in accordance with any door or the transistor of truth table among Fig. 4 b and realize.
Except also being arranged in (array 90 lower left corners) the partial product generator unit (the 3rd MSB array 40 ') on the left column, specify with numeral 6 in Fig. 5 partial product generator unit in array 90 footlines (the 2nd MSB array 30 ').Being implemented among Fig. 6 e of they shows.Partial product generator unit 6 is similar to the full adder that has the AND door in an one input shown in Fig. 6 c.In addition, partial product generator 6 has the counter-rotating control input i of control section product counter-rotating, as shown in Fig. 6 e.The counter-rotating control input of unit 6 is connected to the output 23 of the counter-rotating controll block 15 among Fig. 5.Can use any other or the transistor of realizing the identity logic function to realize replacing circuit among Fig. 6 e.
Fig. 7 a shows the truth table and the realization of counter-rotating controll block 15, its with Fig. 3 in identical.Its input is connected to the control input 12 of multiplier, and its output is connected to the input i of the left column of array among Fig. 5 and the partial product generator unit in the footline.The output 21 partial product generator unit that are connected on the left column, except the partial product generator unit 40 ' on left column and footline (produce partial product A[n] * B[n] the unit, A[n wherein] be highest significant position and the B[n of operand A] be the highest significant position of operand B).The output 22 partial product generator unit 40 ' that are connected in array 90 lower left corners.The output 23 partial product generator unit that are connected on the footline are except partial product generator unit 40 '.Truth table among Fig. 7 a shows the realization of counter-rotating controll block 15.The specific implementation of the door of counter-rotating controll block depends on the coding of control input 12.Can use the door of realizing any combination of truth table among Fig. 7 a.How revising counter-rotating controll block 15 and have the partial product generator unit 3 of counter-rotating control, when the reverse control signal 21,22 or 23 that uses inverted version (all in them or arbitrarily), should be obvious to those skilled in the art.
Fig. 7 b shows the truth table and the realization of the position generator 16 of 2n position.Its input is connected to the control input 12 of multiplier, and its output 50 is connected to the input of the highest significant position position of totalizer 19.Truth table among Fig. 7 b shows the realization of the position generator 16 of 2n position.The specific implementation of the door of circuit depends on the coding of control input 12.Can use the door of realizing any combination of truth table among Fig. 7 b.
Fig. 7 c shows the truth table and the realization of carry generator 58.Its input 85 is connected to the summation output of the partial product generator unit in Fig. 5 lower right corner.This is to produce partial product A[n] * B[n] the unit, A[n wherein] be the least significant bit (LSB) of operand A, and B[n] be the highest significant position of operand B.Other inputs of piece 58 are connected to the control input 12 of multiplier.
The output 60 of piece 58 is connected to the output of multiplier, from the position n that least significant bit (LSB) begins to count.Output 70 is connected to the carry input of totalizer 19.Truth table among Fig. 7 c shows the realization of carry generator 58.The specific implementation of the door of circuit depends on the coding of control input 12.Can use the door of realizing any combination of truth table among Fig. 7 c.
Depend on the demand in cycle, the multiplier among Fig. 5 can become two or more multistage by flowing water.In the streamline of multiplier was realized, latch was inserted in the input of totalizer 19, and/or array 90 inside.These latchs in Fig. 5 such as dotted line 92 and 92 ' signal show.2n and carry generator 16 and 58 be therefore flowing water also, makes output delay proper number cycle of these pieces.Can use the well-known any streamline mechanism of those skilled in the art.
Depend on required functionally, the multiplier among Fig. 5 can have many additional controls inputs, is used for controlling the additional functional of the well-known multiplier of DSP algorithm field technician, for example has the multiplication of saturation degree, has the multiplication of displacement etc.Disclosed method is irrelevant among these features and the present invention.Those skilled in the art can easily combine disclosed method in the functional and this patent that adds.
One skilled in the art will know that the embodiment of example comprises compressed tree shown in Fig. 3, therefore the embodiment than Fig. 5 is fast for the multiplication of high width.On the other hand, array multiplier, for example the embodiment of Fig. 5 is more regular more than the embodiment of Fig. 3, has shorter line in the layout and has lower power consumption.The embodiment of Fig. 3 is preferred for high width multiplication, and the embodiment of Fig. 5 is preferred for low width multiplication.
Though the present invention describes according to a pair of preferred embodiment, those skilled in the art will recognize that, put into practice in essence of claims that the present invention can be below and the various version in the scope.
Claims (17)
1. a multiplier is suitable for operating the operand of representing with any combination of two's complement and no symbol weight form, comprising:
One group of partial product generator, the main array that comprises partial product generator parts, the one MSB array, the 2nd MSB array and the 3rd MSB array, wherein said the one the second and the 3rd MSB array in parts comprise and be used to respond the signal of self reversal control assembly and be reversed in the controllable device of the partial product that the there produced;
The tape symbol position that is connected to described counter-rotating control assembly produces circuit;
The mixed format position that is connected to described counter-rotating control assembly produces circuit; And
Be used for producing the net result totalizer of product from described partial product group.
2. according to the multiplier of claim 1, also comprise being used to make up the device of described partial product group with the input that is formed into described net result totalizer.
3. according to the multiplier of claim 1, also comprise the device of accepting two n position inputs, described thus multiplier can be operated two n position unsigned numbers, two n position twos, and a n position unsigned number and a n position two.
4. according to the multiplier of claim 2, the described counter-rotating control assembly that wherein responds the input format signal of assigned operation number format comprises circuit, to produce a MSB array, the control signal of the 2nd MSB array and the 3rd MSB array in described left column and footline, make and when only described first operand is for tape symbol, to reverse described first and the content of the 3rd MSB array, when only described second operand is for tape symbol, reverse described second and the content of the 3rd MSB array, and when reverse during all for the tape symbol content of the described first and second MSB arrays of described first and second operands.
5. according to the multiplier of claim 4, the described tape symbol position that wherein responds the described input format signal of assigned operation number format produces circuit and comprises circuit, be used for the n position that (a) is added to logical value described multiplier output, and (b) when two operands all are the two's complement form, logical value is added to (n+1) position of output.
6. according to the multiplier of claim 5, wherein said mixed format position produces circuit and comprises the circuit that is used for logical value is added to the 2n position of output.
7. according to the multiplier of claim 1, also comprise flow-line equipment, at least one level is early operated later a pair of operand thus, and at least one later first pair of operand of level operation.
8. according to the multiplier of claim 3, also comprise flow-line equipment, at least one level is early operated later a pair of operand thus, and at least one later first pair of operand of level operation.
9. according to the multiplier of claim 4, also comprise flow-line equipment, at least one level is early operated later a pair of operand thus, and at least one later first pair of operand of level operation.
10. according to the multiplier of claim 5, also comprise flow-line equipment, at least one level is early operated later a pair of operand thus, and at least one later first pair of operand of level operation.
11. a multiplier is suitable for operating the operand of representing with any combination of two's complement and no symbol weight form, comprising:
Partial product with one group of partial product generator produces and the simplification parts, wherein at least some product generators comprise the device that is used to produce carry digit, these parts comprise one group of partial product production part, wherein on the left column and the parts on the footline comprise and be used to respond the signal of self reversal control assembly and be reversed in the controllable device of the partial product that produced of there;
Be connected on the left column and footline on the counter-rotating control assembly of described parts;
The tape symbol position produces circuit;
The mixed format position produces circuit; And
The net result totalizer.
12. a multiplier comprises being used to produce one group of partial product of two operands and being used to make up described partial product group to form the device of finant product that this multiplier also comprises:
The counter-rotating control device is used for inversion section product A[n controllably] B[j], A[n] and B[n] and A[j] B[n], the highest significant position of index [n] assigned operation number wherein, and j is the index of 1～n-1; And
Be used for controllably adding the device of ' 1 ' in (n+1) position and the n position in the 2n position of product.
13. according to the multiplier of claim 12, also comprise the device of accepting two n position inputs, described thus multiplier can be operated two n position unsigned numbers, two n position twos, and a n position unsigned number and a n position two.
14. multiplier according to claim 13, the input format signal of wherein said counter-rotating control device response assigned operation number format, and comprise that circuit comprises A[n to produce] B[j] a MSB array, the highest significant position of index [n] assigned operation number wherein, and j is the index of 1～n-1, comprise A[j] B[n] the 2nd MSB array and comprise A[n] B[n] the control signal of the 3rd MSB array, be used for when only described first operand is for tape symbol, reversing described first and the content of the 3rd MSB array, when only described second operand is for tape symbol, reverse described second and the content of the 3rd MSB array, and when reverse during all for the tape symbol content of the described first and second MSB arrays of described first and second operands.
15. according to the multiplier of claim 12, also comprise flow-line equipment, at least one level is early operated later a pair of operand thus, and at least one later first pair of operand of level operation.
16. according to the multiplier of claim 13, also comprise flow-line equipment, at least one level is early operated later a pair of operand thus, and at least one later first pair of operand of level operation.
17. according to the multiplier of claim 14, also comprise flow-line equipment, at least one level is early operated later a pair of operand thus, and at least one later first pair of operand of level operation.
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|---|---|---|---|
| CN 03158108 CN1591318A (en) | 2003-09-03 | 2003-09-03 | Binary complement and non-symbolic quantity format data multiplier |
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|---|---|---|---|
| CN 03158108 CN1591318A (en) | 2003-09-03 | 2003-09-03 | Binary complement and non-symbolic quantity format data multiplier |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359284B (en) * | 2006-02-06 | 2011-05-11 | 威盛电子股份有限公司 | Multiplication accumulate unit for treating plurality of different data and method thereof |
| CN108351761A (en) * | 2015-11-12 | 2018-07-31 | Arm有限公司 | Use the multiplication of the first and second operands of redundant representation |
| CN113268219A (en) * | 2021-07-19 | 2021-08-17 | 中科南京智能技术研究院 | Adder circuit with binary complement conversion |
-
2003
- 2003-09-03 CN CN 03158108 patent/CN1591318A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359284B (en) * | 2006-02-06 | 2011-05-11 | 威盛电子股份有限公司 | Multiplication accumulate unit for treating plurality of different data and method thereof |
| CN108351761A (en) * | 2015-11-12 | 2018-07-31 | Arm有限公司 | Use the multiplication of the first and second operands of redundant representation |
| CN108351761B (en) * | 2015-11-12 | 2022-08-23 | Arm有限公司 | Method and apparatus for multiplying first and second operands using redundant representations |
| CN113268219A (en) * | 2021-07-19 | 2021-08-17 | 中科南京智能技术研究院 | Adder circuit with binary complement conversion |
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