CN1588554A - USB large volume storage device - Google Patents

Abstract

The invention is a high-capacity USB memory, composed of hardware and software, where the hardware adopts universal devices and is composed of USB interface device, low-cost high speed PIC compatible MCU, and high-capacity memory chip. Its disadvantage is somewhat complex to connect but its advantage is multiple combination possibility and large select space. The invention gives a detailed software solution, and advances a special 'backup-direct write-recover' write flow based on the character of block erase and page copy of the high-capacity memory chip, thus assuring it has the characters of long service life, permanent accuracy and strong compatibility and making the made USB disc have the advantages of being easy to upgrade and performance reliability.

Description

A kind of USB mass storage device

Technical field

The invention belongs to technical field of computer, be specifically related to a kind of USB mass storage device (abbreviation USB flash disk).

Background technology

As the aid of computing machine, floppy disk since its capacity is little, speed is slow, the life-span is short etc. shortcoming replaced by USB flash disk gradually.The maximum characteristics that USB flash disk is different from floppy disk are, do not have mechanical part, thereby can accomplish that speed is fast, and capacity is big, long service life, data security are reliable.

General one piece of special integrated circuit, the high capacity storage chip of adopting of USB flash disk constitutes.The one side that this scheme is favourable is that the drawing that provides according to the special integrated circuit supplier, just directly production and processing are provided in producer.But the USB flash disk of some producer is only supported the format manipulation of producer oneself; The USB flash disk of some producer is not supported the FAT of WINDOWS98/2X, FAT32, NTFS format manipulation entirely; Also have the USB flash disk data of some producers often gratuitous destroyed; There is the problem that the life-span falls short of in addition.Trace it to its cause is that the software existing problems are write in control.

Summary of the invention

The objective of the invention is to propose that a kind of capacity is big, the life-span long, can support the USB memory storage of multiple format manipulation.

The USB mass storage device of the present invention's design is made up of hardware and control read-write software two parts.Hardware (circuit) is formed by connecting through circuit by USB interface and power source generator circuit, oscillatory circuit, usb communication circuit, single chip machine controlling circuit, mass memory interface circuit.The circuit structure block diagram is seen shown in Figure 6.Wherein, USB interface and power source generator circuit provide the USB interface with the usb communication circuit, and supply remaining circuit work from the power supply of about 3.3 volts of USB power supply derivation; Oscillatory circuit drives the usb communication circuit working; The usb communication circuit is responsible for the transmitting-receiving of usb data bag; It is mass storage device by computer Recognition oneself that single chip machine controlling circuit is responsible for by the usb communication circuit, and controls the read-write of mass memory interface circuit intelligently; The mass memory interface circuit is preserved the blocks of data that computing machine transmits via the usb communication circuit, simultaneously also under the effect of single chip machine controlling circuit via the usb communication circuit to computing machine transmission block data.The special integrated circuit that does not have USB flash disk to adopt in the design proposal of the USB mass storage device of the present invention's design, but adopt industrial general cheap chip, it is easier to upgrade, more reliable performance.

In the above-mentioned USB memory storage, power supply generation circuit adopts 3 diodes to be composed in series, and obtains 3.4 volts power supply from the step-down of 5 volts of USB power supplys; Single-chip microcomputer adopts high speed PIC compatible type MCU single-chip microcomputer MDT10P20, and the USB interface device adopts the PDIUSB12D chip, and mass storage adopts the FLASH chip, and the three forms USB high capacity memory module.

Among the present invention, Control Software is made of 2 parts: USB device identification division and high capacity storage read-write part.Wherein, the USB device identification division is finished by 0 read-write of control end points, meets USB standard 1.1; High capacity storage read-write part is finished by end points 2 read-writes, meets USB MASS STORAGE CLASS BULK-ONLY TRANSPORT standard.The operating specification that also will meet in addition, USB interface device and high capacity storage chip.

Description of drawings

Fig. 1 is USB interface and power source generator circuit.

Fig. 2 is the usb communication circuit.

Fig. 3 is a single chip machine controlling circuit.

Fig. 4 is the mass memory interface circuit.

Fig. 5 is

Fig. 6 is the circuit structure block diagram of this memory storage.

Fig. 7 is the Control Software block diagram of this memory storage.

Number in the figure: 1 is USB interface and power source generator circuit, and 2 is the usb communication circuit, and 3 is oscillatory circuit, and 4 is single chip machine controlling circuit, and 5 is the mass memory interface circuit.

Embodiment

Describe the present invention in detail below by embodiment and accompanying drawing.

USB interface shown in Figure 1 and power source generator circuit provide the USB interface with the usb communication circuit, and supply remaining circuit work from the power supply of about 3.3 volts of USB power supply derivation.J1 is a USB socket, and 1 pin is USB ground, and 2 pin are data line DP of USB, and 3 pin are data line DN of USB, and 4 pin are 5 volts of power leads of USB.D2, D3 are 2 silicon diode 1N4007, and D1 is a germanium diode AK15.Three diode series connection are connected between 4 pin and signal V3.3 of J1 as shown in the figure.The pressure drop of three diodes is approximately the 0.65*2+0.3=1.6 volt, from 5 volts of power supplys of 4 pin, draws V3.3 and is approximately 3.4 volts, in order to drive remaining circuit.We select remaining components and parts like this, make their operating voltage between 2.7 volts to 3.6 volts.The effect of capacitor C 3 is to stablize the V3.3 power supply signal.

Usb communication circuit shown in Figure 2 is responsible for the transmitting-receiving of usb data bag.Adopt USB interface device PDIUSB12D, this chip meets the USB1.1 standard, has the full speed usb communication function of 12Mbit/s, and 8 bit parallel interfaces are arranged, and makes things convenient for Single-chip Controlling.The mode of operation 0 of this chip provides end points 0 and end points 2, and end points 0 has the I/O function, and the maximum data packet length is 16 bytes, is used for the control transmission of LSB; End points 2 has the I/O function, and the maximum data packet length is 64 bytes, and the data buffer of dual 64 bytes is arranged, and is fit to piece transmission at full speed.Its pin connects as follows:

1. 5,24 pin are its supply pins, 5 pin ground connection, and 24 pin are connected on the V3.3 signal;

2. 22,23 pin are its vibration pin, the two ends of receiving the ceramic resonator Y1 of built-in stable electric capacity on request, and the frequency of Y1 is 6MHz, as shown in Figure 5;

3. 25,26 pin are respectively usb signal DN, the DP pin of this chip, are connected to 3,2 pin of USB socket by resistance R 3, the R18 of 18 Ω, and the effect of R3, R18 is the impedance of coupling difference channel;

4. the 1,2,3,4,6,7,8, the 9th, its parallel interface is received 8 bit data bus AD[0..7] on, by this bus, single-chip microcomputer can be controlled this chip on the one hand, the FLASH of high capacity storage simultaneously chip can with this chip swap data;

5. so 10 pin are address latch input signals, need not be ground connection; 14 pin are data transmit-receive interrupt identification output signals, need not, so unsettled; 12 pin are to make chip enter the suspended state input signal, open leakage, and this chip never enters suspended state among the design, so can be unsettled; 17,18,19 pin be respectively chip DMA request output, admit input, interrupt input signal that the design does not use the DMA function, so unsettled respectively, receive on the V3.3 signal; Vout33 is 3.3 volts of power supply output pins of chip, need not, can be unsettled, or receive on the V3.3 signal;

6. 11 pin are chip chip selection signals, effectively low, because bus is shared between USB interface chip, MCU single-chip microcomputer, the high capacity storage FLASH chip, when both swap datas of back occupy bus, need the USB interface chip to abandon bus control right, upward control by the MCU single-chip microcomputer so this pin is received signal nCS;

7. 28 pin are address bit input signals, and signal is that what represented in 0 o'clock to import is data on this pin, otherwise is command instruction, so receive on the CLE signal, is controlled by single-chip microcomputer;

8. 13 pin are oscillator signal output pins able to programme, and frequency is 48MHz/ (n+1), and wherein n is the positive number between 1 to 11, are 11 during beginning.This signal is connected on the Clk, is used to drive the MCU single-chip microcomputer;

9. 15,16 pin are reading and writing control input pin respectively, and are effectively low, receive on nRD, the nWR signal, controlled by the MCU single-chip microcomputer;

10. 21 pin are USB connection status pilot lamp, and are effectively low, can absorb the electric current of 8mA, so be connected with light emitting diode LP1 by resistance R 4, the other end of diode is received on the V3.3 signal, and the effect of R4 is the size of Control current.The direction of attention diode can not be put upside down;

It is mass storage device by computer Recognition oneself that single chip machine controlling circuit shown in Figure 3 is responsible for by the usb communication circuit, and controls the read-write of mass memory interface circuit intelligently.Adopt the MCU single-chip microcomputer MDT10P20 of PIC compatibility to realize that operating voltage is between 2.3 volts to 5 volts.Can certainly select other chips for use, for example EM78P257.In fact, so long as IO mouth more than 14 is arranged, the RISC single-chip microcomputer that per second can be carried out the instruction about the 5M bar when 3.3 couchers were made voltage can be competent at.The pin of MDT10P20 connects as follows:

1. supply pin 6,15 is distinguished ground connection, V3.3 signal;

2. 17 is vibration input pins, is connected to the Clk oscillator signal that PDIUSB12D transmits, the 16th, and the vibration output pin, need not, suspend;

3. 5 is the input pins that reset, effectively low, utilizes the inside electrification reset function of chip, is connected on the V3.3 signal without the function of this pin is former;

4. 8 IO mouths of 7 to 14 pin are connected to bus AD[0..7 as bus interface] on, input is during data, and these pin will be arranged to input state, during output data/order, must be arranged to output state;

5. 18 pin are used to select PDIUSB12D, are arranged to output state, are connected on the signal nCS;

6. 19 pin are used to select high capacity storage FLASH chip, are arranged to output state, are connected on the signal nCE;

7. 20,1 pin be used for control write, read, be arranged to output state, be connected respectively on nWR, the nRD signal;

8. 2 pin are used for the order indicating bit, are arranged to output state, notice PDIUSB12D and high capacity storage FLASH chip when being used to give an order;

9. 3 pin are used for the address indicating bit, are arranged to output state, notice high capacity storage FLASH chip when being used to send the address;

10. 4 pin are external pulse input ports, are connected to the operation that high capacity storage FLASH chip transmits and finish/waiting signal nINT, represent to finish in 1 o'clock, in order to quicken to finish the write operation of storer.

Mass memory interface circuit shown in Figure 4 is preserved the blocks of data that computing machine transmits via the usb communication circuit, simultaneously also under the effect of single chip machine controlling circuit via the usb communication circuit to computing machine transmission block data.Adopt USB flash disk high capacity storage FLASH chip commonly used: K9F1208UOC for example, it is the storage chip of the 64MByte that produces of SAMSUNG company, operating voltage is 2.7 volts to 3.6 volts.This chip is based on page or leaf, and every page of size is 512Byte, and 32 pages constitute a piece, have 4096 pieces.Having with the page or leaf is the read-write capability of unit, is unit with the piece when wiping, and does not need special erasing voltage.This chip also has the page copy function.Hardware connects as follows:

1. 13,36 pin are power supply ground, ground signalling; 12,37 pin are connected to the V3.3 signal;

2. 29,30,31,32,41,42,43,44 is 8 bit parallel IO interfaces, meets bus AD[0..7];

3. 9 pin are that sheet selects input signal, connect the nCE signal, by Single-chip Controlling;

4. 16,17 for order, address input signal, is connected to CLE, ale signal respectively, by Single-chip Controlling;

5. 8,18 pin are reading and writing input signals, are connected to nWR, nRD signal respectively, are controlled by Single-chip Controlling.The benefit of solderless wrapped connection here is that data can directly be transmitted between USB interface chip and high capacity storage FLASH chip, and single-chip microcomputer only need be responsible for producing nWR, the nRD pulse signal gets final product.Reading of USB interface chip is exactly writing of high capacity storage FLASH chip, and vice versa;

6. 19 pin are write-protect input signals, and are effectively low, need not, so receive on the V3.3 signal;

7. 7 pin are finished/are needed for operation and wait for output signal, receive on the nINT, and next step operation of notice single-chip microcomputer is mainly used in the read-write task of quickening to finish high capacity storage FLASH chip.

The Control Software block diagram of the USB mass storage device of the present invention's design is made of 2 parts as shown in Figure 7: USB device is known part, is finished by 0 read-write of control end points, meets USB standard 1.1; High capacity storage read-write part is finished by end points 2 read-writes, meets USB MASS STORAGE CLASS BULK-ONLY TRANSPORT.The operating specification that also will meet in addition, USB interface device and high capacity storage chip.

The detailed process of first's USB device identification is as follows:

(1) initialization.The control port of single-chip microcomputer is arranged to output state, not gating USB interface device and high capacity storage chip; The bus port of single-chip microcomputer is arranged to input state, abandons bus control right;

(2) self-expression full speed USB device.Drag down the DP pin of USB interface device, tell and inserted USB device at full speed on the computing machine USB interface, and suitable output oscillation frequency is set:

1. the D12_SetMode function that is provided in the operation instruction file of this device is provided, disconnects this device.Note, D12_SetMode has called bottom D12_Output function, and single-chip microcomputer is when USB interface device write data, and it is output state that bus should be set earlier, by nCS signal gating USB interface device, the combination by CLE, nWR, nRD signal sends order, data successively then again.Recovering bus after finishing is input state, not gating USB interface device.The operation of another bottom D12_Input function similarly repeats no more;

2. wait for 50 milliseconds;

3. call the D12_SetDMA function, close the DMA function;

4. call the D12_SetMode function once more, connect this device and suitable output oscillation frequency is set;

(3) check whether end points 0 receives data.Call the D12_ReadEndpoint function, only read the length (can not clear data) of the data that end points 0 input block receives, this length illustrates that greater than 0 computing machine has sent data to USB device.Whether read data bag type identification is the SETUP bag.Remove the interrupt flag bit of USB interface device end points 0 input by function D12_ReadLastTransactionStatus, obtain the type of the packet of this end points simultaneously.If not setting up bag, spare bits is set.Otherwise, further handle.

(4) read buffer zone 8 bytes, empty buffer zone.Call the D12_ReadEndpoint function and read end points 0 buffer zone 8 bytes, clear buffer is used for reading in data next time.If the data deficiencies of reading 8 bytes illustrate that the data of passing are not right, spare bits is set, the input of call function D12_SetEndpointStatus obstruction end points 0/go out; Otherwise want further concrete condition concrete analysis.

(5) resolve the USB request.Call the input of D12_AcknowledgeEndpoint function release end points 0/go out, extract the data length (the words intercepting greater than 127 is 127) of next step operation from the length field of setting up bag.Check the direction position in the bag type field, if set, the direction of next step data transmission be equipment to computing machine, this may be GetConfiguration, Get Descriptor, Get Interface, Get status standard USB request.Otherwise be computing machine to equipment, check the data length of next step operation:

1. equaling 0, may be Set Address, Set Configuration, Set Feature, Set Interface, SetDescriptor standard USB request.

2. being not more than 8, is to the equipment output data, removes spare bits, is provided with to receive position preparation reception data.

3. greater than 8, call function D12_SetEndpointStatus blocks the input of end points 0/go out.

(6) respond all USB requests.Check and set up bag request type territory:

1. standard request according to setting up the bag request domain, is made specifically corresponding.

I.GET_STATUS, setting up bag request type territory has 3 kinds of situations, returns 2 byte information respectively:

0x00:0x00 0x00 (Remote Wake Up forbid bus power source), 0x02 0x00 (permission);

0x01:0x00 0x00 (interface case);

0x02:0x01 0x00 (end points is forbidden), 0x00 0x00.

II.CLEAR_FEATURE, subset Remote Wake Up and end points forbid two kinds of situations, write down and call D12_SetEndpointStatus and make corresponding setting, return 0 length data and represent to finish.

III.SET_FEATURE, according to record, the data reflection apparatus remote that returns a byte wakes up with end points forbids two kinds of situations.

IV.SET_ADDRESS extracts new address from the numerical value territory of bag, calls the D12_SetAddressEnable function equipment is arranged to this address, returns 0 length data and represents to finish.

V.GET_DESCRIPTOR distinguishes the Returning equipment descriptor according to circumstances, or returns all configurations, interface, class, endpoint descriptor.

VI.GET_CONFIGURATION returns the configuration of a byte/clear data.

VII.SET_CONFIGURATION extracts configuration/clear flag from the numerical value territory of bag, and call function D12_SetEndpointEnable setting/removing configuration is returned 0 length data and represented to finish.

VIII.GET_INTERFACE returns data 0 expression of a byte and finishes.

IX.SET_INTERFACE returns 0 length data and represents to finish.

All the other situations, the input of call function D12_SetEndpointStatus obstruction end points 0/go out.

2. class request is if the USB_CLASS_MASS_BulkOnly_Reset request is returned 0 length data and represented OK; If USB_CLASS_MASS_BulkOnly_GetMaxLun asks, need to return the data 0 of a byte on request, 1 LUN is only supported in expression.

(7) end points 0 has data to need to send: send data.The state of call function D12_ReadLastTransactionStatus USB interface device end points 0 output, and the interrupt flag bit of removing, if spare bits=0 and transmission position=1, expression has data to need to send.Call function D12_WriteEndpoint further sends the data of maximum 16 bytes.Must be during last the transmission less than 16 bytes, expression sends and finishes.

The detailed process of second portion high capacity storage read-write part is as follows:

Check whether end points 2 receives data.Read buffer zone 36 bytes, empty buffer zone, matching check begins 4 bytes, and resolves the SCSIOP order.Call the D12_ReadEndpoint function, read data and clear buffer that maximum 36 byte end points 2 input blocks receive, this length is non-0, illustrates that computing machine has sent data to USB device.Whether matching check the 0th, 1,2,3 bytes are 0x55,0x53, and x042,0x43, unmatched words then no longer deal with.The packet signature that backs up the 4th to 7 byte is used to reply; The 15th byte is the high capacity memory command.Finish last time write operation and this operation between the write operation left over, carry out following PreRestore program:

The words of a flag set of the every block operations of Procedure PreRestore begin if, if meets another write order, and the logic area address is dropped between last the logic area address and its piece upper bound, recovers the data in the middle unwritten zone of this piece from backup block; Else recovers the data of this piece afterbody unwritten areas from backup block, remove every block operations and once indicate; Fi fi end

High and low byte from 19,20 bytes difference extraction logic regional address; High and low byte from 22,23 bytes difference extraction logic section length.According to the high capacity memory command, make following corresponding processing respectively.

(1) .SCSIOP_WRITE write order: carry out following Backup_DirectWrite__Restore and back up _ directly write _ recovery routine, the reliability of USB mass storage device and life-span all depend on it:

Procedure Backup_DirectWrite_Restore begin if begins to write one page, 1., write down the relative address in of living in of current logic area address and the logic area if every block operations once indicates removing; The end addresses in the zone that if is to be written drops within of living in of the logic area, wipes backup block (being arranged on suitably zone of size, mass storage back); Backup does not desire to write the data of Background Region to backup block; Relative address is not 0 in the else if logical blocks, wipes backup block; Relative address is not 0 in the fi if logical blocks,＜!--SIPO＜DP n=" 7 "〉--〉＜dp n=" d7 "/back up and do not desire to write the data of front area to backup block; Wipe the current piece write desired; From backup, recover not desire the front area write; Relative address is not 0 in the fi 2.if logical blocks, wipes current block; Fi calls D12_ReadEndpoint and reads end points 2 input ports 64 bytes, writes mass storage; When finishing 8 operations, write a logic area, correspondingly the logic area address increases by 1; If logic area address still same fast in the every block operations of set once indicate; Else removes every block operations and once indicates; Fi end

(2) .SCSIOP_READ, from the logic area address, if USB interface device end points 2 dicyclos are write buffering and are got whether have one at least for empty, read high capacity one by one and store 64 bytes, call D12_WriteEndpoint and write end points 2 delivery outlets (down with), till having transmitted specified logic area to computing machine and counting content.Necessary, can be out of shape D12_WriteEndpoint to quicken operation;

(3) .SCSIOP_TEST_UNIT_READY sends 13 byte OK information.13 bytes are specially: 0x55,0x53,0x42,0x43,4 bytes signature, 0,0,0,0,0;

(4) .SCSIOP_REQUEST_SENSE returns 14 byte illegal request information earlier, and the back sends 13 byte OK information.The 0th byte in 14 bytes is 0xf0, and 2 is 0x05, and 7 is 0x0a, and 12 is 0x20, and all the other are 0.

(5) .SCSIOP_INQUIRY returns the facility information of 36 bytes earlier, and the back, back sends 13 byte OK information.The 1st byte in 36 joints is 0x80, and 3 is 0x01, and 4 is 0x1f, and all the other are 0.

(6) .SCSIOP_MEDIUM_REMOVAL sends 13 byte OK information.

(7) .READ_FORMAT_CAPACITIES returns 12 byte format capacity informations earlier, and the back sends 13 byte OK information.The 3rd byte in 12 bytes is 0x08, and 4,5,6,7 is logic area sum (earlier high), and 8 is 0x02, and 9,10,11 is logic area byte number (earlier high), and all the other are 0.

(8) .SCSIOP_READ_CAPACITY returns 8 byte capacity information earlier, and the back sends 13 byte OK information.In 8 bytes 0,1,2,3 are to number since 0, the numbering of last logic area (earlier high), and 4,5,6,7 is logic area byte number (high elder generation).

(9) .SCSIOP_VERIFY sends 13 byte OK information.

(10) .SCSIOP_MODE_SENSE returns the pattern information of 8 bytes earlier, and the back, back sends 13 byte OK information.The 0th byte in 8 joints is 0x1C, and 1 is 0x06, and 3 is 0x01, and all the other are 0.

The content according to the present invention adopts single-chip microcomputer MDT10P22 as controller, downloads the SDK (Software Development Kit) of MDT10P22 from the Internet, and the software flow that provides according to the present invention is designed Control Software, generates the scale-of-two programming file of MDT10P22.Shine the schematic diagram that draws shown in the accompanying drawing with PROTEL circuit diagram design software.The placement schemes of planning components and parts adopts the paster components and parts, the PCB figure that draws beautiful.From PCB figure generator device list.The online DDK device drives developing instrument of downloading Microsoft, download UMSS USB flash disk driver package is revised generating run in the USB flash disk driver of WIN98, and with intelligence wrapper packing generation SETUP.EXE installation procedure is installed.

Claims (5)

1, a kind of USB mass storage device, constitute by hardware and software two parts, it is characterized in that hardware is formed by connecting through circuit by USB interface and power source generator circuit, oscillatory circuit, usb communication circuit, single chip machine controlling circuit, mass memory interface circuit, wherein, USB interface and power source generator circuit provide the USB interface with the usb communication circuit, and supply remaining circuit work from the power supply of about 3.3 volts of USB power supply derivation; Oscillatory circuit drives the usb communication circuit working; The usb communication circuit is responsible for the transmitting-receiving of usb data bag; It is mass storage device by computer Recognition oneself that single chip machine controlling circuit is responsible for by the usb communication circuit, and controls the read-write of mass memory interface circuit intelligently; The mass memory interface circuit is preserved the blocks of data that computing machine transmits via the usb communication circuit, simultaneously also under the effect of single chip machine controlling circuit via the usb communication circuit to computing machine transmission block data.

2, USB mass storage device according to claim 1 is characterized in that described power supply generation circuit adopts 3 diodes to be composed in series, and obtains 3.4 volts power supply from the step-down of 5 volts of USB power supplys; Single-chip microcomputer adopts high speed PIC compatible type MCU single-chip microcomputer MDT10P20, and the USB interface device adopts the PDIUSB12D chip, and mass storage adopts the FLASH chip, and the three forms USB high capacity memory module.

3, USB mass storage device according to claim 1 is characterized in that described Control Software is made of 2 parts: USB device identification division and high capacity storage read-write part; Wherein, the USB device identification division is finished by 0 read-write of control end points, meets USB standard 1.1; High capacity storage read-write part is finished by end points 2 read-writes, meets USB MASS STORAGE CLASS BULK-ONLY TRANSPORT standard; In addition, the operating specification that also meets USB interface device and high capacity storage chip.

4, USB mass storage device according to claim 1 is characterized in that in the described high capacity storage read-write software,

(1) have one finish last time write operation and this operation between the PreRestore program of the write operation left over:

Flag set of the every block operations of if,

If meets another write order, and the logic area address drop on last logic area address and its piece upper bound it

Between,

From backup, recover the data in the middle unwritten zone of this piece;

else

From backup, recover the data of this piece afterbody unwritten areas, remove will of every block operations;

fi

fi

(2) there is a Backup_DirectWrite_Restore who is used for write operation back up _ directly to write _ recovery routine, supports multiple file layouts such as FAT, FAT32, NTFS:

If begins to write one page,

1. if every block operations once indicates removing,

Write down the relative address in of living in of current logic area address and the logic area;

The end addresses in the zone that if is to be written drops within of living in of the logic area,

Wipe backup block;

Backup does not desire to write the data of Background Region to backup block;

Relative address is not 0 in the else if logical blocks, wipes backup block;

fi

Relative address is not 0 in the if logical blocks,

Backup does not desire to write the data of front area to backup block;

Wipe the current piece write desired;

From backup, recover not desire the front area write;

fi

2., wipe current block if relative address is not 0 in the logical blocks;

fi

Call D12_ReadEndpoint and read end points 2 input ports 64 bytes, write mass storage; Finish 8 times

During operation, write a logic area, correspondingly the logic area address increases by 1;

If logic area address still same fast in,

The every block operations of set once indicates;

else

Removing every block operations once indicates;

fi

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