CN1581021B - Personal digital assistant for reducing cold start rate and the method - Google Patents
Personal digital assistant for reducing cold start rate and the method Download PDFInfo
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- CN1581021B CN1581021B CN 03153043 CN03153043A CN1581021B CN 1581021 B CN1581021 B CN 1581021B CN 03153043 CN03153043 CN 03153043 CN 03153043 A CN03153043 A CN 03153043A CN 1581021 B CN1581021 B CN 1581021B
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Abstract
The present invention relates to a method for reducing probability of cold start in computer system and its computer system. The computer system has a CPU for controlling computer system, a wake-up key for waking up CPU from a sleeping mode and a battery for providing power supply for computer system. The CPu can be used for supporting software and battery failure processing function. said invention also provides the concrete steps of said method for reducing probability of cold start in the computer system.
Description
(1) technical field
Relevant a kind of method and the computer system thereof that in computer system, reduces the probability of cold boot of the present invention, and particularly relevant for a kind of Synchronous dynamic RAM (Synchronous Dynamic Random Access Memory that avoids causing computer system because of battery failures (Battery Fault), SDRAM) data run off, with the method and the computer system thereof of the probability that reduces cold boot.
(2) background technology
For a computer system that with the battery is main power supply source, when battery failures takes place, when battery can't continue to power, computer system must enter sleep pattern in real time, reduces electric energy loss.Wherein, battery failures is meant that battery electric quantity uses up, or computer system suffers external force collision, makes battery separating computer system and the situation that can't continue to power.This computer system for example be personal digital assistant (Personal DigitalAssistant, PDA).
(Central Processing Unit CPU) comprises two kinds of patterns to the general employed central processing unit of computer system at least: normal mode of operation (Normal Operation Mode) and sleep pattern (SleepMode).When if but CPU is CPU for the treatment of battery fault, after battery failures takes place, CPU will directly enter sleep pattern.When if the employed CPU of computer system is CPU for support software battery failures (SoftwareBattery fault) processing capacity, when battery failures takes place, CPU will receive battery failures indication incident.At this moment, CPU is considered as one with this battery failures indication incident to interrupt source (InterruptSource).This interrupts the source must be through after software program code (Software Code) processing, and CPU just can enter sleep pattern.
When battery failures takes place, CPU enters after the sleep pattern, on the main circuit board of computer system remaining electric weight, comprise the electric weight that equivalent capacity on the main circuit board is stored and the electric weight of standby power supply, SDRAM will be continued to be supplied to, to continue to preserve the data on the SDRAM.Like this, as long as the battery that more renews of user or the battery that will come off are reinstalled finish, then CPU can be waken up once more, and computer system will return back to the state that enters before the sleep pattern and continue to use for the user.After CPU is waken up, CPU will carry out hardware initialization earlier, and afterwards, CPU can begin to carry out the utilization program.Wherein, CPU is when hardware initialization, and CPU can carry out the loading procedure of software program code.The loading procedure of software program code comprises the loading procedure of boot code (Boot Code).
Yet, when above-mentioned employed CPU is CPU for support software battery failures processing capacity, battery failures must betide CPU after the action of the intact hardware initialization of successful execution, and software program code can be handled corresponding battery failures indication incident and make CPU enter sleep pattern.If battery failures is to betide in the process that CPU carrying out hardware initialization, software program code can't be handled this battery failures indication incident, and can't make CPU enter sleep pattern.Like this, because CPU will still be maintained at the normal mode of operation of the big volume and electricity of loss, and battery is unable to supply power supply, so till the remaining capacity on the main circuit board of computer system with quick loss, finishes to all kwh losses.At this moment, the data on the SDRAM will exhaust because of the electric weight on the main circuit board, and main circuit board can't continue power supply and all run off.User's all data and the program of original download will all be eliminated.After the user changes battery or again battery installed,,, return back to the original state of computer system when dispatching from the factory so computer system can only be carried out cold boot (Cold Reset) because of the data of SDRAM disappear.
For ease of explanation, after now CPU being waken up by sleep pattern, CPU carry out hardware initialization during be defined as T1 between the first phase, and after CPU carries out hardware initialization, CPU normally begun to carry out the utilization program during be to be defined as second phase T2.
Please refer to Fig. 1, it is the coherent signal oscillogram that betides T1 between the first phase when battery failures.Power supply enable signal PWR_EN is in order to indicate whether to enter sleep pattern.When power supply enable signal PWR_EN is activation (enabled), for example be high levels, CPU is in normal mode of operation; And when power supply enable signal PWR_EN is disabled, for example be low level, CPU is in sleep pattern.Core cpu power supply signal CPU_CR_PWR is the power supply state in order to the core power supply of indication CPU.As CPU during in normal mode of operation, battery is that normal power supply is given CPU, so core cpu power supply signal CPU_CR_PWR is a high levels, and as CPU during in sleep pattern, battery is not powered to CPU, so core cpu power supply signal CPU_CR_PWR is for being low level.
In addition, CPU peripheral assembly power supply CPU_IO_PWR is the power supply state in order to the peripheral assembly of indication CPU.No matter CPU is in normal mode of operation or sleep pattern, the peripheral assembly of CPU all has the power supply supply, so CPU peripheral assembly power supply CPU_IO_PWR is high levels.Battery failures signal BTRY_FLT is in order to indicate whether having battery failures to take place.When battery failures signal BTRY_FLT was activation, battery failures signal BTRY_FLT transferred low level to.
Please refer to Fig. 1.When time point t1, CPU is waken up from sleep pattern, and power supply enable signal PWR_EN transfers high levels to, and CPU enters T1 between the first phase.If battery failures takes place in the T1 between the first phase, will produce battery failures indication incident 102, battery failures signal BTRY_FLT will transfer low level to.At this moment, software program code can't be handled this battery failures, so CPU will continue to be maintained at normal mode of operation, and consume a large amount of electric energy.After time point t2, because the electric energy on the main circuit board can be exhausted, main circuit board can't provide power supply to SDRAM again.Data on the SDRAM are with complete obiteration.
Please refer to Fig. 2, it is the coherent signal oscillogram that betides second phase T2 when battery failures.Time point t3 in battery failures betides second phase T2 and when producing battery failures indication incident 202, because software program code treatment of battery indicating fault incident 202 successfully, so CPU will successfully enter sleep pattern, with the minimizing loss of power.At this moment, the remaining capacity on the main circuit board still can continue to be supplied to SDRAM, so the preservation that the stored data of SDRAM still can be complete.
Therefore, how to solve because of battery failures and betide between the first phase, make the remaining capacity of main circuit board still to be maintained at the normal mode of operation approach exhaustion because of CPU, main circuit board can't be supplied the SDRAM power supply and problem that the stored data of SDRAM run off again, to reduce the probability of computer system cold boot, be one of industry direction of making great efforts.
(3) summary of the invention
In view of this, the purpose of this invention is to provide a kind of method and computer system thereof that in computer system, reduces the probability of cold boot.The present invention can avoid battery failures to betide between the first phase effectively, cause the problem of SDRAM data loss, and can reduce the probability of cold boot.
According to purpose of the present invention, a kind of method that reduces the probability of cold boot in personal digital assistant is proposed, this personal digital assistant has in order to control a central processing unit of this personal digital assistant, in order to one to wake this central processing unit up button from what a sleep pattern was waken up, and with thinking that this personal digital assistant provides a battery of power supply, this central processing unit support software battery failures processing capacity, this method comprises: be at this central processing unit under the situation of this sleep pattern, and this personal digital assistant is in a battery electric quantity when supplying uncertain state, even a wake events produces, this central processing unit still continues to be maintained at this sleep pattern; And be in this sleep pattern when this central processing unit, and this wake that button is pressed up during during less than a predetermined value, then this central processing unit continues to be maintained at this sleep pattern.
The present invention also provides a kind of personal digital assistant, comprising: a central processing unit, in order to control this personal digital assistant, this central processing unit support software battery failures processing capacity; One circuit unit electrically connects with this central processing unit, and this circuit unit is in order to receiving a wake events, and optionally exports this wake events to this central processing unit; One decision circuitry in order to the state according to this personal digital assistant, is controlled this circuit unit; And a battery, with thinking that this personal digital assistant provides power supply; Wherein, be at this central processing unit under the situation of this sleep pattern, in wake events generation, this decision circuitry is judged battery cover open mode or the low state of charge of battery whether this personal digital assistant is in battery fault condition, battery, if, then this circuit unit does not export this wake events to this central processing unit, makes this central processing unit still continue to be maintained at this sleep pattern.
The present invention also provides a kind of method that reduces the probability of cold boot in personal digital assistant, this personal digital assistant has in order to control a central processing unit of this personal digital assistant, in order to one to wake this central processing unit up button from what a sleep pattern was waken up, and in order to supply a battery of this personal digital assistant power supply, this central processing unit support software battery failures processing capacity, this method comprises: be in this sleep pattern in this central processing unit, in wake events generation, judge whether this personal digital assistant is in battery fault condition, under the low state of charge of the battery cover open mode of battery or battery, if then this central processing unit still continues to be maintained at this sleep pattern.
For above-mentioned purpose of the present invention, characteristics and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. is elaborated as follows:
(4) description of drawings
Fig. 1 is the coherent signal oscillogram that betides T1 between the first phase when battery failures.
Fig. 2 is the coherent signal oscillogram that betides second phase T2 when battery failures.
Fig. 3 is according to a preferred embodiment of the present invention, carries out the calcspar of the computer system of said procedure (1).
Fig. 4 A is that the central processing unit (CPU) of Fig. 3 is in sleep pattern, and decision circuitry to judge computer system be when being in battery electric quantity and supplying uncertain state, the oscillogram of the first signal S1 and secondary signal S2.
Fig. 4 B is that the CPU of Fig. 3 is in sleep pattern, and decision circuitry is judged when computer system is non-to be in battery electric quantity and to supply uncertain state the oscillogram of the first signal S1 and secondary signal S2.
Fig. 5 is according to a preferred embodiment of the present invention, carries out the calcspar of the computer system of said procedure (2).
Fig. 6 A is among Fig. 5, and CPU is in sleep pattern, and wake that button is pressed up during the 3rd signal S3 during less than predetermined value P and the oscillogram of the 4th signal S4.
Fig. 6 B is among Fig. 5, and CPU is in sleep pattern, and wake that button is pressed up during the 3rd signal S3 during greater than predetermined value P and the oscillogram of the 4th signal S4.
(5) embodiment
The present invention is by avoiding battery failures to betide T1 between the first phase, avoiding tradition totally to make all problems of loss of SDRAM data because of electric quantity consumption.And the battery failures of avoiding proposed by the invention betides that the program of T1 comprises between the first phase: (1) is in sleep pattern when computer system, and when computer system is in a battery electric quantity and supplies uncertain state, comprise that battery fault condition, battery cover open mode or battery hang down state of charge, even a wake events (Wake-up Event) produces, the wake events that is produced is not to be sent among the CPU, makes CPU continue to be maintained at sleep pattern.(2) when computer system is in sleep pattern, computer system is waken the time length that button is pressed up by judgement, judges and whether wakes button up because of triggered by external force collision.During waking that button is pressed up, during less than a predetermined value, also make CPU continue to be maintained at sleep pattern.Program (1) and program (2) can be implemented simultaneously or implement individually.
Please refer to Fig. 3, it is according to a preferred embodiment of the present invention, carries out the calcspar of the computer system 300 of said procedure (1).Computer system 300 includes a central processing unit (Central Processing Unit, CPU) 302, one circuit unit 304, a decision circuitry 306 and a battery 308.CPU 302 is in order to controlling computer system 300.CPU 302 is support software battery failures processing capacities.Circuit unit 304 is to electrically connect with CPU 302.Circuit unit 304 is in order to receiving one first signal S1, and exports a secondary signal S2.Decision circuitry 306 is in order to the state according to computer system 300, control circuit unit 304.Battery 308 then is in order to supply computer system 300 power supplys.
Please refer to Fig. 4 A, it is that the CPU 302 of Fig. 3 is in sleep pattern, and decision circuitry 306 to judge computer system 300 be when being in battery electric quantity and supplying uncertain state, the oscillogram of the first signal S1 and secondary signal S2.Suppose that the first signal S1 is a low level when the first signal S1 activation; Similarly, when secondary signal S2 activation, secondary signal S2 is a low level.When a wake events 410 when time point t4 produces, the first signal S1 transfers low level to.When CPU 302 is in sleep pattern, and it is when being in battery electric quantity and supplying uncertain state that decision circuitry 306 is judged computer system 300, circuit unit 304 is can not send wake events 410 to CPU 302, so the time secondary signal S2 be maintained at high levels.Even wake events 410 is input to circuit unit 304, still, because CPU 302 does not receive wake events, so CPU 302 will continue to be maintained at sleep pattern.
Please refer to Fig. 4 B, it is that the CPU 302 of Fig. 3 is in sleep pattern, and decision circuitry 306 is judged when computer system 300 is non-to be in battery electric quantity and to supply uncertain state the oscillogram of the first signal S1 and secondary signal S2.When a wake events 420 when time point t5 produces, the first signal S1 transfers low level to.When CPU 302 is in sleep pattern, and decision circuitry 306 judges when computer system 300 is non-to be in battery electric quantity and to supply uncertain state, and circuit unit 304 can transmit wake events 422 and give CPU 302.CPU 302 will be waken up.
When computer system when battery electric quantity is supplied uncertain state, the present invention does not make CPU 302 be waken up by not allowing wake events input to CPU 302, enters T1 between first phase of above-mentioned execution hardware initialization to avoid computer system.This be because, when computer system 300 has not had electric weight and the battery battery fault condition that battery can't normal power supply such as come off in (1) battery; (2) user will open in order to the battery cover of self-contained battery, will take out battery to change the battery cover open mode of battery; Or during the low state of charge of the low excessively battery of the stored electric weight of (3) battery, if wake computer system 300 up, make computer system 300 enter normal mode of operation, and enter T1 between the first phase to carry out the words of hardware initialization, more than three kinds of states all may produce battery and can't continue power supply, remaining capacity on the main circuit board exhausts fast, and the situation that the SDRAM data are all run off.So the present invention is by the state that detects computer system 300, when computer system meets above-mentioned three kinds of states, then allow CPU 302 continue to remain on sleep pattern.Like this, CPU 302 will can not enter T1 between the above-mentioned first phase, also can be just like in the conventional practice, and the problem that software program code can't the treatment of battery event of failure.Remaining capacity on the main circuit board is continued to power to SDRAM to keep its stored data.So computer system 300 of the present invention can avoid the SDRAM data to run off, and reduces the chance of cold boot.
Please refer to Fig. 5, it is according to preferred embodiment of the present invention, carries out the calcspar of the computer system 500 of said procedure (2).Computer system 500 comprises wakes button 530, a CPU 502, a delay protection circuit 532 and a battery 508 up.Waking button 530 up is to be disposed on the shell of computer system 500, uses for the user and operates.CPU 502 is in order to controlling computer system 500, CPU 502 and support software battery failures processing capacity.Delay protection circuit 532 is the states that wake button 530 in order to detection up.Waking button 530 up is to export one the 3rd signal S3 to delay protection circuit 532, and delay protection circuit 532 is output one the 4th signal S4 to CPU 502.Battery 508 is in order to provide computer system 500 required power supply.
Waking button 530 up may press by user's finger, also may be because computer system 500 drops and clashed into and be pressed.When computer system 500 dropped, battery 508 also came off because of the cause of collision probably simultaneously.Generally speaking, wakes button 530 up and be about 1～2 millisecond (millisecond), and press...with one's finger the down time span of waking button 530 up of user is longer usually because of the general value of collision or the time span that is pressed of bump, its generally value be about about 100 milliseconds.So the present invention is by setting a predetermined value P, predetermined value P is greater than 1～2 millisecond, and less than 100 milliseconds.As long as judge wake that button 530 is pressed up during during less than predetermined value P, can learn that waking button 530 this moment up is to be pressed because of collision or bump.
Because when computer system 500 dropped or clashed into, battery 508 was also hit probably.If battery 508 comes off, then battery 508 can't normally be powered to computer system 500.At this moment, if allow CPU 502 wake up from sleep pattern, then the remaining capacity on the main circuit board will be by approach exhaustion apace, and the SDRAM data are run off.So, when CPU 502 is in sleep pattern, and delay protection circuit 532 detect wake that button 530 is pressed up during during less than predetermined value P, represent that then computer system 500 may be collided or clash into, battery 508 comes off probably.At this moment, the present invention is by making CPU 502 continue to be maintained at sleep pattern, with the situation of avoiding the SDRAM data to run off.
Please refer to Fig. 6 A, it is among Fig. 5, and CPU 502 is in sleep pattern, and wake that button 530 is pressed up during the 3rd signal S3 during less than predetermined value P and the oscillogram of the 4th signal S4.Suppose that the 3rd signal S3 is a low level when the 3rd signal S3 activation; Similarly, when the 4th signal S4 activation, the 4th signal S4 is a low level.When a wake events 610 when time point t6 produces, the 3rd signal S3 transfers low level to.When CPU 502 is in sleep pattern; and delay protection circuit 532 detect wake that button 530 is pressed up during during less than predetermined value P; though delay protection circuit 532 receives wake events 610, delay protection circuit 532 will not transmit any wake events and give CPU 502.So the time postpone holding circuit 532 outputs the 4th signal S4 will be maintained at high levels in time point t6, CPU 502 then continues to be maintained at sleep pattern.
Please refer to Fig. 6 B, it is among Fig. 5, and CPU 502 is in sleep pattern, and wake that button 530 is pressed up during the 3rd signal S3 during greater than predetermined value P and the oscillogram of the 4th signal S4.When a wake events 620 when time point t7 produces, the 3rd signal S3 transfers low level to.When CPU 502 is in sleep pattern, and delay protection circuit 532 detect wake that button 530 is pressed up during during greater than predetermined value P, represent the user to supress and wake button 530 up, desire to wake up computer system 500.Therefore, after delay protection circuit 532 receives wake events 620, delay protection circuit 532 will be exported a wake events 622 to CPU 502.At this moment, the 4th signal S4 of delay protection circuit 532 outputs is to transfer low level in time point t6, and CPU 502 will be waken up.
Wherein, delay protection circuit 532 is controlled by a control signal CTRL.When computer system 500 was in sleep pattern, control signal CTRL was activation, and delay protection circuit 532 is to be activated, to carry out the action as Fig. 6 A and Fig. 6 B.And when computer system 500 was in normal mode of operation, control signal CTRL was disabled, and delay protection circuit 532 is to be failure to actuate.At this moment, the 3rd signal S3 will directly be sent to CPU 502.Like this, can accelerate the operating speed of computer system 500 under normal mode of operation.
The method and the computer system thereof that reduce the probability of cold boot in computer system that the above embodiment of the present invention disclosed can avoid battery failures to betide T1 between the first phase effectively, cause the problem of SDRAM data loss, and can reduce the probability of cold boot.The present invention is for computer system, and particularly personal digital assistant has more time that can prolong the SDRAM storage data and the advantage of preserving data integrity.
In sum; though the present invention discloses as above with a preferred embodiment; yet it is not in order to limit the present invention; any person skilled in the art person without departing from the spirit and scope of the present invention; when can doing various changes and replacement, so protection scope of the present invention is when looking being as the criterion that accompanying Claim defines.
Claims (5)
1. method that in personal digital assistant, reduces the probability of cold boot, this personal digital assistant have in order to a central processing unit of controlling this personal digital assistant, in order to this central processing unit from a sleep pattern wake up one wake button up, and with thinking that this personal digital assistant provides a battery of power supply, this central processing unit support software battery failures processing capacity, this method comprises:
Be at this central processing unit under the situation of this sleep pattern, and this personal digital assistant is when being in a battery electric quantity and supplying uncertain state, even a wake events produces, this central processing unit still continues to be maintained at this sleep pattern; And
When this central processing unit is in this sleep pattern, and this wake that button is pressed up during during less than a predetermined value, then this central processing unit continues to be maintained at this sleep pattern.
2. the method for claim 1 is characterized in that, this predetermined value is waken the general value of button because of collision or the time span that is pressed of bump up greater than this, and wakes the general value of the time span that button pressed by a user up less than this.
3. the method for claim 1 is characterized in that, this predetermined value is greater than 2 milliseconds, and less than 100 milliseconds.
4. personal digital assistant comprises:
One central processing unit is in order to control this personal digital assistant, this central processing unit support software battery failures processing capacity;
One circuit unit electrically connects with this central processing unit, and this circuit unit is in order to receiving a wake events, and optionally exports this wake events to this central processing unit;
One decision circuitry in order to the state according to this personal digital assistant, is controlled this circuit unit; And
One battery is with thinking that this personal digital assistant provides power supply;
Wherein, be at this central processing unit under the situation of this sleep pattern, in wake events generation, this decision circuitry is judged battery cover open mode or the low state of charge of battery whether this personal digital assistant is in battery fault condition, battery, if, then this circuit unit does not export this wake events to this central processing unit, makes this central processing unit still continue to be maintained at this sleep pattern.
5. method that in personal digital assistant, reduces the probability of cold boot, this personal digital assistant have in order to a central processing unit of controlling this personal digital assistant, in order to this central processing unit from a sleep pattern wake up one wake button up, and with thinking that this personal digital assistant provides a battery of power supply, this central processing unit support software battery failures processing capacity, this method comprises:
Be in this sleep pattern in this central processing unit, in wake events generation, judge whether this personal digital assistant is under the battery cover open mode or the low state of charge of battery of battery fault condition, battery, if then this central processing unit still continues to be maintained at this sleep pattern.
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| CN 03153043 CN1581021B (en) | 2003-08-07 | 2003-08-07 | Personal digital assistant for reducing cold start rate and the method |
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| CN 03153043 CN1581021B (en) | 2003-08-07 | 2003-08-07 | Personal digital assistant for reducing cold start rate and the method |
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| CN1581021A CN1581021A (en) | 2005-02-16 |
| CN1581021B true CN1581021B (en) | 2010-05-26 |
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| CN 03153043 Expired - Fee Related CN1581021B (en) | 2003-08-07 | 2003-08-07 | Personal digital assistant for reducing cold start rate and the method |
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| CN100412761C (en) * | 2006-01-20 | 2008-08-20 | 佛山市顺德区顺达电脑厂有限公司 | Method for displaying awakening event of computer system in graphics context mode |
| CN102387571A (en) * | 2010-09-06 | 2012-03-21 | 中国移动通信集团上海有限公司 | Communication establishing method, system and device for wireless sensor network |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0404061A2 (en) * | 1989-06-23 | 1990-12-27 | Kabushiki Kaisha Toshiba | Computer having a resume function and operable on an internal power source |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0404061A2 (en) * | 1989-06-23 | 1990-12-27 | Kabushiki Kaisha Toshiba | Computer having a resume function and operable on an internal power source |
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