CN1574753A - Serial advanced technology attachment (sata) switch - Google Patents

Abstract

An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device. Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch.

Description

Serial Advanced Technology Attachment (SATA) switch

The cross reference of related application

The application has required to propose on June 11st, 2003, application number is 60/60/477,857, the priority that is entitled as the U.S. Provisional Patent Application of " Serial ATA Switch ", and the application proposed on February 9th, 2004, be entitled as " SwitchingSerial Advanced Technology Attachment (SATA) To A ParallelInterface " the _ _ the part continuation application of number U.S. Patent application, and proposed on February 9th, 2004, be entitled as " Route Aware Serial Advanced TechnologyAttachment (SATA) Switch " _ _ the part continuation application of number U.S. Patent application.

Technical field

The present invention relates generally to Serial Advanced Technology Attachment ATA (SATA) switch, relate in particular to have the switch of two host ports and a device port, described device port allows two host ports to conduct interviews to device port simultaneously.

Technical background

The SATA protocol overview

" equipment " refers to the external equipment of the existing standard that adopts in accordance with industry as used herein.SATA is the high speed serialization link displacement that is used for parallel Advanced Technology Attachment (ATA) structure of mass-memory unit.The serial link that is adopted is a point-to-point high speed differential link, and this link uses and is kilomegabit technology well known to those of ordinary skill in the art and 8b/10b coding.Described SATA agreement is based on the layer traffic model that is similar to the OSI(Open Systems Interconnection) reference model.Introduce general introduction below.For more details, ask the reader referring to the SATA standard that is hereby incorporated by.Described SATA standard in August 29 calendar year 2001, be entitled as the publication of the revised edition 1.0 of " SerialATA:High Speed Serialized ATA Attachment ", and provide in the publication of revised edition 1.0 on October 16th, 2002, that be entitled as " Serial ATA II:Extensionsto Serial ATA 1.0 ", this two parts content can obtain from the website www.serialata.com of Serial ATA working group usually.

In the SATA agreement, every layer protocol and its other side directly or indirectly communicate.Fig. 1 a shows SATA protocol communication layer 20.Physical communication between physics (Phy) layer (PL) the 21 management SATA unit.The PL service comprises:

Serialization comes from the parallel input of link layer (LL) 22 and sends differential non-return-to-zero (NRZ) to serial flow.

Receive differential NRZ serial flow, from serial bit stream, extract data (and preferably clock), the described serial flow that unstrings, and provide the position of calibration and the also line output of word to LL 22.

Execution powers up ordering, and the execution speed negotiation.

Outer (00B) input of band and the generation of appointment are provided

Described serial ATA chain route is according to the protocol definition of existing standard, and it has four layers of communication, is used for the physical layer, link layer, transport layer and the application layer that communicate at physical level that is:, perhaps sometimes application layer is called layer order.Transmitter and receiver can't directly communicate with one another, but before arriving another equivalent layer, they must be by other layer of their systems.For example, for the physical layer that makes transmitter and the transport layer of receiver communicate, must then by the application layer of serial ATA link, arrive the transport layer of receiver at last at first by link, transmission and the application layer of transmitter to receiver.

The base unit of communication or exchange is a frame.Frame comprises that frame begins (SOP) primitive, frame information structure (FIS), the Cyclic Redundancy Check that calculates and frame end (EOF) primitive on the content of FIS.Described serial ATA structure has defined a kind of standard, and the definition of frame wherein is provided, and described definition will spread all over this document use.Primitive is double word (Dword) entity that is used to control and provide the state of serial transmission line.Described serial ATA structure has defined a kind of like this standard, and the definition of the primitive that allows wherein is provided, and this definition will spread all over this document use.

Fig. 1 b shows the example of frame 30.In Fig. 1 b, described frame is from SOF primitive (primitive) 30a, succeeded by a FIS content 30b, the back is to be used to indicate transmitter not have the HOLD primitive 30c of data available, succeeded by the 2nd FIS content 30d, succeeded by sending the HOLDA primitive 30e that receives the HOLD primitive for confirmation, the HOLD primitive is sent by receiver, be used to indicate the receiver buffer to be in ' not ready ' state, succeeded by CRC 30f and EOF primitive 30g.

In Fig. 1 b, described frame comprises two primitive HOLD and the HOLDA primitive that is used for flow control.The HOLD primitive shows the impossibility that sends or receive the FIS content.The HOLDA primitive is sent out the reception of HOLD primitive for confirmation.For example, when the buffer that detects it when receiving node almost is full, it will send a HOLD primitive to sending node, request transmitter node stop, and ready when receiving more multidata when described buffer, described receiving node will stop to send the HOLD primitive.Described sending node sends the HOLDA primitive, to confirm the reception of HOLD primitive.Up to receiving the HOLDA primitive, described receiving node just continues to receive data.Overflow for fear of buffer, described SATA agreement is sending the HOLD primitive and is receiving the maximum delay that requires 20 double words between the HOLDA primitive node.

Shown in Fig. 1 d, there is multiple different frame type.For example, in order to send data, used thereafter the frame that is called DMA setup FIS (DMA sets up FIS) as DMA data FIS (DMA data FIS) via direct memory access (DMA) (DMA).Usually there are three kinds of FIS structures, a kind ofly are used for order, a kind ofly are used for setting up transmission, and the another kind of data that are used for about transmission.Every kind of frame structure is used for different purposes.As mentioned above, and shown in Fig. 1 c, the command type of transmit frame in case fill order will set up the data transfer phase that frame is used for warning order, and Frame is used to transmit data.At described layer order, described system communicates by letter with layer order by assignment file.Described layer order uses two different buses to communicate by letter, and one is used to transmit data FIS, and another is used to transmit non-data FIS.Though at this 2 kinds of buses have been discussed, also can have been adopted single bus.

Link layer (LL) 22 sends with received frame, sends primitive based on the control signal that comes from PL 21, and receives the primitive that comes from physical layer (PL) 21, and described primitive is converted into control signal and sends to transport layer (TL) 23.

Transport layer (TL) 23 need not know how to send and received frame.TL 23 is configured to the frame information structure (FIS's) transmitting and decompose the FIS that is received simply.

Fig. 1 d shows the FIS type.Described FIS type is summarized as follows:

-register FIS (Register FIS)-main frame is to equipment 40 (i)

-register FIS (Register FIS)-equipment to main frame 40 (ii)

-DMA starts FIS (DMA Activate FIS) 40 (iii)

-DMA sets up FIS (DMA Setup FIS) 40 (iv)

-equipment position FIS (Set Device Bits FIS) 40 is set (v)

-PIO sets up FIS (PIO Setup FIS) 40 (vi)

-data FIS (Data FIS) 40 (vii)

-BIST starts FIS (BIST Activate FIS 40) (viii)

In the application layer of serial ATA link, one group of register of host access, described register have ATA register, FPDP, mistake, feature, sector, cylinder (Cylinder) lower curtate, the high portion of cylinder, state and order.Thus, described application layer communicates according to the language identical with the ATA standard, and this operates in the layer order and carries out.Thus, described layer order uses the registers group identical with the ATA link.Described registers group is called as task file register.

Described layer order (CL) or application layer (AL) 24 are carried out alternately with TL 23, so that transmission/reception order, data and state.Described CL 24 comprises the block of registers register; Also claim assignment file (TF), be used for transmitting order or mailing state, the operation that provided by traditional Parallel ATA is provided for it.

Fig. 1 c shows the simple version of mask register piece (the Shadow Register Block) structure 31 of Parallel ATA.Described mask register piece comprises

-FPDP 31dp

-error register 31e

-feature register 31f

31sc is calculated in-sector

-sector number 31sn

-cylinder lower curtate 31cl

The high 31ch of portion of-cylinder

-equipment/head 31dev

-state 31s

-order 31c

-alternating state 31as

-Equipment Control 31dc

The sata port that comprises part or all 1 layer functions will be introduced as 1 grade of port of SATA at this.The sata port that comprises part or all 1 and 2 layer functions will be introduced at this as SATA2 level port.The sata port that comprises part or all 1,2 and 3 layer functions will be introduced as 3 grades of ports of SATA.The sata port that comprises part or all 1,2,3 and 4 layer functions will be introduced at this as 4 grades of ports of SATA.The term sata port refers to the universal port that comprises 1 grade or 2 grades or 3 grades or 4 grades.Described SATA layer be used to be coupled main frame or equipment.Term SATA host port refers to the sata port that links to each other with main frame.Term SATA device port refers to the sata port that links to each other with equipment.For example, if the output high speed differential transmission signal 51tx of Fig. 2 a is linked to each other with main frame with the differential received signal 51rx of input, sata port is the SATA host port so.Similarly, if the output high speed differential transmission signal 51tx of Fig. 2 a is linked to each other with equipment with the differential received signal 51rx of input, sata port is the SATA device port so.

Fig. 2 a and 2b show the block diagram of sata port 50.Sata port 50 comprises PL circuit 51, LL circuit 52, TL circuit 53 and CL circuit 54.Described PL circuit 51 and output high speed differential transmission signal 51tx are linked to each other with the differential received signal 51rx of input, PL circuit 51 is sent bus 52t via link link to each other with LL circuit 52 with link reception bus 52r.Described PL circuit 51 comprises AFE (analog front end) (AFE) 51a, initial physical state machine (Phy ISM) 51b, outer (OOB) detector 51c of band, physics/link interface 51e.Physics/link interface piece optionally comprises elasticity first in first out (FIFO) 51ef and sends FIFO51tf.Described physics/link interface 51e sends bus 52t via link and link receives the coupling that bus 52r provides PL circuit 51 to LL circuit 52.Select link to send data 51t or come from the initialization sequence 51s of Phy ISM 51b by the multiplexer 51d of Phy ISM 51b control.Described AFE 51a comprises phy receiver and physics transmitter.Described AFE 51a is coupled to differential transmission signal 51tx and differential received signal 51rx reception data 51r and sends data 51td.Described physics transmitter starts (PhyTxEn) signal 51te by the physics transmitter and starts.When described physics transmitter was under an embargo, described physics output was in idle bus state (the Tx differential signal is reduced to zero).OOB detector 51c detects outer (OOB) signal 51o of band.Described OOB signal 51o comprises COMRESET, COMWAKE.

Described LL circuit 52 sends bus 52t via link and links to each other with PL circuit 51 with link reception bus 52r.Described LL circuit 52 receives bus 53r via transmission transmission bus 53t, transmission and links to each other with TL circuit 53 with transmission control/status bus 53c.Described TL circuit 53 comprises data FIS first in first out (FIFO) circuit 53a, non-data FIS block of registers 53b and multiplexer 53d, and described circuit 53a is used for keeping during the transmission data FIS, and described 53b is used to keep non-data FIS.Data FIS FIFO 53a is a circuit based on dual port FIFO, and each port all has independently input and output.Described FIFO 53a comprises a FIFO port 53a (1) and the second port 53a (2), described first port also comprises a first input end mouth 53a (i1) and a FIFO output port 53a (o1), and described second port also comprises the 2nd FIFO input port 53a (i2) and the second output port 53a (o2).

The one FIFO port 53a (1) sends bus 53t, transmission reception bus 53r and transmission control/status bus 53c and 52 couplings of LL circuit via described transmission.The 2nd FIFO port 53a (2) receives bus 54r via data FIS and data FIS sends bus 54t and 54 couplings of CL circuit.TL circuit 53 is via assignment file input bus 54i and assignment file output bus 54o and 54 couplings of CL circuit.Multiplexer 53d selects between a FIFO output port 53a (o1) and assignment file input bus 54i.CL circuit 54 comprises assignment file 54a.Assignment file 54a is via assignment file input bus 54i and assignment file output bus 54o and 53 couplings of TL circuit.Assignment file 54a is via port assignment file input bus 56i and port assignment file output bus 56o and system bus 57 couplings, in addition, CL circuit 54 is coupled to system bus 57 via data input bus (DIB) 55i and data-out bus 55o with data FIS reception bus 54r and data FIS transmission bus 54t.The configuration signal configuration is used for the operation of the sata port of main frame or operation of equipment.CL circuit 54 can be coupled to system bus 57 via single bus, be used for the visit of FPDP and assignment file.

The SATA switch of prior art allows two different main frames to connect same equipment, yet when a main frame was linked to each other with described equipment, another main frame can't be visited described equipment.This restriction of prior art systems will be explained further.The SATA switch of prior art does not allow two main frames to visit described equipment simultaneously.

Fig. 3 a shows the system 10 that uses prior art SATA switch 14.The system 10 that illustrates comprises the main frame 11 with SATA host bus adaptor (SATA HBA) 11a coupling, shown SATA HBA 11a is via the host port 14a coupling of SATA link 11b and SATA switch 14, described system 10 also comprises main frame 12, shown main frame 12 and SATA HBA 12a coupling, shown SATA HBA 12a is via SATA link 12b and SATA switch 14 host port 14b coupling.The device port 14c of the SATA switch 14 that illustrates is via 16 couplings of SATA link 16a and memory cell, described memory cell such as hard disk drive (HDD) or magnetic tape station or the CD-ROM drive.Described memory cell 16 is examples of equipment.

Select signal 15 to select the host port 14a or the host port 14b of SATA switch 14.To be considered as effective port with the port of the main frame coupling of current selection on the SATA switch, and the port that will be not be coupled with the main frame of current selection is considered as invalid port.Effectively main frame is represented current selecteed main frame as used herein.

Can use two kinds of methods to select effective port, they are: band port is selected and is selected based on the port of agreement.In the band port system of selection, SATA switch 14 optionally is coupled to equipment 16 with main frame 11 or main frame 12 based on the state of selecting signal 15.Be used to generate and select the mechanism of signal 15 to depend on system.Select invalid host port is used the SATA agreement based on the port of agreement, so that make switch become effectively.Described port based on agreement selects to use the sequence of SATA OOB signal to select effective port.Above-mentioned method only allows individual host at any preset time of storage unit access.This type of SATA switch is called simple fault-free (failover) switch.

Fig. 3 b shows the system applies of SATA to ATA switch 64.SATA to ATA switch 64 comprise with the sata port 64a of main frame 11 coupling, with the sata port 64b of main frame 12 couplings and with the ata port 64c of memory cell 66 couplings.In system 60, described memory cell 66 has the ATA link, and ata port 64c is coupled via ATA link 66a and memory cell 66.

If break down then system switches to and uses simple fault-free switch in the application of the second standby main frame at first main frame, called after fault-free switch simply thus.In the system of these types, the operation of system is interrupted and " glitch " occur.Obviously, when breaking down, can't stand the continuous system operation of task key (mission-critical) system requirements of fault.The task key system requires two main frame concurrent access memory cell thus, therefore, the task key system can't use simple fault-free switch, and is to use the memory cell of dual-port, and wherein said memory cell can be simultaneously accessed from two ports.Fiber channel (FC) hard disk drive (HDD) is the memory cell of typical dual-port, and is normally used for the task key system.Typically, FC HDD is than the expensive several magnitude of SATAHDD.Yet the ATA of use less expensive or SATA HDD's is economic needs in the memory cell of the key system of task.Yet ATA or SATA HDD are single port, and simple fault-free switch mustn't be by multiple host concurrent access memory cell.

Therefore, need the electron exchanger of permission by the equipment of host access such as memory cell, wherein allow to come concurrent access single port memory cell from two or more host ports via SATA link or ATA link, wherein said single port memory cell links to each other with the device port of switch.

The SATA switch will produce the additional delay in the signal path, can produce the timing requirement that fault meets the SATA agreement timing necessary condition that is used for signal path thereby do like this.SATA switch for having the exchange additional delay need meet the timing requirement of SATA agreement.According to the context relation of recording and narrating, " main frame " used herein refers to the main frame 11 or 12 of Fig. 3 a and 3b.Similarly, " equipment " used herein refers to the equipment 16 of Fig. 3 a and 3b.

The SATA switch of prior art

The simple fault-free switch of prior art systems is carried out exchange in 1 layer.Fig. 4 shows the block diagram of the simple fault-free switch (SFX) 100 of the prior art that exchanges in 1 layer.The switch 100 that illustrates comprises PL circuit 111, PL circuit 121, PL circuit 131, effectively main frame is selected circuit 141, multiplexer 142 and exchange initializing circuit 144.PL circuit 111,121 and 131 is modified models of PL circuit 51 (shown in Fig. 2 b), is used to provide OOB signal and control signal 111i, 121i and 131i, and the latter is respectively PL circuit 111,121 and 131 number control signal is provided.PL circuit 111 is configured to be connected to main frame, and links to each other with the differential received signal 111rx of input with output high speed differential transmission signal 111tx.The link of PL circuit 111 receives bus 112r and links to each other with multiplexer 142.

The link of PL circuit 111 sends bus 112t and links to each other with the link reception bus 132r of PL circuit 131, and the OOB signal 111o of PL circuit 111 selects circuit 141 to link to each other with exchange initializing circuit 144 with effective main frame, and the Phy ISM control signal 111i of PL circuit 111 links to each other with exchange initializing circuit 144.The PhyTxEn 111en signal of PL circuit 111 selects circuit 141 to link to each other with effective main frame.PL circuit 121 is configured to be connected to main frame, and sending signal 121tx with the output high speed differential links to each other with the differential received signal 121rx of input, the link of PL 121 receives bus 122r and links to each other with multiplexer 142, the link of PL circuit 121 sends bus 122t and links to each other with the link reception bus 132r of PL circuit 131, and the OOB signal 121o of PL circuit 121 selects circuit 141 to link to each other with exchange initializing circuit 144 with effective main frame.The Phy ISM control signal 121i of PL circuit 121 links to each other with exchange initializing circuit 144.The PhyTxEn signal 121en of PL circuit 121 selects circuit 141 to link to each other with effective main frame.PL circuit 131 is configured to be connected to equipment, and send signal 131tx with the output high speed differential and link to each other with the differential received signal 131rx of input, the link of the link reception bus 132r of PL circuit 131 and the link transmission bus 112t of PL circuit 111 and PL circuit 121 sends bus 122t and links to each other.The link of described PL circuit 131 sends bus 132t and links to each other with the output of multiplexer 142, and the OOB signal 131o of PL131 links to each other with exchange initializing circuit 144, and the Phy ISM control signal 131i of PL circuit 131 links to each other with exchange initializing circuit 144.The PhyTxEn signal 131en of PL circuit 131 selects circuit 141 to link to each other with effective main frame, and perhaps as what select, it is set to a level so that start the transmitter of PL circuit 131 transmitters (not shown among Fig. 4).

Effectively main frame selects circuit 141 to comprise SFX port selection testing circuit 141a and SFX port selection testing circuit 141b.Described SFX port is selected testing circuit 141a monitoring COMRESET port whether to occur and is selected sequence, and when detecting port selection sequence, circuit 141a generates index signal.According to the specific timing requirement of determining from the next COMRESET signal of being determined to of a COMRESET signal, it is a series of COMRESET signals that the SATA agreement is selected sequence definition with port.

There is not effective host port of selecting when powering on.A COMRESET or its effective main frame of host port conduct of COMWAKE selective reception from the host port reception.On invalid host port, receive based on the port of agreement and select the signal order to cause effective main frame to select circuit 141 at first to cancel current effective host port, select to receive the host port of selecting signal then thereon.PhyTxEn signal by invalid port is set to predetermined level invalid main frame is changed to the dormancy power rating.

Described effective main frame is selected circuit 141 to generate multiplexer and is selected signal 141s, is used for selecting an output that directly arrives multiplexer of two input signals, as its output.Described effective main frame selects circuit 141 also to generate the first main frame useful signal 141h1, when this signal is in ' height ' or logical one state, shows that the main frame that links to each other with PL circuit 111 is effective main frame.Described effective main frame selects circuit 141 also to generate main frame useful signal 141h2, when this signal is in ' height ' or logical one level, shows that the main frame that links to each other with PL circuit 121 is effective main frame.

Described exchange initializing circuit 144 receives and comes from the OOB signal 111o of PL circuit 111, the OOB signal 131o that comes from the OOB signal 121o of PL circuit 121 and come from PL circuit 131.Described exchange initializing circuit 141 generates PhyISM control signal 111i, the Phy ISM control signal 121i and the PhyISM control signal 131i of PL circuit 121 of PL circuit 111, so that carry out following function:

-relaying (receive then send) COMRESET from effective host port to device port.

-slave unit port is to the relaying COMINIT of effective host port.

-slave unit port is to the relaying COMWAKE of effective host port.

-slave unit port is to the relaying COMWAKE of effective host port.

-slave unit port detects to the relaying ALIGN primitive of effective host port.

-relay host ALIGN primitive from effective host port to device port detects.

The trunking port PHYJRDY of-extremely effective host port.

-slave unit port is to the relaying SYNC primitive of effective host port.

In order to illustrate, when signal 131rx and 131tx were linked to each other with equipment, device port was a circuit 131 in the example.Similarly, when signal 111tx and 111rx were linked to each other with main frame, an example was that host port is a circuit 111.Significantly, another example is that host port is a circuit 121 when signal 121tx and 121rx are linked to each other with main frame.

Such as being in one of the problem of the prior art systems shown in this: described switch 100 causes the delay in the signal path between effective host port and the device port, so can't satisfy the timing requirement of SATA agreement.Especially, according to the SATA consensus standard, HOLD/HOLD-ACKNOWLEDGE (HOLD/HOLDA) handshaking that is used for flow control has been stipulated the maximum delay of 20 double words.Additional switch 100 causes satisfying the timing requirement of 20 double word maximum delays in the signal path between effective host port and device port.

Thus, described switch 100 causes the additional delay in the signal path, may make the timing of signal path can't satisfy the timing necessary condition of SATA agreement thus, and especially, the HOLD/HOLDA handshaking postpones should not surpass 20 double words.

Need be coupling in the switch between a plurality of main computer units and the equipment, be used to arbitrate the communication between them, described switch was associated with time of delay, wherein no matter the delay of switch how, all can be satisfied the timing requirement of SATA agreement.

Described SATA switch 100 mustn't invalid host access equipment.Need electron exchanger to allow from two host ports via SATA link or ATA link the single port memory cell to be carried out concurrent access, wherein said single port memory cell links to each other with the device port of switch.

Summary of the invention

Say that tout court embodiments of the invention comprise the switch with the first serial ATA port that is coupled with first main computer unit, described first port comprises the first host task file.Described switch comprises also and the second serial ATA port of second main computer unit coupling that described second port comprises the second host task file.Described switch comprises also and the 3rd serial ATA port of memory cell coupling that described the 3rd port comprises the equipment task file.Described switch comprises arbiter in addition, when existence comes from one of them the indication of at least one unsettled order of many main computer units, one of them that is used to select a plurality of main computer units is via switch and memory cell coupling, wherein when one of them and the memory cell coupling of a plurality of main computer units, another of a plurality of main computer units sends ata command to switch, so that carried out by memory cell.

The accompanying drawing invention

Fig. 1 a shows the SATA protocol communication layer of prior art.

Fig. 1 b shows the example of prior art SATA frame structure.

Fig. 1 c shows the example of mask register piece of the SATA of prior art.

Fig. 1 d shows the prior art FIS structure of SATA agreement.

Fig. 2 a shows the block diagram of the prior art sata port that comprises agreement 1-4 layer.

Fig. 2 b shows the block diagram of the prior art sata port of some circuit that comprise in each protocol layer.

Fig. 3 a shows the prior art system of SATA switch and uses.

Fig. 3 b shows SATA and uses to the prior art system of ATA switch.

Fig. 4 shows the example at the simple fault-free switch of the prior art of 1 layer of exchange.

Fig. 5 for example understands simple fault-free switch 2 layers of exchange according to embodiments of the invention.

Fig. 6 shows the block diagram according to the switch of the embodiment of the invention.

Fig. 7 a shows the arbitration of Fig. 6 switch and the block diagram of control circuit.

Fig. 7 b shows the block diagram of the Tag/Sactive mapping circuit 341 of Fig. 7 a.

Fig. 7 c shows the multiplexed-decomposer 353 and the multiplexed-decomposer 354 of Fig. 6 switch.

Fig. 8 a shows the operational flowchart of 300 pairs of queue command of leaving over of switch of Fig. 6.

Fig. 8 b shows the operational flowchart of the switch of Fig. 6 to the local queue order.

Fig. 9 for example understands the block diagram of the 3 grades of ports of SATA that use in according to effective switch embodiment of the present invention.

Figure 10 a and 10b for example understand the effective switch according to alternative embodiment of the present invention.

Multiplexed-decomposer the 543a of the switch of for example clear Figure 10 a of Figure 10 c and 10b and the embodiment of multiplexer 543b.

Figure 11 a and 11b for example understand the embodiment to the ATA switch according to effective SATA of the embodiment of the invention.

Figure 12 shows the embodiment according to clear and definite (route aware) the FIS structure of the route of another embodiment use of this switch.

Embodiment

Referring now to figure _ _, the method for employing has been used 2 grades of sata ports of main frame and device port and the FISFIFO between host port and the device port in one of embodiment of the invention, to prevent any data loss.Described 2 grades of sata ports HOLD/HOLDA that makes an immediate response, rather than relaying primitive and wait come from the response of another port.Fig. 5 shows according to the embodiment of the invention, the high level block diagram of the switch 200 of exchange in 2 layers.The switch 200 that illustrates comprises 2 grades of host ports 210 of SATA, 2 grades of host ports 220 of SATA, 2 grades of device ports 230 of SATA, FIS load FIFO 245, multiplexer 242a, multiplexer 242b, demultiplexer 243, effectively main frame is selected circuit 241 and exchange initializing circuit 244.

Described FIS FIFO 245 comprises circuit based on dual port FIFO, and this FIFO has FIS FIFO input port 245 (i1), FIS FIFO output port 245 (o1), FIS FIFO input port 245 (i2) and FIS FIFO output port 245 (o2).

2 grades of host ports 210 of described SATA comprise PL circuit 211 and LL circuit 212, and send signal 211tx with the output high speed differential and the differential received signal 211rx of input links to each other, and comprise transmission receive bus 213r, transmission transmission bus 213t, from the transmission control/status bus 213co of link layer 212 generations and the control/status bus 213ci that is sent to link layer 212.Transmission receives bus 213r and links to each other with multiplexer 242a.The control that illustrates/status bus 213co links to each other with multiplexer 242b, the transmission that illustrates sends bus 213t and links to each other with FIS FIFO output port 245 (o1), and the OOB signal 211o that illustrates selects circuit 241 to link to each other with exchange initializing circuit 244 with effective main frame.Exchange initializing circuit 244 generates Phy ISM control signal 211i.

2 grades of host ports 220 of the SATA that illustrates comprise PL circuit 221 and LL circuit 222, and link to each other with the differential received signal 221rx of input with output high speed differential transmission signal 221tx.The port 220 that illustrates comprises that transmission receives that bus 223r, transmission send bus 223t, the transmission control/status bus 223co that generates from link layer 222 and the control/status bus 223ci that is sent to link layer 222.Described transmission receives bus 223r and links to each other with multiplexer 242a, described control/status bus 213co links to each other with multiplexer 242b, described transmission sends bus 223t and links to each other with FIS FIFO output port 245 (o21), and the described OOB signal 221o that illustrates selects circuit 241 to link to each other with exchange initializing circuit 244 with effective main frame.Described exchange initializing circuit 244 generates Phy ISM control signal 221i.

2 grades of device ports 230 of described SATA comprise PL circuit 231 and LL circuit 232, and link to each other with the differential received signal 231rx of input with output high speed differential transmission signal 231tx.The port 230 that illustrates comprises that transmission receives that bus 233r, transmission send bus 233t, the transmission control/status bus 233co that generates from link layer 232 and the control/status bus 233ci that is coupled to link layer 232.Described transmission receives bus 233r and links to each other with FIS FIFO input port 245 (i2), and described control/status bus 233ci links to each other with the output of multiplexer 242b, and transmission sends bus 233t and connects FIS FIFO output port 245 (o2).Control/status bus 233co is provided the input as demultiplexer 243, and described OOB signal 231o selects circuit 241 to link to each other with exchange initializing circuit 244 with effective main frame.Described exchange initializing circuit 244 generates Phy ISM control signal 231i.

Described effective main frame selects circuit 241 to select circuit 141 identical with effective main frame of Fig. 4.The SFX port of Fig. 5 selects testing circuit 241a to select testing circuit 141a identical with 141b with port respectively with 241b.Described effective main frame selects circuit 241 to generate to be used to select the multiplexed selection signal 241s that imports, and it is placed on the output of multiplexer 242a and multiplexer 242b.Described effective main frame selects circuit 241 also to generate when effective or show host port 210 effective main frame useful signal 141h1 when being in logic state 1 '.Described main frame selects circuit 241 also to generate when effective or show host port 220 effective main frame useful signal 141h2 when being in logic state 1 '.Described main frame useful signal 141h1 and 142h2 serve as the input of demultiplexer 243, and route control/status bus 233co is to effective main frame.

Exchange initializing circuit 244 is identical with the exchange initializing circuit 144 of Fig. 4.The function of being carried out by exchange initializing circuit 244 can be given PL circuit 211,221 and 231.Similarly, can select testing circuit 241a and 241b to give PL circuit 211 and 221 respectively the SFX port.Distribute the optional embodiment of the function of exchange initializing circuit 244 to PL circuit 211,221 and 231, perhaps distribute the SFX port to select the optional embodiment of the function of testing circuit, all fall within the scope of the present invention to PL circuit 211 and 221.

Though 2 layer switch 200 of Fig. 5 have been eliminated the timing problems that is caused by switch 200 delays, switch 200 can't allow two main frames to use standard FIS structures via the SATA link single port equipment to be conducted interviews.

In order to allow two host access single port equipment,, must adopt multichannel multiplexing method according to alternate embodiments of the present invention.Traditional multichannel multiplexing method is a time division multiplexing.In time division multiplexing,, grant that a main frame or another main frame are conducted interviews for alternate cycle (the equal or different times).Because the order in processing interrupts having caused performance to reduce or loss of data, so can't use traditional time division multiplexing together with memory cell.

To be used for multichannel multiplexing method of the present invention is called multiplexed based on what order.Based on the order multiplexed in, switch knows idle condition (do not have order handle), order, order in handling finish with unsettled order (because order is underway and equipment is just busy, so reception and memory command but do not send to equipment), use this information, switch can realize being used to provide the algorithm of two host access equipment.

Based on the order multiplexed requirement 4 layers of processing.Compare with the SATA switch of carrying out the prior art of exchange at 1 layer, adopt based on the multiplexed SATA switch of the present invention of order and carry out exchange (" 4 layer switch ") at 4 layers.In SATA switch of the present invention, be used for being used to select and sending the main frame of ordering to equipment based on the arbitration algorithm of circular priority (rotating priority).When existence comes from the unsettled order of two main frames, the main frame with limit priority will begin to send its order to equipment.

In the operation of power-up initializing, at random give in main frame 11 or 12 one with priority.The SATA switch of different embodiments of the invention is known described priority and is carried out arbitration to select to send to equipment the main frame of order.When the equipment input was used to accept another coomand mode, the switch of different embodiments of the invention changed priority and gives another main frame.

Fig. 6 shows the block diagram according to effective switch 300 of alternative embodiment of the present invention.The switch 300 that illustrates comprises SATA4 level host port 310,4 grades of host ports 320 of SATA, 4 grades of device ports 330 of SATA, arbitration and control circuit 340, multiplexer 351, multiplexer 352, multiplexed-decomposer 353 and multiplexed-decomposer 354.4 grades of host ports 310 of the SATA that illustrates send signal 311tx with the output high speed differential and link to each other with the differential received signal 311rx of input, and comprise main frame 11 layer order input bus 315i, main frame 11 layer order output bus 315o, main frame 11 assignment file input bus 316i and main frame 11 assignment file output bus 316o.4 grades of host ports 320 of the SATA that illustrates send signal 321tx with the output high speed differential and link to each other with the differential received signal 321rx of input, and comprise main frame 12 layer order input bus 325i, main frame 12 layer order output bus 325o, main frame 12 assignment file input bus 326i and main frame 12 assignment file output bus 326o.4 grades of device ports 330 of the SATA that illustrates send signal 331tx with the output high speed differential and link to each other with the differential received signal 331rx of input, and comprise device command layer input bus 335i, device command layer output bus 335o, equipment task file bus in 336i and equipment task file output 336o.

The main frame 11 layer order output bus 315o that illustrate link to each other with the first input end of multiplexer 351.The main frame 12 layer order output bus 325o that illustrate link to each other with second input of multiplexer 351, and multiplexer 351 outputs that illustrate link to each other with device command layer input bus 335i.The main frame 11 assignment file output bus 316o that illustrate link to each other with the input of multiplexer 352, and the main frame 12 assignment file output bus 326o that illustrate link to each other with the input of multiplexer 352.Arbitration and control circuit 340 generate Equipment Control assignment file output bus 352i, the latter and then link to each other with an input of multiplexer 352 again, as shown in Figure 5, and also generate control signal 352s, described control signal 352s is the control signal of multiplexer 352.Multiplexer 352 outputs that illustrate link to each other with equipment task file bus in 336i.In some cases, the function of bus 352i comes from the data of main frame with replacement, and after this this will describe.

The device command layer output bus 335o that illustrates links to each other with the input of demultiplexer 353.The equipment task file bus out 336o that illustrates links to each other with the input of demultiplexer 354.Arbitration and control circuit 340 receive main frame 11 assignment file output bus 316o, main frame 12 assignment file output bus 326o and equipment task file bus out 336o.Arbitration and control circuit 340 generate the selection signal 351s that is used to control multiplexer 351 operations.Described arbitration and control circuit 340 generate control command layer output bus 353i, and this control command layer output bus 353i links to each other with the input of multiplexed-decomposer 353.Circuit 340 also generates control signal 353c, and described control signal 353c is the control signal of multiplexed-decomposer 353.In some cases, the function of bus 353i comes from the data of equipment with replacement, and after this this will describe.

Described arbitration and control circuit 340 generate control task file bus out 354i, and this output bus 354i links to each other with an input of multiplexed-decomposer 354, as shown in the figure, and the operation of the multiplexed-decomposer 354 of control signal 354c control.In some cases, the function of bus 354i is with replacement equipment assignment file output bus 336o, and after this this will discuss.

Referring now to Fig. 7 c,, described multiplexed-decomposer 353 has two input 335o, 353i, and two output 315i, 325i.Multiplexed-decomposer 353 is carried out two functions, first function is to select one of two inputs (multiplexed), second function be with one of selected two inputs route to selected multiplexed-one of the output of decomposer 353, and the output that do not select of multiplexed-decomposer 353 is set to invalid voltage level (multichannel decomposition).Described control signal 353c is used to control the multiplexed and multichannel decomposition function of multiplexed-decomposer 353.

Described multiplexed-decomposer 354 has two input 336o, 354i and two output 316i and 326i.Multiplexed-decomposer 354 is carried out two functions, its first function is to select one of two inputs (multiplexed), its second function be with one of selected two inputs be sent to selected multiplexed-one of the output of decomposer 354, and the output that do not select of multiplexed-decomposer 354 is set to invalid voltage level (multichannel decomposition).Described control signal 354c is used to control multiplexed and the multichannel decomposition function.

The operation of switch 300 requires switch 300 to know order in the processing, and handles some order that is different from other orders.Arbitration and control circuit 340 receive main frame 11 assignment files via main frame 11 assignment file output bus 316o.Described circuit 340 also receives main frame 12 assignment files via main frame 12 assignment file output bus 326o, and via equipment task file bus out 336o receiving equipment assignment file, and receiving equipment layer order output bus 335o.

Except that arbitration, arbitration and control circuit 340 are known order and the unsettled order in the processing, and revise load data or FIS under some particular case.Under specific circumstances, in the time must changing data payload, arbitration and control circuit 340 generate alternate data, and provide alternate data on the control command layer output bus 353i and the value on the control signal 353c so that select output bus 353i, one of input signal of wherein said control command layer output bus 353i and multiplexed-decomposer 353 links to each other.Under specific situation, in the time must changing non-data FIS, in the time of perhaps must sending brand-new non-data FIS, arbitration and control circuit 340 generate corresponding alternative tasks file, and provide alternative tasks file on the control task file bus out 354i and the value on the control signal 354c so that select output bus 354i, one of input signal of wherein said control task file bus out 354i and multiplexed-decomposer 354 links to each other.

The particular case that requires slave unit to change data payload comprises the situation that driving responds of discerning, and it is to respond the identification driving that comes from main frame to order and generate that described identification drives response.Described identification drives the data that response comprises 512 bytes (256 words), is used to provide the predetermined properties of equipment.

Especially, identification drives response and comprises and be used to support to line up and the capacity of equipment of queue depth.As an example, the 1st bit table of the word 83 of identification driving response is bright: whether support read/write DMA queue command (those skilled in the art are known), and that identification drives the 8th bit table of word 76 of response is bright: whether support local queue order (those skilled in the art are known), and identification drives the 0th to 4 of word 75 of response and comprises that queue depth subtracts 1 value.

In an application, can drive response by intercepting identification, use 0 the 8th of replacing the queue depth's value and the word 76 that resets to come the decretum inhibitorium queuing.In effective switch of supporting queuing was used, the queue depth that reports to every main frame must be changed, thus main frame not the transmitting apparatus support not more orders.

In the embodiment of Fig. 5, arbitration and control circuit 340 are intercepted the identification driving response that slave unit sends, and use newly-generated value to replace original value among the 0th to 4 of word 75, wherein said newly-generated value representation queue depth value, it is original queue depth value half.

Represent in the situation of odd number value of queue depth at original value, new numeric representation queue depth value, this value is that original queue depth value cuts half after 1.As mentioned above, the value representation queue depth value in the 4th of word 75 the to 0 (75[4:0]) (this note is represented the 0th to 4 of 16 words 75) subtracts 1.Generate 75[4:0] the operation of new numerical value by the 75[4:0 that is shifted by turn] original value carry out, if 75[4:0 then] original value represent that even number value (minimum significance bit (75[0]) is zero), cut 1 so conditionally.Described arbitration and control circuit 340 generate new numerical value on control command layer output bus 353i, and according to being chosen in of bus 353i this value are set on the control signal 353c, and it is decomposed by multichannel, then as input provide to multichannel multiplexing-decomposer 353.

The word 255 that identification drives response is complete words.The use of this word is arbitrarily.If the 7th to 0 of word 25 (255[7:0], (this note is represented the 0th to 7 of 16 words) comprise value A5 (according to hexadecimal notation), so the 15th of word 255 the to 8 comprise verification and, described verification and be in the word 0 to 254 all bytes with comprise the 0th to 7 byte in the word 255 and two.When use verification and and arbitration and control circuit when revising part identification and driving response, arbitration and control circuit are revised verification and in addition so that reflect correction value, generate then new verification and, and it is provided on the control command layer output bus 353i, and the value on the control signal 353c is set so that select bus 353i.

The operation of leaving over effective switch of lining up with local command that is used to support the SATA agreement is described now.Yet, at first provide the Short Description of lining up of leaving between main frame and the equipment with local command.

Regardless of queue depth, the read/write DMA queue command of leaving over (LQ CMD) comprises the main frame mark of the value that has between decimal integer 0 and 31.The number of the unsettled read/write DMA queue command of leaving over can not surpass queue depth.If main frame sends the LQ CMD order with invalid main frame mark value, equipment responds with error condition so.The example of this situation is when surpassing queue depth.After main frame sent LQ CMD order, host waits came from the response of equipment to it.The response that comes from equipment comprises following situation:

-equipment transmitter register FIS 40 (ii), the REL position of (equaling logical one) register FIS40 in (ii) wherein is set, and the SERV position of register FIS 40 in (ii) resetted (equaling logical zero), command queuing and order are " released " to show equipment." release " is such a case, wherein in queued command so that equipment disconnects and (" disconnection ", " connection " and " reconnecting " definition in the serial ATA standard to be incorporated in this after the subsequent treatment, for your guidance), and the time afterwards reconnect to finish described order.When release command, the short of queue depth that surpasses just allows main frame to send the read/write DMA queue command that another is left over.

-equipment transmitter register FIS 40 (ii) wherein is provided with REL position and the SERV position of register FIS 40 in (ii), and showing described equipment by command queuing, and the service queue order is ready.

-described equipment sending data FIS 40 (vii) or DMA start FIS 40 (iii) to show that equipment carrying out described order;

-described equipment transmitter register FIS 40 (ii), make a mistake so that show in the BSY position of reseting register FIS 40 in (ii) wherein, and the ERR position of register FIS 40 in (ii) is set; Perhaps

-when device ready reconnects to main frame, described equipment to main frame send be provided with equipment position FIS 40 (v) or register FIS 40 (ii), wherein be provided with equipment position FIS 40 (v) or the SERV position of register FIS 40 in (ii) be set up.Described main frame responds this with the SERVICE order, and equipment (ii) sends back to register FIS 40 main frame that comprises the main frame mark value.In this, reconnect main frame and equipment and recovery command execution.When equipment has the non-empty queue of the queue command of leaving over, if main frame sends non-queue command or local queue order, abnormal ending queue command so.

Under the situation of local queue order (NQ CMD), the main frame mark value be limited to 0 and queue depth subtract value between 1 (queue_depth_minus_one).After main frame sent the local queue order, the register FIS 40 that host waits comes from equipment (ii).If reseting register FIS 40 is BSY position and DRQ in (ii), the register FIS that comes from equipment so shows that described order is lined up, and described order is released.If the BSY position of reseting register FIS40 in (ii), and the ERR position of register FIS 40 in (ii) is set, the register FIS 40 that comes from equipment so (ii) shows and makes a mistake.If release command, the so short of queue depth that surpasses, main frame just can send another local queue order.When device ready when reconnecting to main frame, described equipment sends DMA and sets up FIS40 (iv), it comprises the main frame mark value.

In this, reconnect main frame and equipment and recovery command execution.Described equipment (v) is sent completely state via equipment position FIS 40 is set.Equipment position FIS 40 is set, and (Sactive field 40 v) (v) (ii) have 32, and every corresponding to a mark (position is 0 corresponding to mark value 0, and position 1 is corresponding to mark value 1 or the like).((v) the bit table that is provided with in (ii) reveals corresponding queue command and is done Sactive field 40 v) in that equipment position FIS 40 is set.If equipment position FIS 40 is not set, and (the ERR position v), so described order is successfully finished under situation about not making a mistake.When equipment has the non-empty queue of local queue order, if main frame sends non-queue command or leaves over queue command, abnormal ending queue command so.

Because two main frames can use identical mark value, so switch maps to different values with the main frame mark value, can distinguish when reconnecting equipment with box lunch.When the switch of one embodiment of the present of invention receives queue command, the main frame mark is mapped to unique device flag, so make when reconnecting equipment, can identify main frame and origin host mark.

Leaving under the situation of queue command, equipment position FIS 40 is set (equipment that the is provided with position FIS 40 of the SERV position v) (v) when switch 300 slave units receive wherein to be provided with, perhaps receive the register FIS40 (ii) time the wherein be provided with the SERV position of register FIS 40 in (ii), because the Command Flags value that need serve of equipment still is not effectively, thereby switch 300 can not pass on and equipment position FIS 40 is set (v).In order to obtain mark value, switch 300 sends service command to equipment, and equipment (ii) responds with the register FIS 40 that comprises mark.Then, switch 300 remaps mark so that identification main frame and origin host mark value.If do not come from the unsettled queue command of leaving over of main frame in switch 300, under the situation of having set the SERV position, switch sends to main frame and equipment position FIS40 is set (v) so.If in switch, there is the unsettled queue command of leaving over, so switch 300 with described demanded storage in built-in storage 344, and when device ready discharges unsettled when leaving over queue command, described equipment (ii) responds with register FIS 40, wherein is provided with REL position and the SERV position of register FIS 40 in (ii).When main frame responded with service command, switch 300 (ii) responded with the register FIS 40 that comprises the origin host mark value.

Under the situation of local queue order, when receiving the DMA that comes from equipment, switch 300 sets up FIS 40 (vi) the time, switch 300 is at first set up FIS 40 at DMA, and (the described mark that vi) remaps in (ii) is so that identification main frame and origin host mark value, (vi) (ii) transfer to the main frame that identifies, wherein said DMA installs FIS40 and (vi) (ii) has the mark that replaces with the origin host mark then DMA to be set up FIS 40.

Under the situation of local queue order, when switch 300 receives the equipment that the is provided with position FIS 40 that comes from equipment (v) the time, the wherein said equipment position FIS 40 that is provided with (v) comprises Sactive field 41 (Fig. 1 d (v)) that shows local queue order completion status, switch 300 generates main frame 11 Sactive fields and main frame 12 Sactive fields, so make main frame 11sactive field include only the mark in the Sactive field 41 that belongs to main frame 11 (shown in Fig. 3 a), and main frame 12sactive field include only the mark in the Sactive field 41 that belongs to main frame 12 (shown in Fig. 3 a).Switch 300 under the situation that replaces the Sactive field with main frame 11sactive field, will be provided with equipment position FIS 40 (v) transfer to main frame 11 (shown in Fig. 3 a), simultaneously under the situation that replaces Sactive field 41 with main frame 12 Sactive fields, equipment position FIS 40 will be set (v) transfer to main frame 12 (shown in Fig. 3 a).

Fig. 8 a shows the operational flowchart of 300 pairs of queue command of leaving over of switch of Fig. 6.

In idle condition 361, leave over queue command or unsettled assignment file, have the unsettled queue command 362 of leaving over if received from arbitrary main frame, switch 300 is changed into main frame selection mode 363 with state so.Otherwise (v) or register FIS 40 (ii) 372, switch 300 is changed into state and is sent service state (send-the-service state) 373 so if slave unit has received and has the equipment that the is provided with position FIS 40 that is provided with the SERV position.Otherwise switch remains on idle condition 361.

In main frame selection mode 363, switch 300 is arbitrated between main frame, and selects its unsettled order will be transferred to the main frame of equipment subsequently.Described unsettled order comprises the main frame mark of selection.Then, switch 300 is changed into the LQ CMD state 364 that sends with state.

In sending LQ CMD state 364, switch 300 at first maps to the transmitting apparatus mark with selected LQ main frame mark, replaces the LQ main frame mark of selecting with the transmitting apparatus mark, passes on unsettled order to equipment then.Then, switch 300 is changed into waiting facilities responsive state 365 with state.Described transmitting apparatus mark refers to the mark of the equipment that sent to by switch 300.

In waiting facilities responsive state 365, if received device responds, switch 300 is changed into inspection machine responsive state 366 with state so.Otherwise switch 300 keeps waiting facilities responsive state 365.In inspection machine responsive state 366, if device responds be provided with REL position and SERV position in (ii) at register FIS 40 register FIS40 (ii), switch 300 changes state into and disconnects/reconnect state 366b so.Otherwise, if device responds be provided with the REL position and the register FIS40 of the SERV position that resets (ii), switch 300 changes state into off-state 366d so.Otherwise, if device responds be data FIS 40 (vii) or DMA start FIS 40 (iii), switch 300 changes state into executing state 366f so.Otherwise, if device responds be provided with the ERR position register FIS 40 (ii), switch 300 changes state into error condition 366h so.Otherwise switch changes state into removing state 366j, and removes the FIS that is received, and changes state into idle condition 361.

Disconnect/reconnecting among the state 366b, switch 300 send be provided with the REL position and the register FIS 40 of the SERV position that resets (iii) so that select main frame, then state is changed into the service CMD state 373 that sends.In off-state 366d, switch 300 sends to selected main frame and is provided with the REL position and the register FIS of the SERV position that resets, and then state is changed into idle condition 361.

In executing state 366f, switch 300 is waited for finishing of the current command, and described the current command is the order that is sent out in sending LQ CMD state 364.After completing successfully the current command, switch 300 changes state into idle condition 361.Otherwise, stopping the current command because of wrong, switch 300 changes state into error condition 366h then.In error condition 366h, switch 300 error process, and after finishing fault processing, change state into idle condition 361.

In sending service CMD state 373, switch 300 sends service CMD to equipment, and changes state into waiting facilities flag state 374.

When being in waiting facilities flag state 374, if received device responds, switch 300 changes state into the state of remapping 375 so, otherwise switch 300 keeps waiting facilities flag state 374.In the state of remapping 375, the device flag that switch 300 remaps and receives, described mark is by receiving in switch 300 slave units, so that identification main frame and origin host mark, and switch 300 utilizes described origin host mark to replace the receiving equipment mark.If have pending queue in the host task file that identifies, switch 300 changes state into preservation state 376b so, otherwise switch 300 changes state into and reconnects to Host Status 376a.Reconnecting to Host Status 376b, switch 300 sends the equipment that the is provided with position FIS 40 that is provided with the SERV position to the main frame that identifies (main frame that identifies in the state 375 that remapping) and (v), then state is changed into the response of host state 377 of waiting for.

In waiting for response of host state 377, if received the response of host of identification, switch 300 changes state into check response of host state 378 so, otherwise switch 300 keeps waiting for response of host state 377.In check response of host state 378, if response of host is a service command, switch 300 changes state to send into and is tagged to Host Status 378b so, otherwise, if response of host is another LQ CMD, switch 300 changes state into pending status 378e is set so, and not so, switch 300 changes state into wrong 2 state 378d.

Be tagged among the Host Status 378b in transmission, switch 300 sends the register FIS with origin host mark to the main frame that identifies, and changes state into the state of reconnecting 379.In pending status 378e was set, switch 300 was provided with the CMD of pending queue sign so that show that main frame has sent another and left over queue command.In preservation state 376b, switch 300 is stored in the assignment file of the main frame that identifies in the unsettled assignment file, sends the register FIS 40 that is provided with the SERV position and is provided with the REL position (v) to the main frame that identifies then.

Disconnect/reconnecting among the state 366b, be tagged to Host Status 378b, revise FIS or new FIS sends to main frame reconnecting to Host Status 376a, preservation state 376b and transmission.The assignment file that arbitration and control circuit 340 generate corresponding to the FIS (perhaps new FIS) that revises, and send it on the control task file bus out 354i, described control task file bus out 354i links to each other with the input of multiplexed-decomposer 354.Circuit 340 also is provided with the value of control signal 354c, so that select bus 354i, and its multichannel is decomposed with the output as multiplexed-decomposer 354.

In sending LQ CMD state 364, the FIS (perhaps new FIS) that sends service CMD 373, revise is sent to equipment.Arbitration and control circuit 340 generations are corresponding to the assignment file of the FIS of the modification on the Equipment Control assignment file output bus 352i or new FIS, the latter and then link to each other with one of input of multiplexer 352 again, as shown in Figure 5, and the value of selecting signal 352s is set so that select the output of bus 352i, the latter and then link to each other with equipment task file bus in 336i again as multiplexer 352.

Fig. 8 b shows the operational flowchart of 300 pairs of local queue orders of switch (NQ CMD).In idle condition 381, can carry out a plurality of judgements, shown in 382-386.At 382 places, if received the local queue order from arbitrary main frame, and equipment has responded previous NQ CMD, switch 300 changes state into main frame selection mode 382a so, otherwise, at 383 places, if slave unit has received the register FIS of the ERR position that resetted, switch 300 changes state into NQ off-state 383a so.Otherwise, at 384 places,, slave unit sets up FIS 40 (iv) if having received DMA, and switch 300 changes state into the NQ state 384a that remaps so.Otherwise,, equipment position FIS 40 is set (v) if received at 385 places, and at the 385a place, resetting is provided with ERR position among the FIS of equipment position, and switch changes state into NQ stable state 385b so, otherwise if be provided with the ERR position, switch 300 changes state into NQ error condition 386a so.If at 385 places, equipment position FIS is set does not show completion status, at 386 places, if received the device register FIS that is provided with the ERR position, switch 300 changes state into NQ error condition 386a so, otherwise switch 300 keeps idle condition 381.

In main frame selection mode 382a, switch 300 is arbitrated between main frame, and selects its unsettled order will be transferred to the main frame of equipment subsequently in sending NQ CMD state 382b.Then, described switch 300 changes state into and sends NQ CMD state 382b.

In sending NQ CMD state 382b, switch 300 at first maps to the transmitting apparatus mark with selected NQ main frame mark, replace selected NQ main frame mark with the transmitting apparatus mark, pass on to equipment and to send the order that sends among the NQ CMD state 382b, and sign " device_not_responded " is set, and changes state into idle condition 381.Described sign " device_not_responded " shows that equipment does not also respond the local queue order.

In NQ off-state 383a, switch 300 makes register FIS be transferred to selected main frame, and reseting mark " device_not_responded " changes state into idle condition 381 then.In NQ remaps state 384a, switch 300 remaps the receiving equipment mark so that identification main frame and origin host mark, and the origin host mark that uses DMA to set up among the FIS is replaced the receiving equipment mark, and send DMA to the main frame that identifies and set up FIS, and change state into NQ and reconnect state 384b.Reconnect among the state 384b at NQ, the main frame that identifies is reconnected to equipment, and data FIS is transmitted between main frame that reconnects and equipment.Reconnect among the state 384b at NQ, at the 384c place, whether switch 300 check DMA transmission countings are used up.If DMA transmission counting is not used up, switch 300 keeps reconnecting state 384b so, otherwise switch 300 changes state into idle condition 381.In NQ stable state 385b, switch 300 is handled the state of the NQ CMD that completes successfully, and this is by equipment equipment position FIS 40 (report in the Sactive field 41 v) to be set.

Switch 300 generates main frame 11 sactive fields and main frame 12 sactive fields from Sactive field 41, so make main frame 11 sactive fields include only the mark in the Sactive field 41 that belongs to main frame 11, and main frame 12 sactive fields include only the mark in the Sactive field 41 that belongs to main frame 12.Switch 300 will be provided with equipment position FIS and transfer to main frame 11 under the situation that replaces Sactive field 41 with main frame 11 sactive fields, under the situation that replaces Sactive field 41 with main frame 12 sactive fields equipment position FIS will be set then and transfer to main frame 12.Described switch 300 changes idle condition 381 then into.In NQ error condition 386, switch 300 error process, and after finishing fault processing, change state into idle condition 381.

In NQ remaps state 384a and NQ stable state 385b, the FIS that revises is sent to main frame.Arbitration and control circuit 340 generate the assignment file corresponding to the FIS of modification or new FIS, and on control task file bus out 354, send, described control task file bus out 354 links to each other with second input of multiplexed-decomposer 354, and the value on the control signal 354c is set so that selection and multichannel are decomposed bus 354i to selected main frame.

In sending NQ CMD state 364, the FIS that revises is sent to equipment.The assignment file that arbitration and control circuit 340 generate corresponding to the FIS that revises, and on Equipment Control assignment file output bus 352i, send, one of input of described Equipment Control assignment file output bus 352i and multiplexer 352 links to each other, and the value of selecting on the signal 352s is set so that select the output of bus 352i as multiplexer 352, described multiplexer 352 links to each other with equipment task file bus in 336i again.

In one embodiment of the invention, device flag (transmitting apparatus mark and receiving equipment mark) value is divided into two scopes, main frame 11 scopes and main frame 12 scopes.In one embodiment of the invention, main frame 11 scopes comprise the mark from minimum main frame 11 mark value to maximum host 11 mark value, and main frame 12 scopes comprise the mark from minimum main frame 12 mark value to maximum host 12 mark value, wherein minimum main frame 11 mark value are 0, and maximum host 11 mark value equal main frame queue depth and subtract one.Minimum main frame 12 mark value equal main frame queue depth, and maximum host 12 mark value equal 2*host_queue_depth-1, and main frame queue depth is that response identification drives the value that order reports to main frame 11 and main frame 12, and these contents were described previously.

For example, if equipment is supported 32 queue depth, will respond so and discern the main frame queue depth that drives order and report will be 16, and main frame 11 scopes from 0 to 15 are come mark, and main frame 12 scopes are come mark from 16 to 31.In another example, if equipment is supported 31 queue depth, will respond so and discern the main frame queue depth that drives order and report will be 15, and main frame 11 scopes from 0 to 14 are come mark, and main frame 12 scopes are come mark from 15 to 30.Main frame 11 and main frame 12 adopt the alternative embodiment of the different queue degree of depth to belong to scope of the present invention.

Referring to Fig. 7 a, arbitration and control circuit 340 comprise main frame arbiter 343, mark/Sactive mapping circuit 341 and control circuit 342.Comprise by the function that mark/Sactive mapping circuit 341 is carried out:

The main frame mark is mapped to the transmitting apparatus mark, and under the situation of leaving over the formation mark, mapping result is kept in the mark memory, and preserve one and show effect formation mark.

Inverse mapping receiving equipment mark is so that discern main frame and obtain the origin host mark, and under the situation of LQ CMD, when when finishing order by control circuit 342 when directed, the dead queue mark.

Sactive field 41 is mapped to respectively main frame 11 Sactive fields and main frame 12 Sactive fields corresponding to main frame 11 and main frame 12.

Main frame 11 assignment file output bus 316o comprise main frame 11FIS request 318, and it comprises main frame 11 FIS request indication and queue command indication.Described main frame 11 FIS request indication is written to main frame 11 assignment file orders or device control register generates from decoding.Write leaving over of main frame 11 assignment file command registers or local queue order by decoding and generate the indication of main frame 11 queue command.

Main frame 12 assignment file output bus 326o comprise main frame 12 FIS request 328, and it comprises main frame FIS request signal and queue command signal.Described main frame 12 FIS request signals are written to main frame 12 assignment file orders or device control register generates from decoding.Write leaving over of main frame 12 assignment file command registers or the local queue order generates main frame 12 queue command signals by decoding.

The quene state signal 341q that main frame arbiter 343 receives main frame 11FIS request 318, main frame 12FIS request 328, comes from the control signal 343c of control circuit 342 and come from mark/Sactive mapping circuit 341.Response comes from the control signal 343c of control circuit 342, and main frame arbiter 343 generates the main frame that serves as control circuit 342 inputs and selects signal 343hs.Main frame selects the logical zero on the signal 343hs to show that main frame 11 can send order to equipment, and logical one shows that main frame 12 can send order to equipment.Operating in the table 1 of main frame arbitration 343 described.

The function of being carried out by control circuit 342 comprises:

Generation is used to control the selection signal 351s of multiplexer 351 operations;

Generate Equipment Control assignment file output bus 352i, this bus links to each other with the input of multiplexer 352, and generates the selection mark 352s that is used to control described multiplexer 352 operations;

Generate control command layer output bus 353i, its input with multiplexed-decomposer 353 links to each other, and generates the control signal 353c as the control signal of multiplexed-decomposer 353;

The control task file bus out 354i that generation links to each other with the input of multiplexed-decomposer 354, and be used to control described multiplexed-the control signal 354c of decomposer 354 operations;

Generation is used for the control signal 342c of main frame arbiter 343;

Generation is used for the control signal 341ctl of mark/Sactive mapping circuit 341; And

Generate control signal so that the host task file that identifies is kept in the unsettled assignment file 344, and the operation of control multiplexer 354.

Fig. 7 b shows the mark/Sactive mapping circuit that is used for one of embodiments of the invention.Described mark/Sactive mapping circuit 341 comprises mark memory 341d, is used to show whether effectively effectively LQT register 341a, LQT mapping 341b, NQT mapping 341g, NQT oppositely shine upon 341f, device flag multiplexer 341m1 and main frame mark multiplexer 341m2 to corresponding LQT.Described mark/Sactive mapping circuit 341 inputs comprise device flag input 341j, the input of main frame mark 341i, Sactive input 341k, the input 341qd of main frame queue depth and control bus 341ctl.Described mark/Sactive mapping circuit 341 generates and comprises the main frame mark 341dt of mapping, main frame mark 341ht, the main frame 11 Sactive output bus 341s1 of retrieval and some output of main frame 12 Sactive output bus 341s2.

Under the situation of local queue order, with described main frame mark value be limited in 0 and host_queue_depth_minus_one between.Utilize adder/subtracter to realize mapping and inverse mapping.Device flag corresponding to main frame 11 marks is identical with main frame 11 marks, adds main frame queue depth and equal main frame 12 mark value corresponding to the device flag of main frame 12 marks.

This operation of mapping NQ mark is carried out by NQT mapping 341g.Described NQT mapping 341g receives selected main frame mark input 341i and the 341qd of main frame queue depth, and its output is linked to each other with the input of device flag multiplexer 341m1.If selected main frame mark input 341i comes from main frame 11 (signal 341h is a logical zero), the output of NQT mapping equals selected main frame mark input 341i so, main frame mark input 341i comes from main frame 12 (signal 341h is a logical one) else if, and the output of NQT mapping equals selected main frame mark input 341i and adds main frame queue depth so.

The inverse mapping of NQ mark is carried out by NQT inverse mapping 341f.Described NQT inverse mapping 341f receives the input of receiving equipment mark 341j, the 341qd of main frame queue depth, and its output 341int comprises the binary value signal, and described signal is used to discern the main frame that links to each other with corresponding origin host mark value (logical zero show main frame 11 is identified and logical one shows that main frame 12 is identified).Described output 341int links to each other with the input of main frame mark multiplexer 341m2.If 341j is less than the 341qd of main frame queue depth for the input of receiving equipment mark, output equals the logic zero signal (showing main frame 11) that links to each other with device flag input 341j so, deducts the 341qd of main frame queue depth otherwise export the logical one signal (showing main frame 12) that 341int equals to link to each other with receiving equipment mark 341j.

In leaving over the situation of queue command, no matter main frame queue depth how, and the main frame mark value is between 0 and 31.As mentioned above, will distribute to main frame 11 scopes from 0 to host_queue_depth_mmus_one device flag, and will distribute to main frame 12 scopes from host_queue_depth to the device flag of (2*host_queue_depth-1).Mark memory unit 341d is used to store the main frame mark value corresponding to device flag.Because mark memory unit 341d accessed corresponding to receiving equipment marked address place, has reduced the complexity relevant with the function that oppositely mirrors execution so do like this.

Mark memory 341d storage is corresponding to the main frame mark of device flag.In one embodiment of the invention, mark memory 341d has 32 inlets, and the storage of inlet 0 (address 0) is corresponding to the main frame mark of device flag value 0, and main frame mark corresponding to device flag value 1 or the like is stored in inlet 1 (address 1).Not all inlet all is effective in mark memory.Described mark memory 341d has the independently conventional memory of write access port.Described mark memory 341d read access port comprises to be read address port, read gate port and reads output port.Described mark memory 341d write access port comprises writes input port, write address port and write gate port.Described mark memory 341d reads address port and links to each other with receiving equipment mark input 341j, and the read gate port links to each other with control signal 341rd, links to each other with mark memory output bus 341ilt and read output port.The output of described mark memory 341d write address port and LQT mapping 341t links to each other, and the write gate port links to each other with control signal 341wr, and writes input bus and imported the bus that 341i forms by the main frame mark of contact control signal 341h and selection and link to each other.Effectively LQT inlet 341a comprises the valid_lqt_bit of each device flag value.When the value of valid_lqt_bit was logical one, this showed and has used the corresponding apparatus mark value, and logical value 0 shows and do not use the corresponding apparatus mark value.Described valid_lqt_bus 341v is the bus that comprises whole valid_lqt_bits.Described valid_lqt_bus 341v is offered LQT mapping 341b as input.When control signal 341h was in logical zero, LQT mapping 341b found untapped first mark value in main frame 11 scopes, and was placed on the LQT mapping output 341lt.When control signal 341h was in logical one, LQT mapping 341b found untapped first mark value in main frame 12 scopes, and was placed on the LQT mapping output 341lt.LQT mapping output 341t links to each other with the input of device flag multiplexer 341m1.Described control signal 341n selects to place the input of the main frame mark multiplexer 341m1 on the device flag multiplexer output 341dt.When acknowledgement control signal 341wr, the value that will be arranged on selected main frame mark input 341i and the control signal 341h writes the mark memory 341d that is positioned at corresponding to the porch of LQT mapping output 341lt, and will be set at logical one corresponding to the valid_lqt_bit of LQT mapping output 341lt.

By carry out the inverse mapping of LQ mark at porch access flag memory 341d with the address that equals receiving equipment mark input 341j.The receiving equipment mark input 341j that illustrates links to each other with the address port of reading of mark memory 341d, and when acknowledgement control signal 341rd, access flag memory 341d, and the inlet that will be in corresponding to the place, address of receiving equipment mark input 341j places in the output.Described mark memory output 341ilt links to each other with the input of main frame mark multiplexer 341m2.Described control signal 341n selects to place the input of the main frame mark multiplexer 341m2 in the output of multiplexer 341m2.The output of main frame mark multiplexer 341m2 is kept among the retrieve_tag_register 341e.Described retrieve_tag_register output 341ht comprises and shows which platform main frame is the signal and the corresponding main frame mark value of origin host.

Described Sactive mapping 341s receives Sactive input 341k and the 341qd of main frame queue depth, and generates main frame 11 Sactive output bus 341s1 and main frame 12Sactive output bus 341s2.To place the corresponding positions of main frame 11 Sactive output bus 341s1, the holding position of (logical zero) main frame 11 Sactive output bus 341s1 that reset through the position 0 of the host_queue_depth_minus_one of Sactive input 341k.To place position 0 through the position host_queue_depth of Sactive input 341k (2*host_queue_depth-1), the holding position of (logical zero) main frame 12Sactive output bus 341s2 that resets through the host_queue_depth_minus_one of main frame 12Sactive output bus 341s2.

Operating in the following table 1 of main frame arbitration 343 described.As mentioned above, main frame arbitration 343 uses circular priority to select to send to equipment the main frame of order.At first, priority is at random distributed to main frame 11.Described arbiter is known described priority and is carried out arbitration to select to send to equipment the main frame of order (FIS).When equipment enters the state of accepting another order, the notice arbiter, and arbiter changes priority to another main frame.

The signal of describing the arbiter operation in table 1 is as follows:

H1_fis_req shows that when set main frame 11 has the FIS request

H2_fis_req when set, shows that main frame 12 has the FIS request

H1_Qcmd when set, shows that main frame 11 issued queue command, non-queue command when resetting,

H2_Qcmd when set, shows that main frame 12 issued queue command, queue command not when resetting

H1_Qempty when set, shows that main frame 11 has empty queue, non-empty queue when resetting

H1_Qempty when set, shows that main frame 11 has empty queue, non-empty queue when resetting

Table 1. main frame arbitration operations

H1_fis_ H2_fis_ H1_Qc H2_Qc H1_Qe H2_Qe main frame arbitration action

Req req md md mpty mpty1 10 x x 11 permission main frames 112 01 x x 11 permission main frames 12

The main frame that 3110011 permissions have priority

4110111 permission main frames 11

5111011 permission main frames 12

The main frame that 6111111 permissions have priority

710 x x, 01 permission main frames 11

801 x 001 do not issue permission (3)

901 x, 101 permission main frames 12

10 110001 permission main frames 11 (1)

11 110101 permission main frames 11 (1)

12 111001 permission main frames 11

Replacedly, if leave over team

Main frame is so just permitted in the row order

11, otherwise, if local team

Permission (4) is not then issued in the row order

The main frame that 13 111101 permissions have priority

14 100 x 10 do not issue permission (3)

15 101 x, 10 permission main frames 11

16 01 x x, 10 permission main frames 12

17 110010 permission main frames 12 (2)

18 110110 permission main frames 12

Replacedly, if leave over team

Main frame is so just permitted in the row order

12, otherwise, if local team

Permission (4) is not then issued in the row order

19 111010 permission main frames 12 (2)

The main frame that 20 111110 permissions have priority

21 100 x, 00 permission main frames 11 (1)

22 101 x, 00 permission main frames 11

23 01 x, 000 permission main frames 12 (2)

24 01 x, 100 permission main frames 12

The main frame that 25 110000 permissions have priority

26 110100 permission main frames 12

27 111000 permission main frames 11

The main frame that 28 111100 permissions have priority

29 00 x x x x do not issue permission

Note:

(1) when main frame 11 has non-empty queue, it issues non-queue command.Described switch is transferred to equipment with order.The reception of the non-queue command of response non-empty queue, equipment will be provided with mistake (ERR).Reception mistake with non-empty queue will cause switch to refresh the non-empty queue order, and send the ERR state to the main frame with non-empty queue.

(2) when main frame 11 has non-empty queue, it issues non-queue command.Described switch is transferred to equipment with order.The reception of the non-queue command of response non-empty queue, equipment will be provided with mistake (ERR).Reception mistake with non-empty queue will cause switch to refresh the non-empty queue order, and send the ERR state to the main frame with non-empty queue.

(3) has empty queue owing to send the main frame of non-queue command, and another main frame has non-empty queue, sending non-queue command will cause equipment that mistake is set and cause formation to be refreshed, therefore when sending main frame with empty queue, and when another main frame has the non-empty queue order, keeping sending non-queue command, is empty up to another main frame formation.

(4) as mentioned above, when the main frame with empty queue when another main frame has non-empty queue, when issuing non-queue command, keep non-queue command, be empty up to formation.In this case, when the main frame with non-empty queue sends another queue command, be empty in order to allow formation, need to keep the queue command of up-to-date reception, be empty up to formation, and send non-queue command.In leaving over the situation of queue command, because when reconnecting equipment, so the necessary release command of switch is the actual queue command of leaving over of up-to-date reception that do not keep.Yet this restriction is not suitable for the local queue order.

The effective switch 300 that uses Fig. 6 of the arbitration algorithm of weighing based on rotation priority is above being described.Use the alternative embodiment of different arbitration algorithm to belong within the spirit and scope of the present invention.This interchangeable arbitration algorithm includes, but are not limited to: the arbitration algorithm that bandwidth is provided to every main frame based on static state or dynamic weighting (weighting is " bandwidth of distributing to main frame " and the ratio of " total available bandwidth ").This arbitration algorithm utilized bandwidth assay method, such as, but not limited to: the average transmission counting (number of user data) of every order.

In 4 layers, from 1 layer of first protocol stack up to 4 layers of exchange of handling received frames, 4 layers by second protocol stack are then handled down to 1 layer from 4 layers of second protocol stack then.In order to reduce the circuit relevant, and reduce delay, introduced several changes according to embodiments of the invention via switch 300 with switch 300.These changes will be summarized and describe below in more detail.

-described host protocol stack and device protocol stack are shared same data FIS FIFO

-prevent to send assignment file for another 4 layers from 4 courses, by sending FIS for 3 layers, reduce delay thus via switch from 3 courses

Fig. 9 shows and is used for effective switch 500 (3 grades of ports 410 of the SATA of Figure 10 embodiment a).3 grades of ports 410 of SATA comprise PL circuit 411, LL circuit 412 and TL circuit 413.Described PL circuit 411 comprises analog front circuit (AFE) 411a, physics/link interface circuit 411e, initial physical state machine (Phy ISM) 411b and OOB detector 411c.The described PL circuit 411 that illustrates sends signal 411tx with the output high speed differential and links to each other with the differential received signal 411rx of input.The described PL circuit 411 that illustrates sends bus 412t via link and links to each other with LL circuit 412 with link reception bus 412r.Described OOB detector 411c detects the OOB signal and send the OOB signal that detects on 411o.By the multiplexer 411b selection transmission data 411t of Phy ISM411b control or the PhyISM output 411s that is used to transmit.Described Phy ISM 411b control signal comprises signal 411i.The LL circuit 412 that illustrates sends data/address bus 412t via link and links to each other with PL circuit 411 with link reception data/address bus 412r.Described LL circuit 412 provides off-position and provide power down request on signal 412p.The LL circuit 412 that illustrates receives bus 413r via transmission transmission bus 413t, transmission and links to each other with TL circuit 413 with transmission control/status bus 413c.TL circuit 413 comprises that FIS keeps register 413a and multiplexer 413b.Described TL circuit 413 does not comprise data FIS FIFO.Data FIS FIFO 415a and the FIFO control 415b that is associated are shifted out TL circuit 413, and externally be positioned 3 grades of ports 410 of SATA usually.This modification of TL circuit, that is, aspect reducing the FIFO number and reducing the delay that is associated with effective switch, it is crucial that the TL circuit is physically outwards shifted out in FIFO and FIFO control.3 grades of ports 410 of the SATA that illustrates link to each other with external data FIS FIFO 415a with FIFO output bus 415o via FIFO input bus 415i.3 grades of ports 410 of the SATA that illustrates link to each other with external FIFO control 415b with fifo status bus 415s via FIFO control bus 415c.The FIS input bus 416i of 3 grades of ports 410 of SATA and maintenance FIS output bus 416o (altogether as " FIS bus structures ") externally provide additional input and output interface.In the embodiment of Fig. 9, first double word that data FIS FIFO includes only load, the data FIS of data FIS will be positioned at FIS and input or output on the bus.The FIS bus structures allow do not passing through under the situation of FIS, among 3 layers sata port by the non-data FIS and the first double-word data FIS that sends via 4 layers.The external FIFO architecture allows under not via 4 layers of situation by the load of data FIS, the load by data FIS among sata port.In alternative embodiment, data FIS FIFO comprises complete data FIS, and it comprises first double word of data FIS.Described FIS input bus and maintenance FIS output bus generally include non-data FIS.

Figure 10 a and 10b show the block diagram of another embodiment of effective switch 500 of the present invention.Effectively one of feature of the architecture of switch 500 be not via 4 layers by under the data conditions, use public FIFO to come among sata port by the load of data FIS, reduce the delay that is associated with switch and the number of FIFO thus.Effectively another feature of switch 500 is the FIS bus structures, this structure allows do not passing through under the situation of FIS via 4 layers, among 3 layers sata port,, reduce delay thus through effective switch 500 by non-data FIS and first double-word data FIS.

Referring to Figure 10 a, effectively switch 500 comprises 3 grades of host ports 510 of SATA, SATA3 level host port 520,3 grades of device ports 530 of SATA, data FIS FIFO 555a, FIFO control 555b, data multiplexer 551a, control multiplexer 551b, data multiplexer 553, main frame FIS circuit 542, equipment FIS circuit 543 and arbitration and control circuit 541.SATA 3 grades of ports 510,520 and 530 architectures with as mentioned above and the architecture of the 3 grades of ports 410 of SATA shown in Fig. 9 identical.Main frame FIS circuit 542 comprises main frame FIS register 514a, main frame FIS register 524a, unsettled main frame FIS register 542b and main frame FIS multiplexer 542a.Main frame FIS output 517o, the main frame FIS output 527o that illustrates links to each other with the input of multiplexer 542a with unsettled main frame FIS output 542p.The output of the main frame FIS multiplexer 542a that illustrates links to each other with main frame FIS output bus 542o.Described equipment FIS circuit 543 comprise equipment FIS register 534a, equipment FIS multiplexed-decomposer 543a and equipment FIS multiplexer 543b.Equipment FIS output 537o, the FIS bus 543i that illustrates be multiplexed with equipment FIS with sub-FIS bus 543j-and the input of decomposer 543a links to each other.First output of multiplexed-decomposer 543a is main frame FIS input bus 516i, and second output of multiplexed-decomposer 543a is main frame FIS input bus 526i.Control signal 543k control appliance FIS is multiplexed-operation of decomposer 543a.Main frame FIS output bus 542o, the FIS bus 543m that illustrates links to each other with the input of equipment FIS multiplexer 543b with sub-FIS bus 543n.The equipment FIS multiplexer output 543d that illustrates links to each other with equipment FIS input bus 536i.Described equipment FIS multiplexer is selected the operation of signal 543s control multiplexer 543b.

Referring to Figure 10 c, the operation of multiplexed-decomposer 543a is multiplexed succeeded by the secondary of multichannel decomposition.At the multiplexed place of the first order, 543k represents by control signal, selection equipment FIS output bus 537o or FIS bus 543i and multiplexed by the second level, if wherein it is represented by control signal 543k, replace the multiplexed part output of the first order with sub-FIS bus 543j so, and the multichannel as a result that the second level is multiplexed decomposes two outputs of multiplexed-decomposer 543a.Described control signal 543k comprises and is used for the multiplexed and control signal multichannel decomposition function.The described multichannel decomposition function result that the second level is multiplexed passes to selected output, and another output of multiplexed-decomposer 543a is set to invalid level.Multiplexer 543b operation is that a secondary is multiplexed, in the first order, 543s represents by control signal, select main frame FIS output bus 542o or FIS bus 543m, and it is multiplexed to send it to the second level, wherein is placed on the output 543d, is perhaps represented by control signal 543s on the contrary, replace the multiplexed part output of the first order with sub-FIS bus 543n, place then on the output 543d.

Referring to Figure 10 a, data FIS FIFO 555a is a circuit based on dual port FIFO, comprises data FIFO input 555a (i1), data FIFO output 555a (o1), data FIFO input 555a (i2) and data FIFO output 545a (o2).FIFO control 555b comprises fifo status output 555b (o1), the control input 555b (i2) of FIFO control input 555b (i1), the control that data FIFO port 555a is provided and state and provides the control of data FIFO port 555b and the fifo status output 555b (o2) of state.3 grades of host ports 510 of the SATA that illustrates send signal 511tx with the output high speed differential and link to each other with the differential received signal 511rx of input.The main frame FIFO output bus 515o that illustrates links to each other with multiplexer 551a.The main frame FIFO input bus 515i that illustrates links to each other with data FIFO output port 555a (o1).The main frame FIFO control bus 515c that illustrates links to each other with fifo status port 555b (o1) with multiplexer 551b respectively with fifo status bus 515s.

The main frame that illustrates keeps FIS output bus 516o to link to each other with the input of main frame FIS register 514a.The output of the multiplexed-decomposer 543a that illustrates links to each other with main frame FIS input bus 516i.3 grades of host ports 520 of the described SATA that illustrates send signal 521tx with the output high speed differential and link to each other with the differential received signal 521rx of input.The main frame FIFO output bus 525o that illustrates links to each other with multiplexer 551a.The main frame FIFO input bus 525i that illustrates links to each other with data FIFO output port 555a (o1).The main frame FIFO control bus 525c that illustrates links to each other with fifo status port 555b (o1) with multiplexer 551b respectively with fifo status bus 525s.The main frame that illustrates keeps FIS output bus 526o to link to each other with the input of main frame FIS register 524a.The main frame FIS input bus 526i that illustrates links to each other with the output of multiplexed-decomposer 543a.

3 grades of device ports 530 of the described SATA that illustrates send signal 531tx with the output high speed differential and link to each other with the differential received signal 531rx of input.The equipment FIFO output bus 535o that illustrates links to each other with multiplexer 553.The equipment FIFO input bus 535i that illustrates links to each other with data FIFO output port 555a (o2).The equipment FIFO control bus 535c that illustrates links to each other with fifo status port 555b (o2) with FIFO control port 555b (i2) respectively with equipment fifo status bus 535s.The equipment that illustrates keeps FIS output bus 536o to link to each other with the input of equipment FIS register 534a.The equipment FIS input bus 536i that illustrates links to each other with equipment FIS multiplexer output 543d.

Arbitration and control circuit 541 receive main frame 11 FIS output bus 517o, main frame 12 FIS output bus 527o, main frame FIS output bus 542o and equipment FIS output bus 537o.Arbitration and control circuit 541 generate selects signal 551s to select effective main frame, and described selection signal 551s is the control signal of multiplexer 551a and 551b.Arbitration and control circuit 541 generate control command layer output bus 553i and select signal 553s, described control command layer output bus 553i links to each other with the input of multiplexer 553, and described selection signal 553s is the control signal that is used for multiplexer 553.In some cases, the function of bus 553i comes from the data of equipment with replacement, and after this this will describe.

Arbitration and control circuit 541 generate main frame FIS multiplexer control signal 542s, are used to control the operation of multiplexer 542a so that select one of input of multiplexer 542a, and so that selected input are placed on the output 542o.Arbitration and control circuit 541 generation FIS bus 543i and sub-FIS bus 543j, the input of their-decomposer 543as multiplexed with equipment FIS links to each other.Circuit 541 also generates equipment FIS control signal 543k, be used to control described multiplexed-operation of decomposer 543a.Arbitration generates FIS bus 543m, the sub-FIS bus 543n that links to each other with the input of equipment FIS multiplexer 543b with control circuit 541, and the apparatus operating FIS of control multiplexer 543b selects signal 543s.

As described in previously, Fig. 8 a and 8b show switch of the present invention respectively to leaving over the operational flowchart of queue command and local queue order (NQ CMD).Fig. 8 a and 8b are applicable to Figure 10 a of switch 500 of the present invention and the embodiment of 10b.

Disconnect/reconnecting among the state 366b, with preservation state 376b, send mark and send to main frame to the remap FIS of state 384a and NQ stable state 385b, modification of Host Status 378b, NQ.Arbitration and control circuit 541 send the FIS of modifications, and are placed on the sub-FIS bus 543j, and described sub-FIS bus 543j is multiplexed with equipment FIS-and the input of decomposer 543a links to each other.Circuit 541 also is provided with the value of selecting on the signal 543k, so that with the part of sub-FIS bus 543j alternate device FIS output 537o, multichannel decomposes in the output of the multiplexed-decomposer 543a that links to each other with main frame FIS input bus then.

In reconnecting to Host Status 376a, new FIS is sent to main frame.Arbitration and control circuit 541 send to new FIS on the FIS bus 543i, described FIS bus 543i is multiplexed with equipment FIS-and the input of decomposer 543a links to each other, and the value of selecting on the signal 543k is set, so that select bus 543i, multichannel decomposes in the output of the demultiplexer 543a that links to each other with main frame FIS input bus then.

Sending LQ CMD state 364 and sending among the NQ CMD state 382b, the FIS that revises is sent to described equipment.Arbitration and control circuit 541 generate the FIS that revises, and be placed on the sub-FIS bus 543n, described sub-FIS bus 543n links to each other with the input of equipment FIS multiplexer 543b, and be provided with and select the value on the signal 543s, with output as multiplexer 543b so that use sub-FIS bus 543n to substitute the part that main frame FIS exports 542o.The output of multiplexer 543b links to each other with equipment FIS input bus 536i.

In sending service CMD state 373, new FIS is sent to equipment.Arbitration and control circuit 541 send to new FIS on the FIS bus 543m, described FIS bus 543m links to each other with the input of equipment FIS multiplexer 543b, and the value of selecting on the signal 543s is set, so that select bus 543m as the output of multiplexer 543b.The output of multiplexer 543b links to each other with equipment FIS input bus 536i.

Referring to Figure 10 b, arbitration and control circuit 541 comprise main frame arbiter 544, mark/Sactive mapping circuit 546 and control circuit 545.

Mark/Sactive mapping circuit 546 identical with shown in Fig. 7 b, and comprise by the function that mark/Sactive mapping circuit 546 is carried out:

Selected main frame formation mark is mapped to the transmitting apparatus mark, and under the situation of leaving over the formation mark, the result is kept among the mark memory 341d, and preserve one and show effect formation mark.

Inverse mapping receiving equipment formation mark is so that identification main frame and obtain the origin host mark, and under the situation of leaving over the formation mark, when when finishing order by control circuit 342 when directed, the dead queue mark.

The Sactive field is mapped to main frame 11sactive field and main frame 12sactive field corresponding to main frame 11 and main frame 12 respectively.

Main frame 11 FIS output bus 517o comprise main frame 11 FIS request 518, and it comprises main frame 11 FIS request signals and FIS type.Main frame 12 FIS output bus 527o comprise main frame 12 FIS request 528, and it comprises main frame 12 FIS request signals and FIS type.The quene state signal 546q that main frame arbiter 544 receives main frames 11 FIS request 518, main frame 12 FIS request 528, comes from the control signal 544c of control circuit 545 and come from mark/Sactive mapping circuit 546.Response comes from the control signal 544c of control circuit 545, and main frame arbiter 544 generates the main frame of the input of serving as control circuit 545 and selects signal 544hs.Operating in above of main frame arbitration 544 described with respect to table 1.

The function of being carried out by control circuit 545 comprises:

Generation is used to control the selection signal 551s of the operation of multiplexer 551a and 551b

Generate control command layer output bus 553i and select signal 553s, described control command layer output bus 553i links to each other with the input of multiplexer 553, and described selection signal 553s is the control signal of multiplexer 553

Generate FIS bus 543i and sub-FIS bus that links to each other with the input of equipment FIS demultiplexer 543a and the apparatus operating control signal 543k that is used to control multiplexed-decomposer 543a

The apparatus operating FIS multiplexer that generates FIS bus 543m, the sub-FIS bus that links to each other with the input of equipment FIS multiplexer 543b and control multiplexer 543b is selected signal 543s

Generate the control signal of mark/Sactive mapping circuit 546

Generate the control signal of main frame arbitration 544

The embodiment of Figure 10 b comprises exchange initializing circuit 549 in addition and comes from the off-position and the request signal of sata port.

The off-position of the 3 grades of ports 510 of SATA that illustrate links to each other with control circuit 545 with request signal 512p.The OOB detector signal 511o of the 3 grades of ports 510 of SATA that illustrate links to each other with exchange initializing circuit 549.The Phy ISM control signal 511i of the 3 grades of ports 510 of SATA that illustrate links to each other with exchange initializing circuit 549.

The off-position of the 3 grades of ports 520 of SATA that illustrate links to each other with control circuit 545 with request signal 522p.The OOB detector signal 521o of the 3 grades of ports 520 of SATA that illustrate links to each other with exchange initializing circuit 549.The Phy ISM control signal 521i of the 3 grades of ports 520 of SATA that illustrate links to each other with exchange initializing circuit 549.

The off-position of the 3 grades of ports 530 of SATA that illustrate links to each other with control circuit 545 with request signal 532p.The OOB detector signal 531o of the 3 grades of ports 530 of SATA that illustrate links to each other with exchange initializing circuit 549.The Phy ISM control signal 531i of the 3 grades of ports 530 of SATA that illustrate links to each other with exchange initializing circuit 549.Described exchange initializing circuit 549 is identical with the exchange initializing circuit 244 of Fig. 5.The function of being carried out by exchange initializing circuit 549 can be given the SATA PL circuit in sata port 510,520 and 530.As interchangeable embodiment, the function that is about to exchange initializing circuit 549 is given the SATA PL circuit in sata port 510,520 and 530, falls within the scope of the present invention.

It will be apparent to those skilled in the art that and the embodiment of the effective switch of SATA of the present invention can be expanded to the effective switch of SATA to ATA.Figure 11 a and 11b show the embodiment of the effective switch of this SATA to ATA, the memory cell that its permission is linked to each other with switch via the ATA link by two main frame concurrent accesses, and wherein said two main frames link to each other with switch via the SATA link.

Figure 11 a shows the embodiment according to SATA to ATA switch 600 of the present invention.Described switch 600 is basic identical with the switch 300 of Fig. 6, but has following difference:

Replace 4 grades of device ports 330 of SATA in the switch 300 with 4 grades of SATA to ATA bridge 630

With SATA link 331tx, the 331rx in the ATA link 636 replacement switches 300.

4 grades of SATA comprise SATA layer order 634, ATA transport layer 633 and ata interface bridge 632 to ATA bridge 630.The ata interface bridge 632 that illustrates links to each other with ATA link 636, and with the activity of the activity on the ata bus 636 conversion (bridge joint) to the transport layer interface 633io, vice versa.Described SATA layer order 634 is identical with transport layer 53 with the layer order 54 of Fig. 2 b with transport layer 633.

Figure 11 a shows another embodiment according to SATA to the ATA switch 700 of the embodiment of the invention.Switch 700 is basic identical with the switch 500 of Figure 10 a, but has following difference:

Replace 3 grades of device ports 530 of SATA in the switch 500 with 3 grades of SATA to ATA bridge 730

With SATA link 531tx, the 531rx in the ATA link 736 replacement switches 500.

3 layers of described SATA comprise ATA transport layer 733 and ata interface bridge 732 to ATA bridge 730.Described ata interface bridge 732 links to each other with ATA link 736, and with the activity of the activity on the ata bus 736 conversion (bridge joint) to the transport layer interface 733io, vice versa.Described transport layer 733 is identical with the transport layer 413 of Fig. 9.

Used the Parallel ATA bus to describe the embodiment of Figure 11 a and 11b.Those skilled in the art it is evident that, the present invention can be expanded to and use other parallel buss.Scope of the present invention is except that the Parallel ATA bus, also comprise and use other parallel buss.

Figure 12 shows modification to SATA FIS structure so that routing iinformation is provided.That is to say that according to another embodiment of the present invention, sata port comprises the frame information structure that route is clear and definite, being used to discern which platform main frame is that source host and which platform main frame are destination hosts.Shown in Fig. 1 d, SATA FIS structure has minority and keeps the position in first double word (double word 0) of FIS, especially the position 8 to 12 of double word 0.Represent that by using these to keep one of position main frame is origin or the destination of FIS, has greatly simplified the Route Selection in the switch.With this routing bit be called the H position (91 (i), 91 (ii), 91 (iii), 91 (iv), 91 (v), 91 (vi), 91 (vii) with 91 (viii)), according to the FIS direction, logical value 0 shows main frame 11 and logical value 1 shows that main frame 12 is origin or destinations of FIS.Thus, which platform main frame of recognition of devices is origin and/or destination, thereby the Route Selection of FIS is transparent for switch, has reduced the design complexity of switch thus, make its cost more cheap, provide ' route is clear and definite ' Route Selection via switch thus.

When the switch forward device sent FIS, if FIS derives from main frame 11, switch was reset to logical value 0 with the H position so, if FIS derives from main frame 12, the H position is set to logical value 1 so.Described equipment must be preserved the H position, and is inserted into any FIS that is sent to main frame.Utilize the clear and definite FIS structure of route, the complexity of effective switch can be reduced to 2 layer switch.Can revise 2 layer switch of Fig. 5, so that operate as effective switch with the clear and definite FIS structure of route.In a this modification, revise effective main frame of switch 200 and select circuit 141, so that check the H position of the input FIS come from equipment, and generate the control signal that is used for Route Selection by H position and will import the H position of FIS and route to suitable main frame based on the FIS of input.

The embodiment of the invention of using circuit based on dual port FIFO has been described.It should be apparent to those skilled in the art that and to use adjunct circuit and single port FIFO to come together to replace circuit based on dual port FIFO.In addition, some buses in described embodiment, i.e. input or output can be merged into the two-way input/output bus of wall scroll.In addition, the bus that is exclusively used in a function can be merged into single bus.

In order to summarize, in an embodiment of the present invention, two main frames, main frame 1 and main frames 2 (such as main frame among Fig. 3 a 11 and main frame 12), with memory cell coupling so that from wherein or to reading writing information wherein, seek memory cell (such as memory cell 16 via switch, shown in Fig. 3 a) time visit, described switch is respectively such as the switch 300 and 500 of Fig. 6 and 10a.This is the important difference with prior art systems, though because in the prior art, two main frames can storage unit access, and they can not visit same memory cell simultaneously.In the prior art, if the connection between one of main frame and the memory cell is broken down for a certain reason, another main frame can continue storage unit access so.Yet, after detecting fault, switch to another main frame and since system need another main frame be reset before memory cell is communicated by letter, can the generation glitch so do like this.

In other prior art systems, such as the fault-tolerance system, a main frame shields another main frame, that is to say that any action of effective main frame execution all attempts to be disabled the main frame imitation.This principle is called " heartbeat ", show two connectednesses between the main frame reached two main frames know deposit each other and another be exercisable.That is to say that a main frame is recognized the fault of another main frame, the result no longer detects " heartbeat ", at that time, has carried out the main frame that detects and has taken over storage unit access, and do not had to continue operation under the situation of another main frame.In addition, because described main frame can not resemble simultaneously storage unit access of the present invention,, and can not use the single port memory cell so this prior art systems requires the use dual port memory unit.

In business system, because need multiple host to visit the single port memory cell simultaneously, so be starved of embodiments of the invention.In the present invention, will order according to the other types information from host computer and send to memory cell simultaneously.The present invention has eliminated by from caused glitch valid till the conversion of invalid main frame, as by experiencing in more above-described prior art systems.In fact, in the present invention, the exchange between two main frames is carried out according to a kind of continuous and smooth mode.

Hardware is followed multilayer SATA basically and is constructed.The SATA physical layer comprises the AFE (analog front end) that is used to send and receive high speed signal.The init state machine also is included in together with the interface block that band external detector and being used to connects link layer.Select choice of equipment to send initialization information and still send the data that come from physical layer.Described link layer is communicated by letter with transport layer, one group of register that it generally includes the FIFO that is used for the data transmission and is used for non-data FIS exchange.Described FIFO is generally used for storing data FIS, and register is generally used for storing non-data FIS.

As shown in Figure 4, in a system of prior art, there is a physical layer in a main frame, and there is another physical layer in another main frame, and also there are physical layer in equipment or the memory cell of being used by switch, and wherein said switch is coupling between main frame and the equipment.There are not other layers and main frame and/or devices communicating.Via described physical layer, select wherein main frame by multiplexer, so that communicate with equipment, equipment sends data to that effective main frame then.Effectively main frame is selected the circuit decision or is selected which platform main frame to select at first together with initializing circuit.Thus, the switch of this prior art only needs one deck or physical layer to communicate by letter, and does not need other layers to communicate by letter.Yet as previously mentioned, one of problem that adopts this prior art systems is to postpone via switch.Another problem is to have only the main frame can be at arbitrarily preset time and devices communicating.

One of embodiments of the invention manage to solve the delay issue via switch, as shown in Figure 5.Owing to adopted the SATA link of the second layer rather than only used ground floor, so no longer be problem via the delay of switch.Described switch is actually 2 layer switch, thus, and can be in link layer and physics intralayer communication.But before being sent to equipment, will come from the data multiplex of host link layer, they are stored among the FIFO so that be cushioned, the result makes via the delay of switch and is longer than the delay that serial ATA standard is in either case allowed, in prior art systems, this data have often been lost because of long delay.Yet in the embodiment of Fig. 5, the FIFO buffering has prevented any loss of data, even if be longer than the requirement of standard via the delay of switch.Subsequently, by using demultiplexer 243 (Fig. 5), the data that will come from equipment are routed to effective main frame.Thus, in the embodiment of Fig. 5,, there is not the EVAC (Evacuation Network Computer Model) performance via the delay of switch 200 though have only a main frame to communicate by letter with device in any given time, and consistent with the requirement of standard.

As selection, adopt 1 layer or physical layer to make delay look and can ignore by using FIFO (rather than only 1 layer) via switch, operate just as adopting at above-described additional 2 layers.

In Fig. 6, visit when having described by two main frames to equipment.Expression simultaneously is when equipment (such as memory cell) when not being in idle condition as used herein, comes from any one order of two or more main frames in reception preset time arbitrarily.Idle condition is that equipment is not when handling other orders.Traditionally, by realizing, perhaps be referred to as time division multiplexing (TDM) usually simultaneously at multiplexed every the main frame of sheet preset time.Yet, because of new timeslice or time slot interrupt suddenly sending when serving another main frame, because wherein one may be arranged in data and transmits,, tend to destroy systematic function like this and may cause obliterated data so memory device can't operate as normal.

Thus, the embodiment of Fig. 6 has adopted based on the exchange of ordering or multiplexed.That is to say that when handling the order that comes from a main frame, buffering comes from any order of another main frame, and sends to equipment after finishing the current command or the like, produces ping-pong thus between the order of two main frames.

For realizing multiplexed based on order, be two main frames and described equipment and assignment file is used for 4 layers.In Fig. 6, it is shown as port host port and device port all are 4 layers of (perhaps layer order) ports.Arbitration and control circuit 340 (Fig. 6) monitor task file 10 are checked any order that perhaps can be sent out, and in a preferential order list order then, and the order of highest priority is sent to equipment.When host port received described order and has priority, it was sent to device port with order.Simultaneously,, so it is stored in the assignment file, and sends to arbitration and control circuit if received another order from another main frame, and in case service in preceding order, just with unsettled command auto repeat to equipment, and this ping-pong takes place.It should be noted, in the embodiment of Fig. 6, satisfied the timing requirement of switch, realize message transmission because use comprises the 1-4 layer of FIFO.In addition, can send order simultaneously, between two main frames and equipment, transmit simultaneously so that allow.

The arbitration of Fig. 6 and the more details of control circuit 340 are provided in the residue accompanying drawing of this document, and discuss from start to finish identical.

Described device responds " identification drives order " sends the information relevant with its ability, and can be changed by switch by some parameters that equipment is represented.For example, if equipment is supported command queuing, it has the queue depth that indicates it can line up and how much order so, and this information becomes very important for main frame then.For example,, only can line up 16 when ordering when every main frame so, will overflow above the order of any number of this number, and cause order to be lost if described queue depth represents to have only 32 orders can be by the queuing of two main frames.Thus, queue depth's information is changed to represent 16 rather than 32,16 orders thereby every main frame is only lined up.

The mode of doing like this is actually the Q DEPTH information that comes from equipment with intercepting, and its value is changed into 16 from 32.In addition, adopted the formation marking circuit that is used to shine upon the main frame mark and the device flag that remaps.

Run through this document, wherein use or discussed multiplexed-splitter circuits, select referring to first between two or more signals, thus, carry out multiplexed function, and route to effective main frame with signals selected after a while, thus, carry out the demultiplexer function.

In the embodiment of Fig. 6, adopted three FIFO, one in every main frame and the 3rd in equipment.Introduce like this and postpone.

In alternative embodiment, as shown in Figures 9 and 10, have only a FIFO to be used, wherein FIFO is taken out from transport layer.More precisely, the FIS interface is used for 3 layers, helps to reduce design complexity like this and reduce delay because of FIFO.Share FIFO by all three ports, host port and device ports.

In Figure 11, use non-serial ATA port to replace 1 layer and 2 layers such as ata port, use non-serial ATA standard to start the use of memory cell thus, so that the low-cost memory cell in the using system is improved system cost.

In yet another embodiment of the present invention, the FIS structure clear and definite with route replaces the FIS structure, thereby adopts 2 layer switch to run through each layer processing.

Thus, show and discussed four distinct embodiment, one is to use 4 layers of exchange, one is that communication and the introducing FIFO that reduces different layers (3 layers) admits this communication, another is to use ata interface to replace serial ATA, and the 4th is the clear and definite FIS structure of route that is used to exchange, and wherein said FIS structure is known the Route Selection of the information of different main frames.

It should be noted, though run through this patent documentation, mentioned the particular polarity of signal or the logic state such as logic state 1 ' or ' 0 ' come index signal effectively or disarmed state, but in fact under situation about not departing from the scope of the present invention with spirit, can use opposite polarity.In addition, under situation about not departing from the scope of the present invention with spirit, can also utilize the known state of any other type of signal.

This patent documentation is employed as running through, certain alphabetical capital and small letter of signal, state, equipment or the like title, in order to keep publishing the title consistency of disclosed corresponding signal, state, equipment or the like in " Serial ATA:High Speed Serialized At Attachment " with the www.serialata.com of serial ATA working group, its content is hereby incorporated by, and just looks like that they all set forth the same at this.

Though described the present invention, can expect that variation of the present invention and modification are conspicuous beyond doubt to those skilled in the art according to certain embodiments.Therefore, plan following claims are interpreted as covering all this variation and modifications, and these variations and modification all fall into the spirit and scope of the present invention.The present invention is combined equipment and the method that is used to carry out the multiple function that comprises that the present invention instructs to develop with prior art, it will be apparent to those skilled in the art that.This equipment and method fall into scope of the present invention.

Claims (94)

1. switch that is coupling between a plurality of main computer units and the equipment, is used for communicating betwixt comprises:

A) be coupled to first Serial Advanced Technology Attachment (ATA) port of first main computer unit;

B) be coupled to the second serial ATA port of second main computer unit;

C) be coupled to the 3rd serial ATA port of equipment; And

D) arbitration and control circuit when being used for order that any transmission whenever first or second main computer unit is used for being carried out by equipment, select one of first main computer unit or second main computer unit to be coupled to described equipment via switch.

2. switch as claimed in claim 1, wherein, the described first serial ATA port comprises the first host task file.

3. switch as claimed in claim 1, wherein, the described second serial ATA port comprises the second host task file.

4. switch as claimed in claim 3, wherein, described the 3rd serial ATA port comprises the equipment task file.

5. switch as claimed in claim 3, wherein, described first, second and the 3rd port are 4 grades of ports.

6. switch as claimed in claim 1, wherein, described equipment is memory cell.

7. switch as claimed in claim 1, wherein, described switch is used in the business system.

8. switch as claimed in claim 1, wherein, described arbitration and control circuit make the first and second main computer unit concurrent access equipment.

9. switch as claimed in claim 1, wherein, to send to first or second main computer unit with the information slave unit transmission of data, order or foundation (setup) form by this switch, and before first or second main computer unit receives them, revise described information by switch, make thus and win or second main computer unit receives amended information but not described information.

10. switch as claimed in claim 9, wherein, described information is called as ' identification drives response '.

11. switch as claimed in claim 9, wherein, described information is called as ' mark '.

12. switch as claimed in claim 1, wherein, by this switch will be with data, order or the information of setting up form is sent to equipment from first or second main computer unit, and before equipment receives them, revise described information by switch, the equipment that makes thus receives amended information but not described information.

13. switch as claimed in claim 12, wherein, described information is called as ' mark '.

14. switch as claimed in claim 12, wherein, described arbitration and control circuit comprise mark/Sactive mapping circuit, and this circuit is used for the main frame mark is mapped to device flag, and are used for inverse mapping so that the identification main frame.

15. switch as claimed in claim 1 wherein, is first main frame or is that second main frame sends the queue command of leaving over by device queue.

16. switch as claimed in claim 1 wherein, is first main frame or is that second main frame sends the local queue order of being carried out by equipment.

17. switch as claimed in claim 16 wherein, before the equipment of sending to, is revised the mark in the local queue order, thereby is avoided identical mark is used for two main frames, and prevents to surpass the maximum mark value that allows.

18. switch as claimed in claim 17, wherein, before sending to main frame, will be in FIS the mark that receives of slave unit be revised as its initial value.

19. switch as claimed in claim 1, wherein, first, second and the 3rd port are 3 grades of serial ATA ports, and data FIS FIFO and the FIFO control that is associated is coupled to first, second and the 3rd port, and are placed in its outside.

20. a switch comprises:

A) be used to be connected to first Serial Advanced Technology Attachment (ATA) port of first main computer unit;

B) be used to be connected to the second serial ATA port of second main computer unit;

C) be used to the 3rd serial ATA port of the equipment that is connected to; And

D) arbitration and control circuit are used for selecting first main computer unit or second main computer unit to be coupled to the described equipment for the treatment of via switch when arbitrary main computer unit sends the order that is used for by the equipment execution,

Wherein, when one of first or second main computer unit was coupled to described equipment via switch, another in first or second main computer unit sent the order that is used for by described equipment execution to switch.

21. switch as claimed in claim 20, wherein, described switch is the serial ATA switch.

22. switch as claimed in claim 20, wherein, the described first serial ATA port comprises the first host task file.

23. switch as claimed in claim 22, wherein, the described second serial ATA port comprises the second host task file.

24. switch as claimed in claim 23, wherein, described the 3rd serial ATA port comprises the equipment task file.

25. switch as claimed in claim 20, wherein, described equipment is memory cell.

26. switch as claimed in claim 20, wherein, described switch is used in the business system.

27. switch as claimed in claim 20, wherein, described arbitration and control circuit make the first and second main computer unit concurrent access equipment.

28. switch as claimed in claim 20, wherein, by this switch will be with data, order or the information slave unit of setting up form is sent to first or second main computer unit, and before first or second main computer unit receives them, revise described information by switch, make thus and win or second main computer unit receives amended information but not described information.

29. switch as claimed in claim 28, wherein, described information is called as ' mark '.

30. switch as claimed in claim 28, wherein, described information is called as ' identification drives response '.

31. switch as claimed in claim 20, wherein, by this switch will be with data, order or the information of setting up form is sent to equipment from first or second main computer unit, and before equipment receives them, revise described information by switch, the equipment that makes thus receives amended information and described information.

32. switch as claimed in claim 31, wherein, described information is called as ' mark '.

33. one kind is coupling between a plurality of main computer units and the equipment, is used for being betwixt the switch of frame information routing, comprising:

A. first Serial Advanced Technology Attachment (ATA) port comprises the frame information structure (FIS) that route is clear and definite, is coupled to first main computer unit;

B. the second serial ATA port comprises the FIS that route is clear and definite, is coupled to second main computer unit;

C. the 3rd serial ATA port comprises the FIS that route is clear and definite, is coupled to equipment; And

D. arbitrate and control circuit, be used for whenever any of first or second main computer unit when equipment sends FIS, select first main frame or second main computer unit to be coupled to described equipment via switch, and wherein, in the FIS of first and second main computer units and equipment identification first or second main computer unit which is origin and/or destination host, thereby make that the Route Selection of FIS is transparent for switch, reduce the complexity of switch design thus, thereby make its cost cheaper.

34. switch as claimed in claim 33, wherein, described equipment is memory cell.

35. switch as claimed in claim 33, wherein, described switch is used in the business system.

36. switch as claimed in claim 33, wherein, described arbitration and control circuit make the described equipment of the first and second main computer unit concurrent accesses.

37. switch as claimed in claim 33, wherein, utilizing a bit to indicate which main frame is origin or the destination of FIS.

38. switch as claimed in claim 33, wherein, described first, second and the 3rd port are 2 layers of ports.

39. switch as claimed in claim 33, wherein, described switch provides ' route is clear and definite ' Route Selection.

40. switch as claimed in claim 33, wherein, described switch switches between 2 layers, and comprises the first in first out (FIFO) of dual-port.

41. a switch comprises:

A. first Serial Advanced Technology Attachment (ATA) port comprises the frame information structure (FIS) that route is clear and definite, is used to be connected to first main computer unit;

B. the second serial ATA port comprises the FIS that route is clear and definite, is used to be connected to second main computer unit;

C. the 3rd serial ATA port comprises the FIS that route is clear and definite, is used to be connected to equipment, and described switch is used for being the frame information routing between first and second main computer units and equipment;

D. arbitration and control circuit are used for selecting first main computer unit or second main computer unit to be coupled to equipment when any of first or second main computer unit during to equipment transmission FIS via switch,

Wherein, when one of first or second main computer unit is coupled to equipment via switch, in first or second main computer unit another sends FIS to switch, so that be routed to described equipment, and wherein, in the FIS of first and second main computer units and equipment identification first or second main computer unit which is origin and/or destination host, thereby make that the Route Selection of FIS is transparent for switch, reduce the complexity of switch design thus, thereby make its cost cheaper.

42. switch as claimed in claim 41, wherein, described switch is the serial ATA switch.

43. switch as claimed in claim 41, wherein, described equipment is memory cell.

44. switch as claimed in claim 41, wherein, described switch is used in the business system.

45. switch as claimed in claim 41, wherein, described arbitration and control circuit make the first and second main computer unit concurrent access equipment.

46. a switch, it can be connected to first main computer unit, second main computer unit and equipment through Serial Advanced Technology Attachment (ATA) link, is used for being the frame information routing between first and second main computer units and equipment, and described switch comprises:

A. the first serial ATA port comprises the frame information structure (FIS) that route is clear and definite, is used to be connected to first main computer unit;

B. the second serial ATA port comprises the FIS that route is clear and definite, is used to be connected to second main computer unit;

C. the 3rd serial ATA port comprises the FIS that route is clear and definite, is used to be connected to equipment;

D. arbitration and control circuit, be used for when first or second main computer unit when equipment sends FIS, be coupled to described equipment through one of switch selection first or second main computer unit,

Wherein, when one of first or second main computer unit is coupled to equipment, in first or second main computer unit another sends FIS to switch, so that be routed to described equipment, and wherein, in the FIS of first and second main computer units and equipment identification first or second main computer unit which is origin and/or destination host, thereby makes that the Route Selection of FIS is transparent for switch, reduce the complexity of switch design thus, thereby make its cost cheaper.

47. switch as claimed in claim 46, wherein, described switch is the serial ATA switch.

48. switch as claimed in claim 46, wherein, described equipment is memory cell.

49. switch as claimed in claim 46, wherein, described switch is used in the business system.

50. switch as claimed in claim 46, wherein, described arbitration and control circuit make the described equipment of the first and second main computer unit concurrent accesses.

51. one kind is used for the method that communicates by Serial Advanced Technology Attachment (ATA) switch between a plurality of main computer units and equipment, described switch utilizes the serial ATA link couples to a plurality of main computer units and equipment, and be the frame information routing betwixt, comprise:

A. the first serial ATA port is coupled to first main computer unit so that be connected to switch, the described first serial ATA port comprises the frame information structure (FIS) that route is clear and definite;

B. the second serial ATA port is coupled to second main computer unit so that be connected to switch, the described second serial ATA port comprises the FIS that route is clear and definite;

C. be coupled the 3rd serial ATA port so that be connected to equipment, described the 3rd serial ATA port comprises the FIS that route is clear and definite;

D. between first and second main computer units and equipment, arbitrate;

E. when order that any one transmission in first or second main computer unit is used for being carried out by equipment, select one of first or second main computer unit to be coupled to equipment via switch;

F. with in the device coupled to the first or second main computer unit selected one; And

G. when in first or second main computer unit selected one when being coupled to equipment, another in first or second main computer unit sends FIS so that be routed to equipment to switch

During forwarding step g., in the FIS of first and second main computer units and equipment identification first or second main computer unit which is origin and/or destination host, thereby make that the Route Selection of FIS is transparent for switch, reduce the complexity of switch design thus, thereby make its cost cheaper.

52. a switch that is coupling between a plurality of main computer units and the equipment, is used for communicating by letter betwixt comprises:

A) be coupled to first Serial Advanced Technology Attachment (ATA) port of first main computer unit, described port comprises first main frame;

B) be coupled to the second serial ATA port of second main computer unit;

C) be coupled to the 3rd Parallel ATA port of equipment; And

D) arbitration and control circuit are used for selecting one of first main computer unit or second main computer unit to be coupled to described equipment via switch when arbitrary main computer unit sends the order that is used for being carried out by equipment.

53. switch as claimed in claim 52, wherein, the described first serial ATA port comprises the first host task file.

54. switch as claimed in claim 53, wherein, the described second serial ATA port comprises the second host task file.

55. switch as claimed in claim 54, wherein, described the 3rd Parallel ATA port comprises the equipment task file.

56. switch as claimed in claim 55, wherein, described first, second and the 3rd port are 4 grades of ports.

57. switch as claimed in claim 52, wherein, described equipment is memory cell.

58. switch as claimed in claim 52, wherein, described switch is used in the business system.

59. switch as claimed in claim 52, wherein, described arbitration and control circuit make the described equipment of the first and second main computer unit concurrent accesses.

60. switch as claimed in claim 52, wherein, by this switch will be with data, order or the information slave unit of setting up form is sent to first or second main computer unit, and before first or second main computer unit receives them, revise described information by switch, make thus and win or second main computer unit receives amended information but not described information.

61. switch as claimed in claim 60, wherein, described information is called as ' identification drives response '.

62. switch as claimed in claim 60, wherein, described information is called as ' mark '.

63. switch as claimed in claim 52, wherein, by this switch will be with data, order or the information of setting up form is sent to equipment from first or second main computer unit, and before equipment receives them, revise described information by switch, the equipment that makes thus receives amended information but not described information.

64. as the described switch of claim 63, wherein, described information is called as ' mark '.

65. as the described switch of claim 64, wherein, described arbitration and control circuit comprise mark/Sactive mapping circuit, this circuit is used for the main frame mark is mapped to device flag, and is used for inverse mapping so that the identification main frame.

66. switch as claimed in claim 52 wherein, is first main frame or is that second main frame sends the queue command of leaving over by device queue.

67. switch as claimed in claim 52 wherein, is first main frame or is that second main frame sends and to be used for the local queue order carried out by equipment.

68. switch as claimed in claim 52, wherein, first, second and the 3rd port are 3 grades of ports, and Frame information system (FIS) first in first out (FIFO) and the FIFO control that is associated is coupled to first, second and the 3rd port, and are placed in its outside.

69. a switch comprises:

A. be used to be connected to first Serial Advanced Technology Attachment (ATA) port of first main computer unit;

B. be used to be connected to the second serial ATA port of second main computer unit;

C. the 3rd Parallel ATA port that is used to the equipment that is connected to; And

D. arbitration and control circuit are used for selecting first main computer unit or second main computer unit to be coupled to described equipment via switch when arbitrary main computer unit sends the order that is used for by the equipment execution,

Wherein, when one of first or second main computer unit was coupled to described equipment via switch, another in first or second main computer unit sent the order that is used for by the equipment execution to switch.

70. as the described switch of claim 69, wherein, described switch is the serial ATA switch.

71. as the described switch of claim 69, wherein, the described first serial ATA port comprises the first host task file.

72. as the described switch of claim 71, wherein, the described second serial ATA port comprises the second host task file.

73. as the described switch of claim 72, wherein, described the 3rd Parallel ATA port comprises the equipment task file.

74. as the described switch of claim 69, wherein, described equipment is memory cell.

75. as the described switch of claim 69, wherein, described switch is used in the business system.

76. as the described switch of claim 69, wherein, described arbiter makes the described equipment of the first and second main computer unit concurrent accesses.

77. as the described switch of claim 69, wherein, by this switch will be with data, order or the information slave unit of setting up form is sent to first or second main computer unit, and before first or second main computer unit receives them, revise described information by switch, make thus and win or second main computer unit receives amended information but not described information.

78. as the described switch of claim 77, wherein, described information is called as ' identification drives response '.

79. as the described switch of claim 77, wherein, described information is called as ' mark '.

80. as the described switch of claim 69, wherein, by this switch will be with data, order or the information of setting up form is sent to equipment from first or second main computer unit, and before equipment receives them, revise described information by switch, the equipment that makes thus receives amended information but not described information.

81. as the described switch of claim 79, wherein, described information is called as ' mark '.

82. a switch, it can be connected to first main computer unit, second main computer unit and equipment through Serial Advanced Technology Attachment (ATA) link, and described switch comprises:

A. be used to be connected to the first serial ATA port of first main computer unit;

B. be used to be connected to the second serial ATA port of second main computer unit;

C. the 3rd Parallel ATA port that is used to the equipment that is connected to; And

D. arbitration and control circuit are used for being coupled to described equipment via one of switch selection first or second main computer unit when first or second main computer unit sends the order be used for being carried out by equipment,

Wherein, when one of first or second main computer unit was coupled to described equipment, another in first or second main computer unit sent the ata command that is used for by the equipment execution to switch.

83. as the described switch of claim 82, wherein, described switch is the serial ATA switch.

84. as the described switch of claim 82, wherein, the described first serial ATA port comprises the first host task file.

85. as the described switch of claim 84, wherein, the described second serial ATA port comprises the second host task file.

86. as the described switch of claim 85, wherein, described the 3rd Parallel ATA port comprises the equipment task file.

87. as the described switch of claim 82, wherein, described equipment is memory cell.

88. as the described switch of claim 82, wherein, described switch is used in the business system.

89. as the described switch of claim 82, wherein, described arbitration and control circuit make the described equipment of the first and second main computer unit concurrent accesses.

90. as the described switch of claim 82, wherein, by this switch will be with data, order or the information slave unit of setting up form is sent to first or second main computer unit, and before first or second main computer unit receives them, revise described information by switch, make thus and win or second main computer unit receives amended information but not described information.

91. as the described switch of claim 90, wherein, described information is called as ' identification drives response '.

92. as the described switch of claim 90, wherein, described information is called as ' mark '.

93. as the described switch of claim 82, wherein, by this switch will be with data, order or the information of setting up form is sent to equipment from first or second main computer unit, and before equipment receives them, revise described information by switch, the equipment that makes thus receives amended information but not described information.

94. as the described switch of claim 93, wherein, described information is called as ' mark '.

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