CN1571139A - A method for reducing power lead current in integrated circuit - Google Patents
A method for reducing power lead current in integrated circuit Download PDFInfo
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- CN1571139A CN1571139A CN 200410037661 CN200410037661A CN1571139A CN 1571139 A CN1571139 A CN 1571139A CN 200410037661 CN200410037661 CN 200410037661 CN 200410037661 A CN200410037661 A CN 200410037661A CN 1571139 A CN1571139 A CN 1571139A
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 230000001360 synchronised effect Effects 0.000 claims abstract description 5
- 238000012731 temporal analysis Methods 0.000 claims description 2
- 238000000700 time series analysis Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 11
- 230000003068 static effect Effects 0.000 abstract description 5
- 238000012300 Sequence Analysis Methods 0.000 abstract 1
- 239000000872 buffer Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000004458 analytical method Methods 0.000 description 4
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Abstract
The invention relates to a method for reducing power line current in IC, firstly dividing synchronous time sequence circuit into many parallel circuits; making static time sequence analysis on these parallel circuits to obtain the time sequence of each of them; according to the time sequence of each parallel circuit, adding a different delay time to original clock of the parallel circuit to make the clock phases of all the parallel circuits different; using original clock to compensate the phase of output signal of each parallel to synchronize all the output signals. The method uses a corresponding clock to each parallel circuit whose turning time is staggered, thus making the current in each circuit reach the peak value at a different time, reducing peak current of the total circuit and its change trend, and thus reducing ohm voltage drop of power supply/ground wire net and the partial noise that the digital circuit injects into the substrate.
Description
Technical field
The present invention relates to a kind of method that reduces power line electric current in the integrated circuit, belong to the integrated circuit (IC) design technical field.
Background technology
In large scale integrated circuit design, because integrated circuit technology entered the sub-micro stage, the scale and the area of circuit are increasing, and speed is more and more faster, thereby the electric current that causes flowing through power supply and ground wire is increasing; On the other hand, the width of interconnection line is more and more littler, length is more and more longer, even under the ever-increasing situation of interconnection line thickness, the resistance of power/grounding line is also increasing.Therefore, the ohm voltage drop of power/grounding line in the integrated circuit (IR Drop) effect is more and more significant, and the time-delay of logical block in the circuit produced has a strong impact on, thereby causes the circuit cisco unity malfunction.
Present large scale integrated circuit design is mainly used the method for designing of synchronous circuit.In order to obtain correct logical block magnitude of voltage, reduce ohm voltage drop and adopt the method that reduces interconnection line resistance usually: the size such as changing interconnection line added buffer (buffer) in circuit in the past.Existing in circuit the technology of buffer mainly be to optimize the size of buffer, quantity, position etc., then use emulation tool that the circuit of improved is carried out emulation, make the circuit of design satisfy the integrality of signal, and function is correct.Will in original circuit design, add a plurality of buffers but so do certainly, thereby increase circuit area, increase the difficulty of circuit power consumption and placement-and-routing, and emulation repeatedly and placement-and-routing also can consume the plenty of time.These all are that we wish the problem avoided in circuit design.
In integrated circuit (IC) design, the influence of substrate noise is increasing, particularly for present everybody mixed-signal circuit design of often using, because numerical portion and substrate of simulation partial common, the substrate noise that the numerical portion coupling is come has reduced the performance of simulation part very significantly.People have proposed some and have reduced the method for substrate coupled noise, mainly contain: use low logic voltage, current mode logic to also have and use the CMOS that has shielding conductor and decoupling capacitance.Wherein use low logic voltage can reduce the speed of circuit, reduce noise margin; Use current mode logic, topmost shortcoming is the quiescent dissipation that increases, and can not be used for large-scale circuit; The gate of use decoupling crossed belt shielding conductor can increase the area of circuit, increases power line quantity.Therefore it is reasonable to go back neither one so far, and impeccable method effectively suppresses the substrate noise source.
Summary of the invention
The objective of the invention is to propose a kind of method that reduces power line electric current in the integrated circuit, reduce ohm voltage drop, reduce substrate noise by reducing power line current amplitude and variation tendency simultaneously by reducing the power line electric current.
The method of power line electric current in the reduction integrated circuit that the present invention proposes comprises following step:
(1) synchronizing sequential circuit is divided into a plurality of parallel circuits;
(2) above-mentioned a plurality of parallel circuits are carried out Time-Series analysis, obtain the sequential of each parallel circuit;
(3) according to the sequential of above-mentioned each parallel circuit, to the different time-delay of original clock adding of each parallel circuit, the clock phase that all parallel circuits are used is inequality;
(4) with original clock the output signal of each parallel circuit is carried out phase compensation, make all output signals synchronous.
In the said method, synchronizing sequential circuit is divided into the method for a plurality of parallel circuits, may further comprise the steps:
(1) synchronizing sequential circuit is mapped to directed graph, gate in the circuit or logic module are mapped to the summit of directed graph, and interconnection line is mapped as the limit of directed graph in the circuit;
(2) above-mentioned directed graph is divided into a plurality of parallel subgraphs, i.e. parallel circuit.
The method of power line electric current in the reduction integrated circuit that the present invention proposes, be under the stable prerequisite of circuit function, use the clock of out of phase for each parallel circuit in the chip, the upset of parallel circuit module is staggered constantly in time like this, make the electric current in each bar circuit reach peak value in the different moment, thereby reduce the peak current of way circuit, so under the situation that interconnection line resistance does not have to change in circuit, reduce current peak total in the circuit, and then reduced the ohm voltage drop of power/grounding line.And the current amplitude of power supply and variation tendency all reduce, and reduced in the circuit because the voltage amplitude of noise that the LC vibration produces and substrate coupling, thereby reduced the noise that digital circuit partly is injected into substrate.For the influence of the switching noise that reduces numerical portion in the chip, be a kind of effective means that reduces signal cross-talk to simulation and radio frequency.
Description of drawings
Fig. 1 is the circuit diagram of the inventive method institute foundation.
Fig. 2 is the directed graph that is shone upon with circuit diagram.
Fig. 3 is the schematic diagram that uses the clock of out of phase in the inventive method on parallel circuit.
Fig. 4 is the bus current peak value comparison diagram that utilizes the inventive method to obtain.
Embodiment
The method of power line electric current in the reduction integrated circuit that the present invention proposes, at first synchronizing sequential circuit is divided into a plurality of parallel circuits, the circuit diagram of institute's foundation carries out static timing analysis to a plurality of parallel circuits as shown in Figure 1 then, obtains the sequential of each parallel circuit; According to the sequential of each parallel circuit, to the different time-delay of original clock adding of each parallel circuit, the clock phase that all parallel circuits are used is inequality; With original clock the output signal of each parallel circuit is carried out phase compensation, make all output signals synchronous, as shown in Figure 3.
In the said method, the method that synchronizing sequential circuit is divided into a plurality of parallel circuits is: synchronizing sequential circuit is mapped to directed graph, as shown in Figure 2, gate in the circuit or logic module are mapped to the summit of directed graph, and interconnection line is mapped as the limit of directed graph in the circuit; Above-mentioned directed graph is divided into a plurality of parallel subgraphs, i.e. parallel circuit.
The present invention proposes is divided into synchronizing sequential circuit a plurality of parallel circuits, and its process can be by Fig. 1 and Fig. 2 explanation.With Fig. 1 is example, and the gate in the circuit is abstracted into summit in the directed graph, and interconnection line is abstracted into the limit that connects between the summit, obtains Fig. 2.Directed graph is divided parallel subgraph, can obtain four parallel subgraph P
4, be respectively: { ABC}, { DEFGHI}, { JK}, { LMN}; So can be divided into four parallel circuits in the ifq circuit.
Carry out static timing analysis for each parallel circuit, obtain its sequential situation, determine the employed clock phase of this circuit in conjunction with original clock.Such as obtaining 4 parallel circuits in the last example, need utilize existing Static Timing Analysis Methodology that each parallel circuit is carried out static timing analysis (STA), obtain its sequential, thereby determine to adopt the phase place of clock, determine to use the clock number of out of phase.
Next be the clock that produces out of phase, can obtain by using an existing clock to add different time-delays, as Fig. 3.Also can realize, these two kinds of methods can also be used in combination by special multiphase clock circuit.
When different clocks drives parallel circuit module arrival output,, with regard to using original clock phase compensation is carried out in the output of each parallel circuit, as shown in Figure 3 if subsequent conditioning circuit needs strict sequential unanimity.
Under the stable prerequisite of circuit function, use the clock of respective phase for each parallel circuit, the upset of parallel circuit is staggered constantly as far as possible in time like this, make the electric current in each bar circuit reach peak value in the different moment, thereby reduce the peak current of way circuit, so interconnection line resistance not have under the situation of variation in circuit, reduced current peak total in the circuit, and then the ohm voltage drop (IR Drop) of reduction power/grounding line, shown in figure three.We can see from Fig. 4, the current amplitude and the variation tendency of power supply have all reduced, and have reduced in the circuit because the noise that the LC vibration produces has reduced the voltage amplitude of substrate coupling, thereby have reduced the noise that digital circuit partly is injected into substrate.For the influence of the switching noise that reduces numerical portion in the chip, be a kind of effective means that reduces signal cross-talk to simulation and radio frequency.
Claims (2)
1, a kind of method that reduces power line electric current in the integrated circuit is characterized in that this method comprises following step:
(1) synchronizing sequential circuit is divided into a plurality of parallel circuits;
(2) above-mentioned a plurality of parallel circuits are carried out Time-Series analysis, obtain the sequential of each parallel circuit;
(3) according to the sequential of above-mentioned each parallel circuit, to the different time-delay of original clock adding of each parallel circuit, the clock phase that all parallel circuits are used is inequality;
(4) with original clock the output signal of each parallel circuit is carried out phase compensation, make all output signals synchronous.
2, the method for claim 1 is characterized in that synchronizing sequential circuit is divided into may further comprise the steps the method for a plurality of parallel circuits:
(1) synchronizing sequential circuit is mapped to directed graph, gate in the circuit or logic module are mapped to the summit of directed graph, and interconnection line is mapped as the limit of directed graph in the circuit;
(2) above-mentioned directed graph is divided into a plurality of parallel subgraphs, i.e. parallel circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410037661 CN1571139A (en) | 2004-04-29 | 2004-04-29 | A method for reducing power lead current in integrated circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410037661 CN1571139A (en) | 2004-04-29 | 2004-04-29 | A method for reducing power lead current in integrated circuit |
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| Publication Number | Publication Date |
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| CN1571139A true CN1571139A (en) | 2005-01-26 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102456087A (en) * | 2010-11-03 | 2012-05-16 | 上海华虹集成电路有限责任公司 | Method for repairing establishing timing sequence |
| CN102479264A (en) * | 2010-11-25 | 2012-05-30 | 上海华虹集成电路有限责任公司 | Method for reducing transient power consumption |
| CN107886012A (en) * | 2017-10-28 | 2018-04-06 | 天津大学 | One shot hardware Trojan horse detection method based on gate leve architectural feature |
| CN114389607A (en) * | 2021-12-24 | 2022-04-22 | 莱弗利科技(苏州)有限公司 | Digital-analog hybrid chip with low noise interference |
-
2004
- 2004-04-29 CN CN 200410037661 patent/CN1571139A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102456087A (en) * | 2010-11-03 | 2012-05-16 | 上海华虹集成电路有限责任公司 | Method for repairing establishing timing sequence |
| CN102456087B (en) * | 2010-11-03 | 2013-12-04 | 上海华虹集成电路有限责任公司 | Method for repairing establishing timing sequence |
| CN102479264A (en) * | 2010-11-25 | 2012-05-30 | 上海华虹集成电路有限责任公司 | Method for reducing transient power consumption |
| CN107886012A (en) * | 2017-10-28 | 2018-04-06 | 天津大学 | One shot hardware Trojan horse detection method based on gate leve architectural feature |
| CN114389607A (en) * | 2021-12-24 | 2022-04-22 | 莱弗利科技(苏州)有限公司 | Digital-analog hybrid chip with low noise interference |
| CN114389607B (en) * | 2021-12-24 | 2024-06-04 | 莱弗利科技(苏州)有限公司 | Digital-analog hybrid chip with low noise interference |
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