CN1567594A - Novel ring grid vertical SiGe CMOS device - Google Patents

Abstract

The invention provides a novel annular grid vertical SiGeCMOS device, including: a grid oxide layer, a polycrystalline silicon grid layer, a grid, a source, a drain, an electrode lead wire and a SiO2 isolation region; its characteristic: it also includes in turn a p+-Si1-alpha-betaGealphaCbeta layer growing on a n-Si substrate, a p+-Si1-alpha-betaGealphaCbeta layer (acting as a source region together with the previous one), an intrinsic SiGeC isolation layer, an n-Si1-x-yGexCy channel layer, an intrinsic SiGeC isolation layer, a p+-Si1-alpha-betaGealphaCbeta layer (acting as a drain region) and a Si cap layer between the SiGeC multilayer structure and grid oxide layer. It can replace the current bulk Si MOS device and has the characters of high speed, high frequency, good subthreshold region characteristic, high integrity, etc.

Description

The vertical SiGeC MOS of novel ring grid device

Affiliated technical field

The invention belongs to field of semiconductor devices, it is particularly related to the MOS device.

Background technology:

Be that the characteristic size of the integrated circuit technique of core has reached the 100nm scope at present with the CMOS structure.Further minification faces the restriction of machining accuracy, and characteristic size is dwindled the restriction of the ghost effect (short channel effect, thermoelectronic effect etc.) that brings and the restriction of physics limit.And serviceability is better than the new material of silicon and new device architecture, the technology of available routine, and acquisition is higher than the performance of silicon device and circuit.

Lot of domestic and foreign company, colleges and universities and research unit all are devoted to research and how utilize existing technological level, improve device performance and integrated level.People such as Lothar Risch are at " Vertical MOS transistors with70nm channel length " article (IEEE, Electron.Device, vol.43, p.1495, Sep.1996) middle report adopts vertical structure, utilize existing photoetching level, the thickness of epitaxial growth film is as the channel length of MOSFET, and thin gate oxide is manufactured experimently out raceway groove length and is respectively 170,120 and the nmos device of 70nm (L=70nm be the shortest device of channel length of report) at present.Device has good electrology characteristic, the long 70nm device of raceway groove wherein, and the drain-source saturation current is 500 μ A/ μ m, its mutual conductance reaches 800 μ S/ μ m.Compare with unidimensional planar device, chip area reduces that half is many.But in technologies such as gate oxidation and source leakage implantation annealing, the outdiffusion of source-drain area boron impurity, it is very difficult that the vertical stratification channel length is reduced again; Secondly, owing to use the Si raceway groove, the mobility raising is restricted; Moreover the channel MOS device subthreshold region characteristic of 70nm length is relatively poor.

Existing vertical structure Si MOS device, external existing report.As shown in Figure 1, it adopts p type Si as substrate, is n successively on the substrate ⁺-Si makes raceway groove (channel length is the thickness of channel layer), the n that the MOS device is made in source region, p-Si ⁺-Si does the drain region; Surrounded by gate oxide 3 and polysilicon layer 4 around the above three-decker, the grid of device 5 is drawn by polysilicon layer, and draw in source electrode 6, drain electrode 7 sources by correspondence, drain region.8 is contact conductor, and 9 is SiO ₂Isolated area.Its feature is: channel length enters nanoscale, chip area significantly reduces.But be subjected to the low restriction of Si material transition rate, device speed is difficult to further improve; Next is in technologies such as gate oxidation and source leakage implantation annealing, the outdiffusion of source-drain area boron impurity, and it is very difficult that the vertical stratification channel length is reduced again; Moreover vertical stratification equally also should consider owing to short channel brings some effect, and existing vertical structure Si MOS device is discussed this.

Summary of the invention:

Task of the present invention provides the vertical SiGeC MOS of a kind of novel ring grid device, it is to utilize new material (SiGeC), designs a kind of new MOS device architecture, based on existing conventional Si planar technique, in conjunction with advanced technologies such as MBE, obtain the new device of high-performance, high integration.

The vertical SiGeC MOS of novel ring grid of the present invention device, it comprises: gate oxide 3, polysilicon layer 4, grid 5, source electrode 6, drain electrode 7 and contact conductor 8 and SiO ₂Isolated area 9; It is characterized in that it also comprises: p grows on the n-Si substrate ⁺-Si _{The 1-alpha-beta}Ge _αC _βLayer 16 (doing the source region), SiGeC sandwich construction 1, Si block layer 2 with 13; SiGeC sandwich construction 1 comprises p ⁺-Si _{The 1-alpha-beta}Ge _αC _βLayer 13 (identical and do together source region), intrinsic SiGeC separator 11, n-Si with 16 _1-x-yGe _xC _yChannel layer 12, intrinsic SiGeC separator 11, p ⁺-Si _{The 1-alpha-beta}Ge _αC _βLayer 10 (doing the drain region), more than five layers form column type SiGeC sandwich constructions 1; It between SiGeC sandwich construction 1 and the gate oxide 3 Si block layer 2; Device is by the p that is cuboid ⁺-Si _{The 1-alpha-beta}Ge _αC _βLayer 16 and the cylinder on it are formed, and cylinder divides four layers to be SiGeC sandwich construction 1 (column type), Si block layer 2 (drum type), gate oxide 3 (drum type), polysilicon layer 4 (drum type) successively from inside to outside, shown in Fig. 2,3.

Need to prove that α, β are the component of drain-source district Ge and C, x, y are the component of channel region Ge and C, require β and y less than 1%, and α and x are less than 50%.α, β, x, y optimum value are obtained by Computer Simulation Optimization by deberthing loose measure journey and continuity equation.

Annexation between each layer of the vertical SiGeC MOS of novel ring grid of the present invention device as shown in Figure 3, device is by being cuboid p ⁺-Si _{The 1-alpha-beta}Ge _αC _βLayer 16 and the cylinder on it are formed, and cylinder divides four layers to be SiGeC sandwich construction 1 (column type), Si block layer 2 (drum type), gate oxide 3 (drum type), polycrystal layer 4 (drum type) successively from inside to outside; Described SiGeC multiple layer 1 is a column type, comprises p from the bottom to top ⁺-Si _{The 1-alpha-beta}Ge _αC _βLayer 13, intrinsic SiGeC separator 11, n-Si _1-x-yGe _xC _yLayer 12, intrinsic SiGeC separator 11, P ⁺-Si _{The 1-alpha-beta}Ge _αC _βLayer 10; Source electrode 6 is by bottom p ⁺-Si _{The 1-alpha-beta}Ge _αC _βThin layer 16 is drawn, and drain electrode 7 is by top P ⁺-Si _{The 1-alpha-beta}Ge _αC _βLayer 10 is drawn.

The vertical SiGeC MOS of novel ring grid of the present invention device innovation point is:

(1) Si _1-x-yGe _xC _yMaterial replaces the raceway groove of Si material as device;

(2) adopt intrinsic SiGeC separator;

(3) design Si block layer between channel layer and gate oxide;

(4) Si _{The 1-alpha-beta}Ge _αC _βMaterial replaces the drain-source of Si as device;

(5) gate-all-around structure.

Innovative point of the present invention is mainly based on following principle:

(1) the SiGeC material can obtain than high channel mobility as device channel.Because the character of silicon materials self such as mobility is low, energy gap is fixing etc., cause device speed not high, can't realize the free cutting that can be with etc.In the Si material, add Ge and form the Si of strain _1-xGe _xExponential form increases with the increase of Ge component x for material, its hole mobility, and it is worth greater than hole mobility among the body Si.But the SiGe alloy critical thickness of high Ge content is minimum on the one hand.When SiGe alloy thickness surpasses its critical thickness, the interface will produce a large amount of misfit dislocations.At Si _1-xGe _xIn mix with an amount of instead type C atom and can reduce dependent variable in the alloy effectively, increase critical thickness, make under the situation of high-Ge component, still can guarantee the alloy material strain.Can be by regulating Si _1-x-yGe _xC _yGe component x and C component y (C component y is less than 1%) make Si in the alloy _1-x-yGe _xC _yAlloy keeps high mobility, and the amount of valence band sudden change simultaneously almost remains unchanged.On the other hand,, meet high temperature (T＞800 ℃) SiGe Stress Release, produce defective, have a strong impact on device performance because SiGe is in metastable condition.At Si _1-x-yGe _xIn mix and an amount of instead type C atom, reduce the dependent variable in the alloy, increase thermal stability.Low temperature (T＜800 ℃) needn't be required in the subsequent technique (as oxidation, annealing) again, conventional thermal oxidation and ion implantation technology can be adopted, with existing conventional Si MOS process compatible, the minimizing cost of manufacture.Moreover the surface ratio SiGe of SiGeC epitaxial loayer is smooth more smooth, helps to reduce parameters such as leakage current, and then can improve device performance.

(2) the SiGeC material as raceway groove effectively suppressed drain-source district impurity to the channel region outdiffusion, be expected to realize that vertical structure MOS device channel length further reduces.Because the diffusion coefficient of B atom only is (the identical N of 1/80 among the Si in the SiGeC material ₂Annealing conditions under).

(3) design intrinsic SiGeC makes separator, further isolates drain-source district impurity and spreads to channel region.

(4) design Si block layer between channel layer and gate oxide is avoided when oxidation (even low temperature), and SiGeC channel layer Ge is diffused in the gate oxide, causes quality of oxide layer to reduce, and causes device electric property and reliability to reduce.The design of Si block layer simultaneously can reduce oxide layer and the influence of SiGeC interface scattering to carrier mobility in the SiGeC raceway groove, guarantee simultaneously SiGeC channel layer and Si block a shot layer between the lower interface state density in interface.

(5) adopt vertical, gate-all-around structure, improve the control action of grid, consequently help suppressing short-channel effect and improve the subthreshold region characteristic raceway groove.

Fig. 4 is the present invention's novel ring grid vertical SiGeC MOS device transverse cross-sectional view (vertical view), and dash area 15 is the depleted zone of SiGeC sandwich construction 1.

The depletion-layer capacitance C of per unit area _dFor

$C_d=-\frac{d{Q}_b}{d{\mathrm{\φ}}_s}=\frac{{\mathrm{\ϵ}}_{\mathrm{SiGeC}}}{R\·\ln \frac{R}{R-W_d}}$

Here R=R _SiGeC+ R _Cap, R _SiGeCBe the radius of SiGeC cylinder, R _CapThe thickness that is Si block layer (exhausting) is definite value, and R is relevant with gate voltage.R Wd, W _dThickness for depletion layer.Q _bBe the depletion layer charge of per unit area, Φ s is a surface potential, ε _SiGeCDielectric constant for the SiGeC material.Can derive by following formula

$\frac{d{C}_d}{\mathrm{dR}}=-{\mathrm{\ϵ}}_{\mathrm{SiGeC}}{(R\·\ln \frac{R}{R-W_d})}^{-2}\·(\ln \frac{R}{R-W_d}-\frac{R}{R-W_d}+1)$

Because R is Wd, so following formula is greater than 0.When R, become the planar structure device.Along with SiGeC cylindrical radius R _SiGeC(the thickness R of Si block layer _CapBe definite value) reduce depletion-layer capacitance C _dReduce, up to working as R=W _dThe time, C _dBecome 0.

Can be similar to the S relational expression reciprocal that draws subthreshold region transfer characteristic slope

$S=\frac{\mathrm{KT}}{q}\·\ln 10(1+\frac{C_d}{C_{\mathrm{OX}}})$

Here C _OXBe the electric capacity of oxide layer, k is a Boltzmann constant, and T is the device operating ambient temperature, and q is a unit quantity of electricity.Along with depletion-layer capacitance C _dReduce, S will reduce, and subthreshold region transfer characteristic curve slope increases, the curve steepening, and the subthreshold region characteristic improves.

For ring grid SiGeC MOS structure, in case the SiGeC cylinder is exhausted fully, grid voltage continues to increase, and the electric charge of depletion layer can not increase yet again, but electric charge will improve in surface potential and the inversion layer, cause depletion-layer capacitance C _dReduce rapidly.Very little in the SiGeC cylindrical radius, when highly (channel length L) was enough big, the ideal value of S was kT/q ln (10).And planar S i MOS structure is at subthreshold region, continue to increase with grid voltage, the electric charge of depletion layer increases, though surface potential also increases, but its depletion-layer capacitance is obviously big than ring grid SiGeC MOS structure, be that its S factor is also relatively large, illustrate that ring grid SiGeC MOS structure has better subthreshold region characteristic than planar structure.

(7) Si _{The 1-alpha-beta}Ge _αC _βMaterial is regulated Ge component α and C component β and channel region alloy Si in the alloy as drain-source _1-x-yGe _xC _yGe component x and C component y make Si in the alloy _{The 1-alpha-beta}Ge _αC _βThe energy gap in drain-source district is lower than Si _1-x-yGe _xC _yChannel region, that realizes two district's materials can be with biasing, helps suppressing SCE and DIBL effect.

The vertical SiGeC MOS of novel ring grid device can be used for replacing present Si MOS device, utilizes existing processes, overcomes the restriction of photoetching level, produce have high-performance, high integration MOS device.

The basic functional principle of ring grid SiGeC MOS device is: under normal utilization, the source electrode 6 of SiGeCPMOSFET pipe (enhancement mode) is in zero potential, and drain electrode 7 connects negative potential.If grid 5 is in zero potential, because the source region is a p to the drain region ⁺-n-p ⁺Structure, thus drain 7 and source electrode 6 between just can not have electric current to pass through, have only minimum p-n junction reverse saturation current.But when grid 5 adds negative potential V _GS, and greater than cut-in voltage V _TThe time, the sensed p-type inversion layer that formed in n type SiGeC channel layer surface of grid inboard couples together identical source region of conduction type and drain region.At this moment, 7 add negative potential, just have the hole to flow to the drain region along the Z direction, form the drain current that flows to drain electrode 7 from source electrode 6, as shown in Figure 4 from the source region by the SiGeC raceway groove if drain.

Work as V _DSBe one when very little, the raceway groove of responding between source region and the drain region will resemble a resistance.

Work as V _DSDuring increase,, make near potential difference between drain electrode 7 one end grids 5 and the raceway groove along the voltage drop on the raceway groove to be (V because leakage current increases _GS-V _DS), less than near the electrical potential difference of source electrode 6 one ends, thereby the electric field that grid 5 produces on silicon face weakens, cause channel thickness from the source to leaking along raceway groove attenuation gradually, the result causes channel resistance to increase.So, work as V _DSWhen increasing gradually, I _DIncreased slack-off (linear district).Work as V _DSBe increased to V _Dsat=V _GS-V _TThe time, on the close raceway groove of drain terminal, the electric field that produces on the gate surface can not have been kept any inversion layer charge again, so inversion layer disappears only remaining depletion region on the silicon face of close leakage one end.At this moment, by pinch off, the drain current of metal-oxide-semiconductor begins saturated raceway groove near drain terminal.

Work as V _DS＞V _DsatThe time, dropping near the Lou voltage increase of depletion region, it is big that depletion region thickness becomes, and pinch-off point is mobile slightly to the source end.If ignore moving of pinch-off point, then drain current I _DTo not increase, remain on saturation value I with drain voltage _Dsat(saturation region).

Work as V _DS＞BV _DSAfter, the living avalanche breakdown of binding up one's hair of leakage-substrate, this is V _DSIncrease slightly, leakage current just sharply increases, and enters cut-off region.

Indulge the above, the vertical SiGeC MOS of novel ring grid of the present invention device has following characteristics:

(1) at a high speed high frequency;

(2) the subthreshold region characteristic is good;

(3) high integration;

(4) help suppressing SCE and DIBL effect.

Accompanying drawing and drawing explanation:

Fig. 1 is the longitudinal profile structure chart of existing vertical structure Si nmos device

Wherein, adopting p type Si as substrate, is the n that does the source region above successively ⁺-Si layer, as raceway groove p-Si layer, as the n in drain region ⁺-Si layer is gate oxide 3 and polysilicon layer 4 around the above-mentioned three-decker, and the grid 5 of device is drawn by polysilicon layer 4, and source electrode 6, drain electrode 7 are drawn by the source-drain area of correspondence, and 8 is contact conductor, and 9 is SiO ₂Isolated area.

Fig. 2 is the vertical SiGeC MOS of a novel ring grid of the present invention device longitudinal sectional drawing.

P grows on the n-Si substrate ⁺-Si _{The 1-alpha-beta}Ge _αC _βLayer 16 (with 13 as the source region) is the SiGeC sandwich construction on it, is p successively ⁺-Si _{The 1-alpha-beta}Ge _αC _βLayer 13 (with 16 as the source region), intrinsic SiGeC separator 11, n-Si _1-x-yGe _xC _yLayer 12 (as raceway groove), intrinsic SiGeC separator 11, P ⁺-Si _{The 1-alpha-beta}Ge _αC _βLayer 10 (as drain region); Surrounded successively by Si block layer 2, gate oxide 3 and polysilicon layer 4 fully around the above five-layer structure, source electrode 6 is by p ⁺-Si _{The 1-alpha-beta}Ge _αC _βLayer 16 is drawn, drain electrode 7 p by top layer ⁺-Si _{The 1-alpha-beta}Ge _αC _βDraw in layer drain region 10, and grid 5 is drawn by polysilicon layer 4, and 8 is contact conductor, and 9 is isolated area.

Fig. 3 is the vertical SiGeC MOS of novel ring grid of the present invention device external form figure.

The p that is cuboid ⁺-Si _{The 1-alpha-beta}Ge _αC _βBeing the sandwich construction of column type on the thin layer 16, dividing four layers from inside to outside, is SiGeC layer 1 (cylinder), Si layer 2 (drum), gate oxide 3 (drum), polysilicon layer 4 (drum) successively; Source electrode 6 is by cuboid p ⁺-Si _{The 1-alpha-beta}Ge _αC _βThin layer 16 is drawn, and drain electrode 7 is by top P ⁺-Si _{The 1-alpha-beta}Ge _αC _βLayer 10 is drawn, and grid 5 is drawn by polysilicon layer.

Fig. 4 is the vertical SiGeC MOS of a novel ring grid of the present invention device transverse cross-sectional view

Behind drain-source district added electric field, 15 is depleted zone, comprises the part and the Si block layer 2 of column type SiGeC layer 1; Center white portion 14 is the remaining SiGeC that do not exhaust; Outside depleted region 15, be gate oxide 3 and polysilicon layer 4; R is radius and Si block layer 2 (drum) thickness sum of SiGeC layer 1 (cylinder), W _dThickness for depletion layer.

Fig. 5 is the fundamental diagram of the vertical SiGeC MOS of novel ring grid of the present invention device

Wherein, 2 are Si block layer, and 3 is gate oxide, and 4 is polysilicon layer; Source electrode 6 ground connection, drain electrode 7 connects negative potential, and grid 5 connects negative potential.

Claims (2)

1, the vertical SiGeC MOS of a kind of novel ring grid device, it comprises: gate oxide (3), polysilicon layer (4), grid (5), source electrode (6), drain electrode (7) and contact conductor (8) and SiO ₂Isolated area (9); It is characterized in that it also comprises: be grown in p on the n-Si substrate ⁺-Si _{The 1-alpha-beta}Ge _αC _βLayer (16), SiGeC sandwich construction (1), Si block layer (2); SiGeC sandwich construction (1) comprises p ⁺-Si _{The 1-alpha-beta}Ge _αC _βLayer (13) (with 16 as the source region), intrinsic SiGeC separator (11), n-Si _1-x-yGe _xC _yChannel layer (12), intrinsic SiGeC separator (11), p ⁺-Si _{The 1-alpha-beta}Ge _αC _βLayer (10), more than five layers form column type SiGeC sandwich constructions (1); It between SiGeC sandwich construction (1) and gate oxide (3) Si block layer (2); Device is by the p that is cuboid ⁺-Si _{The 1-alpha-beta}Ge _αC _βLayer (16) and the cylinder on it are formed, and cylinder divides four layers from inside to outside, are SiGeC sandwich construction (1) (column type), Si block layer (2) (drum type), gate oxide (3) (drum type), polysilicon layer (4) (drum type) successively.

2, the vertical SiGeC MOS of a kind of novel ring grid according to claim 1 device is characterized in that described α, β are the component of drain-source district Ge and C, and x, y are the component of channel region Ge and C, require β and y less than 1%, and α and x are less than 50%; α, β, x, y optimum value can be obtained by Computer Simulation Optimization by deberthing loose measure journey and continuity equation.

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