CN1567589A - High-density integrated circuit - Google Patents

Abstract

The present invention provides a high density integrated circuit. Plural integrated circuit layers in the high density integrated circuit are integrated to one chip in vertical direction; each integrated circuit has a certain independent memory, logic and/or analog function, the interlayer connecting passage ports couple the different integrated circuit. The invention further improves the high density integrated circuit having a memory, such as provides wiring subareas to facility the wiring; uses a buffer to advance speed and uses user program memory matrix as excess array in order to improve rate of finished products.

Description

High density integrated circuit

The present invention is that application number is 99813068.0, denomination of invention is divided an application for the application for a patent for invention of " high density integrated circuit ".

Technical field

The present invention relates to integrated circuit fields, or rather, relate to high density integrated circuit.

Background technology

Super large rule film integrated circuit has been obtained brilliant achievement so far.In the prior art of very lagre scale integrated circuit (VLSIC), the transistor with certain logic/memory/analog functuion is manufactured on the semi-conductive substrate.This just represents that these transistors are to be arranged in a two-dimensional space, promptly on the Semiconductor substrate plane.Therefore, for certain chip area, transistorized number is limited, correspondingly, the function of chip also is restricted, simultaneously, the function of system such as PC (PC) can only be distributed on several chips, and the I/O of these chips (I/O) pin has greatly limited the data transmission bauds (because the number of pins of a chip is limited) between these chips.This brings many difficulties for further developing of computer, and for example, the increasing speed official post between microprocessor and the memory further improves very difficulty of computer speed.

Correspondingly, monolithic system (System-on-a-chip) with systemic-function is suggested a solution as these problems.A good example is that DRAM (dynamic random access memory) and microprocessor are integrated on the chip.Like this, transmit data by internal bus between DRAM and the microprocessor.And the width of internal bus is restricted unlike the I/O pin, and its number can be unlimited.Therefore, in theory, the data transmission bauds between DRAM and the microprocessor can be very fast.This is a well design, if but DRAM and microprocessor realize according to the manufacture method of custom integrated circuit that still that is to say on the Semiconductor substrate that is manufactured on a two dimension, it has several potential problems.At first, because DRAM and microprocessor are distributed on two-dimensional space, DRAM is merely able to be placed on the next door of microprocessor.Like this, the transfer of data between the relative both sides, DRAM and the microprocessor outside can be because apart from too far away and slack-off.Another aspect, because they build a two-dimensional space in, the transistor density of DRAM and microprocessor (transistor size on the unit are) is restricted.Therefore, their function also is subjected to certain limitation.The 3rd potential problems are that this design does not comprise nonvolatile storage as yet.Therefore it need be from information extraction on nonvolatile external memory chip or the hard disk, and it is unfavorable that this performance to chip improves.

Disclosure of an invention

The high density integrated circuit that the purpose of this invention is to provide that a kind of computing is quick, function is strong, it is convenient to use, can just can make by prior art.

The objective of the invention is that this technical scheme of three dimensions realizes by circuit element is distributed in.Described high density integrated circuit possesses: contain first integrated circuit layer of at least one first circuit element, other circuit element coupling on described first circuit element and described first integrated circuit layer; Second integrated circuit layer that contains at least one second circuit element, other circuit element coupling on described second circuit element and described second integrated circuit layer; One layer insulation dielectric layer between described first integrated circuit layer and described second integrated circuit layer; At least one passes described layer insulation dielectric layer and will described first integrated circuit layer and the interlayer interface channel mouth that is coupled of described second integrated circuit layer.Integrated circuit layer of the present invention is overlapped, and one is layered on another layer.Every layer of integrated circuit layer has necessarily independently logic, memory and/or analog functuion, that is to say, contains the circuit function block of logical block, block of memory and/or simulated block etc. in each integrated circuit layer.Between each layer integrated circuit layer, the effect of data line is played in interlayer interface channel hole.Because interlayer interface channel hole is at chip internal, its number is unrestricted.Therefore, the bandwidth of transfer of data is unrestricted.Simultaneously, because transistor is disposed in three dimensions, the function of chip also can greatly improve.For example, an integrated circuit layer can provide microprocessor and some nonvolatile storage functions, and another integrated circuit layer can be as the function of RAM.These possibilities are infinite.

In recent years, the maturation of thin-film transistor (TFT) and chemico-mechanical polishing (CMP) makes the realization of high density integrated circuit have possibility.Thin-film transistor technologies grows up in liquid crystal display industry at first.Transistor is to be manufactured on the glass substrate.Transistor is manufactured on the glass substrate and Semiconductor substrate on the difference of what essence not.Thin-film transistor in the liquid crystal display industry can similarly be applied in the semi-conductor industry.Be different from general integrated circuit, thin-film transistor is manufactured on transistor on the semiconductor film, and need be on a Semiconductor substrate, therefore, can different thin film transistor integrated circuit layers is overlapped, to form high density integrated circuit.A thin film transistor integrated circuit layer can independently be finished certain logic, memory and/or analog functuion.

Because the thin film transistor integrated circuit layer is overlapped, following thin film transistor integrated circuit layer is necessary for top integrated circuit layer a good basis is provided.Utilize chemical Mechanical Polishing Technique, this task can be finished easily.One dielectric is deposited on the thin film transistor integrated circuit layer and filling space wherein, uses CMP (Chemical Mechanical Polishing) process with its surfacingization afterwards.Therefore, another thin film transistor integrated circuit layer can generate at an easy rate in the above.Repeat these steps, can make high density integrated circuit.

Advantage of the present invention is that volume is little, function is strong, performance is good, computing is quick, application is convenient, utilizes prior art to make.Utilize the present invention that the realization of monolithic system (System-on-a-chip) to some extent may.

Simultaneously, the present invention has done further perfect to the high density integrated circuit that contains memory, as provides the wiring subregion with convenient wiring; Use buffer to improve speed; Use the user program storage matrix as unnecessary array to improve rate of finished products etc.

Brief description of drawings

Below in conjunction with drawings and Examples high density integrated circuit of the present invention is elaborated.

Fig. 1 is the structure section schematic diagram of embodiment 1.

Fig. 2 is the structure section schematic diagram of embodiment 2.

Fig. 3 one contains the perspective view of the high density integrated circuit of three-dimensional storage.It contains one deck substrate integrated circuit layer (SUIC) and the two-layer substrate integrated circuit layer (ASIL) that is higher than, and this two ASIL layer all contains memory.

Fig. 4 is a perspective view with high density integrated circuit of wiring channel.

Fig. 5 A, Fig. 5 B, Fig. 5 C, Fig. 5 D are the plane graphs of metal line on different ASIL layers.

Fig. 6 is the perspective block diagram of a high density integrated circuit.Contain a read-only memory (ROM) on its ASIL 100, contain the cache memory relevant on the SUIC000 with this ROM.

Fig. 7 is the perspective block diagram of a high density integrated circuit.Contain a memory that constitutes by thin-film transistor on its ASIL 100, contain the cache memory relevant on the SUIC 000 with this memory.

Fig. 8 is the block diagram of another high density integrated circuit.Contain a masking film program read-only memory (MPROM) on its ASIL 100, contain unnecessary electric programming read-only memory (EPROM) array relevant on the SUIC 000 with this MPROM.

Realize best mode of the present invention

Embodiment 1:

Figure 1 shows that one has a substrate integrated circuit layer (SUIC 000) and two sectional drawings that are higher than the high density integrated circuit of substrate integrated circuit layer (ASIL100 and 200).The structure of SUIC 000 is identical with the standard integrated circuit.It comprises active element, as field effect transistor (MOS) 99a, 99b etc.These field effect transistor 99a, 99b...... build on the semi-conductive substrate 10, comprise a gate electrode 1, one gate insulation layer 2, leakage/source 3.In this embodiment, field effect transistor (MOS) is used as an example.Also can use the active element of triode and other form.Substrate field domain 4 is isolated transistor mutually on substrate 10.Be linked together by access opening 6 and metal line 7 between the transistor.For clarity, the layer of metal wiring 7 of only having drawn here.In fact, the metal wire 7 on the SUIC 000 can be a multilayer as the standard integrated circuit.SUIC 000 also can contain passive component, as resistance, inductance etc.Therefore SUIC 000 can have logic, memory and/or analog functuion.

SUIC000 covered by dielectric insulating film between from level to level 20, this layer by layer between deielectric-coating 20 filled SUIC000 and gone up space between metal line.The processing step of one dielectric planarization is with 20 complanations of inter-level dielectric film afterwards.Like this, be ASIL 100 flat dielectric surface all set.

Be similar to SUIC 000, ASIL 100 includes active element, as thin- film transistor 199a, 199b etc.Thin- film transistor 199a, 199b are manufactured on the semiconductor film 110 that approaches, and it has a gate electrode 101, one gate insulation layers 102, leakage/source 103.Semiconductor film 110 can use the semi-conducting material as silicon, germanium, GaAs and so on.This semiconductor film 110 can be non-setting attitude, polycrystalline attitude or monocrystalline.Thin-film transistor is isolated mutually by field domain 104.In this embodiment, semiconductor film 110 is identical with the thickness of field domain 104.In fact, the thickness of semiconductor film 110 can be greater than the thickness of field domain 104.In this embodiment, the transistor 99a on thin- film transistor 199a, 199b and the substrate, the similar of 99b.......Concrete technological process of making thin-film transistor can be found on a lot of lists of references, is CN 1108004A, open day to be the invention " transistor and manufacture method thereof " in September 6 nineteen ninety-five as publication number.Similarly, also can have all on this layer ASIL 100 as if the active element that triode is the same and/or all passive components like an elephant resistance, inductance etc.

In ASIL 100, intercouple by access opening 106 and metal line 107 between the thin-film transistor.Similarly, which floor the metal line among the ASIL 100 also can have.These thin-film transistors that intercouple can have necessarily independently logic, memory and/or analog functuion.That is to say that even one deck ASIL, it also can possess many functions.In the same way, the high density integrated circuit that is made of multilayer ASIL eclipsed form then possesses more function.

Interlayer interface channel hole 190a0,290a0...... form in inter-level dielectric 20.Interlayer interface channel hole 190a0 provides the coupling between ASIL 100 and the SUIC 000.Therefore, the integrated circuit on different layers can mutual data transmission/instruction.Because interlayer interface channel hole 190a0,290a0 are the inside at high density integrated circuit, their size can be very little, and can lean on very closely, and therefore, the bandwidth of transfer of data is very big between layer and the layer.In other words, high density integrated circuit has very high arithmetic speed.

After forming thin- film transistor 199a, 199b and metal line 107, form an interlayer dielectric insulating film 120 thereon and with its complanation.On this dielectric insulating film, can form another and be higher than substrate integrated circuit layer ASIL 200 as a same reason.Similarly, ASIL 200 contains semiconductor film 210, and forms thin- film transistor 299a, 299b...... thereon.These thin- film transistors 299a, 299b...... also have gate electrode 201, gate insulation layer 202, and leakage/source 203 keeps apart mutually by field domain 204 between them.Thin- film transistor 299a, 299b...... intercouple by access opening 206 and metal line 207 simultaneously.Interlayer interface channel hole 290a1 passes the metal wire coupling on inter-level dielectric 120 and the ASIL 100.Interlayer interface channel hole 290a1 and 290a0 merge and are called contact channels hole 290a, and it provides thin-film transistor 299c on the ASIL 200 and the coupling between the substrate 10.Repeat above step, form more multi-layered high density integrated circuit.

Embodiment 2:

Fig. 2 provides the embodiment of another high density integrated circuit.This embodiment and the comparison of Fig. 1 in the past, the thin-film transistor structure on the ASIL 200 is different.In this embodiment, the structure of thin- film transistor 299a, 299b, 299c...... is put upside down, and its gate electrode 201 is below leakage/source 203 and gate insulation layer 202.This thin-film transistor structure of putting upside down is very common in liquid crystal display industry.Making the method for this (inverted) thin-film transistor of putting upside down, can be CN 1108004A, open day to be the invention " transistor and manufacture method thereof " in September 6 nineteen ninety-five with reference to publication number.The place that the another one of this embodiment is different is that thin-film transistor 299a...... can be formed on access opening 206a and the metal line 207a top of this ASIL 200.This structure brings more convenience can for the design of integrated circuit.

Fig. 3 one contains the perspective view of the high density integrated circuit of three-dimensional storage.It contains one deck substrate integrated circuit layer (SUIC) and the two-layer substrate integrated circuit layer (ASIL) that is higher than, and this two ASIL layer all contains memory.Be similar to Fig. 1 and Fig. 2, the metal line that SUIC 000 contains transistor and they are intercoupled.For simplifying drawing, only represent substrate integrated circuit layer SUIC 000 here with a plane.Contain storage element 296aa, 296ab...... and word line 292a...... and the bit line 293a...... relevant on the ASIL 200 with them.Here, the layout of storage element and word/bit line and standard integrated circuit are similar.Storage element 296aa, 296ab...... can be random access memory unit (RAM) or non-volatile memories unit.It can contain active or/and passive component.The structure of storage element and technological process can be found on many reference books, as works " microcomputer theory of constitution " such as Qi Qi P.193～199, have just repeated no more here.Contact channels hole 290a...... forms electrical connection between word line 292a...... and substrate 10.Word line 292a...... joins at ASIL contact point 295a2 place and contact channels hole 290a; Contact channels hole 290a joins at SUIC contact point 295a0 place and substrate 10; Bit line 293a joins at ASIL contact point 294a2 place and contact channels hole 291a; Contact channels hole 291a joins at SUIC contact point 294a0 place and substrate 10.Similarly, ASIL 100 contains storage element 196aa, 196ab...... and corresponding word line 192a...... and bit line 193a.......The layout of storage element and word/bit line is similar to the standard integrated circuit.Contact channels hole 190a...... forms electrical connection between word line 192a...... and substrate 10.Word line 192a...... joins at ASIL contact point 195a1 place and contact channels hole 190a, and contact channels hole 190a joins at SUIC contact point 195a0 place and substrate 10.Bit line 193a joins at ASIL contact point 194a1 place and contact channels hole 191a, and contact channels hole 191a joins at SUIC contact point 194a0 place and substrate 10.Here, memory layer can be just not two-layer, can be multilayer yet.Clearly, this memory device is placed on three-dimensional high density integrated circuit, promptly three-dimensional storage can greatly improve memory span.

Fig. 4 has shown the perspective view of a high density integrated circuit metal line.On ASIL 200, metal wire 293a～293h and their contact channels hole 290a～290h are separately formed two subregions, subregion A: metal wire 293a～293d and contact channels hole 290a～290d; Subregion B: metal wire 293e～293h and contact channels hole 290e～290h.Here, metal wire 293a～293h bends extension on ASIL 200, and the plane that is formed by contact channels hole 290a～290d and 290e～290h is parallel to each other like this, and has a space between this.This space is called as wiring path 170a, 170b, and the metal wire 175a～175d below ASIL 200 can be passed through.This more can be clear that in Fig. 5 C, Fig. 5 D.

In Fig. 5 A and Fig. 5 B, the metal wire 293a～293h on the ASIL 200 is a straight line, not bending.Their ASIL contact point 294a2～294h2 separately form straight line.This makes the metal wire below the ASIL 200 have only considerably less space can pass the plane that is formed by contact channels hole 290a～290h.Therefore, there is a strong possibility must finish before they arrive contact channels hole 290a～290h for the metal wire 193a～193h on the ASIL 100.Transfer of data between like this may limiting layer.

Another kind of circuit design, as shown in Fig. 4, Fig. 5 C and Fig. 5 D, metal wire 293a～293h is that bending is extended, so their ASIL contact point 294a～294d, 294e～294h forms two planes, and the distance between these two planes is much larger than the width of metal wire.Therefore, the metal wire 175a～175d on the ASIL 100 can unimpededly pass.Correspondingly, the performance of integrated circuit is improved.Simultaneously, Fig. 5 A, Fig. 5 B and Fig. 5 C, Fig. 5 D compare, and each spacing of contact channels hole 290a～290h can not be changed by each spacing decision of metal wire 293a～293h among Fig. 5 A, Fig. 5 B; And the spacing between contact channels hole 290a～290d and the 290e～290h can be adjusted arbitrarily among Fig. 5 C, Fig. 5 D, and therefore, the circuit design of Fig. 5 C, Fig. 5 D is more simple.

Fig. 6 is the perspective block diagram of a high density integrated circuit.Contain a read-only memory (ROM) on its ASIL 100, contain the cache memory relevant on the SUIC 000 with this ROM.Read-only memory on ASIL 100 (ROM) array comprises word line 193a, 193b......, bit line 192a, 192b...... and read-only storage element 196aa, 196ab.......Read-only storage element can have some simple structures, such as using a nonlinear resistance as read-only storage element.In this embodiment, do not have active element on the ASIL 100, thereby its manufacturing process is fairly simple.In order to read the digital information in the ROM array, the signal of telecommunication transmits mutually by contact channels mouth 190a～190j and substrate 10.Have sense amplifier 61a～61j on substrate, it will become from the signal of telecommunication that the ROM array comes makes digital signal.Here sense amplifier 61a～61j is an example of simulated block.Substrate 10 also has transmission control gate 51a～51j and cache memory 90.They play the effect of a buffer concerning the ROM array.Transmission control gate 51a～51j controls by a control signal 50.When it allowed transmission, the digital information that is latched on sense amplifier 61a～61j was transferred in the cache memory 90 simultaneously.Cache memory 90 has storage element 96aa, 96ab......, and their relevant word-line/bit- line 92a, 92b......, 93a, 93b.......Other of high density integrated circuit chip partly as microprocessor 80, can read information in the cache memory 90 by address decoder 70.Here microprocessor 80 and address decoder 70 are some examples of logical block.Because playing the contact channels mouth 190a～190j of tie effect between cache memory 90 and ROM array is at chip internal, its number can be unrestricted.In other words, the data transmission bauds between ROM array and the cache memory can be very fast.Correspondingly, the performance issue brought of the velocity contrast of microprocessor and ROM array can be resolved.Here, cache memory can be random access memory or other high-speed memory.When read operation, among the ROM on word line the information of a plurality of storage elements be transferred in the cache memory simultaneously.

Fig. 7 is the perspective block diagram of a high density integrated circuit.Contain a memory that constitutes by thin-film transistor on its ASIL 100, contain the cache memory relevant on the SUIC 000 with this memory.Because contain active element on the ASIL 100, thereby can generate sense amplifier 161a...... (simulated block) in the above, address decoder 171 (logical block) and other circuit.They are by transmitting data between contact channels mouth 190a～190j and the SUIC 000.Similarly, can contain high-speed buffer 90 and microprocessor 80 on the SUIC 000.Because the number of contact channels mouth 190a～190j is unrestricted, use the high density integrated circuit of this embodiment that very fast speed can be arranged.

Fig. 6 and Fig. 7 just explain the method for cache memory as buffer as two examples.In fact, the method as buffer can be applied in the high density integrated circuit in the prior art.

Fig. 8 is the block diagram of another high density integrated circuit.Contain a masking film program read-only memory (MPROM) on its ASIL 100, contain unnecessary electric programming read-only memory (EPROM) array relevant on the SUIC 000 with this MPROM.Here, except electric programming read-only memory, can also use any electric programmable memory as unnecessary array.In the manufacture process of integrated circuit, can run into defective circuit inevitably.For fear of the reduction of rate of finished products, need to use the method for unnecessary array.In this embodiment, a masking film program read-only memory (MPROM) 197 is arranged on the ASIL 100.MPROM 197 can have very simple structure and manufacture method.In test process, if there is the storage element in the delegation 198 to find defectiveness, this word line is shown by taboo and reads so, and the information on it is stored in the delegation 94 of an electric programming read-only memory (EPROM) 87.The row address of defectiveness capable 198 is stored in the EPROM array 85 as a label among the MPROM 197 simultaneously.Use EPROM that we are write the information of unnecessary array after chip testing again.Read to require and a row address 81 when being admitted to when one, row address 81 at first each label in comparator 84 and EPROM array 85 is compared.If an identical situation is arranged, control signal 83 will inform that it is output (Dout) 94 that MUX 91 is selected the output 93 of EPROM87.If do not have identically, control signal 83 will be selected row suitable among the MPROM 197, and with its output 92 as memory output 94.Equally, the unnecessary array approach in any standard integrated circuit can use in the high density integrated circuit, and for example, any one can all can be used as unnecessary array by the memory that the user rewrites.

Though some embodiments of the present invention are described in specification, those skilled in the art should recognize, under the prerequisite away from the spirit and scope of the present invention not, can change form of the present invention and details.Therefore, except the spirit according to additional claims, the present invention should not be subjected to any restriction.

Claims (10)

1. high density integrated circuit, it comprises a substrate integrated circuit layer (SUIC000) and at least one and is stacked and placed on and is higher than the substrate accumulation layer on this substrate integrated circuit layer, this is higher than the substrate accumulation layer and contains at least two first, second parallel, adjacent address addressing lines (293a, 293b), and described address addressing line is characterised in that:

In the memory array of described accumulation layer, described first, second address addressing line is along the first direction extension and have first spacing;

Outside the memory array of described accumulation layer, the bearing of trend of described first, second address addressing line departs from first direction, the described first address addressing line (293a) contacts with substrate by the first contact channels hole (290a), the described second address addressing line (293b) contacts with substrate by the second contact channels hole (290b), and the spacing in the described first and second contact channels holes is greater than first spacing.

2. high density integrated circuit, it comprises a substrate integrated circuit layer (SUIC000) and at least one and is stacked and placed on and is higher than the substrate accumulation layer on this substrate integrated circuit layer, this is higher than the substrate accumulation layer and contains at least two first, second parallel, adjacent address addressing lines (293a, 293b), and described address addressing line is characterised in that:

In the memory array of described accumulation layer, described first, second address addressing line extends along first direction;

Outside the memory array of described accumulation layer, the bearing of trend of described first, second address addressing line departs from first direction, the described first address addressing line (293a) contacts with substrate by the first contact channels hole (290a), the described second address addressing line (293b) contacts line direction out of plumb and this first direction that the described first and second contact channels holes are constituted by the second contact channels hole (290b) with substrate.

3. high density integrated circuit, it comprises a substrate integrated circuit layer (SUIC000), at least one interconnection line layer (170a...) and at least one being stacked and placed on that is stacked and placed on this substrate integrated circuit layer is higher than the substrate accumulation layer on this interconnection line layer, this is higher than the substrate accumulation layer and contains many parallel, adjacent address addressing lines (293a...), described address addressing line contains first, second adjacent address addressing line subregion (A, B) of at least two groups, and described address addressing line subregion is characterised in that:

The first address addressing line subregion (A) contains at least one first address addressing line (293a), and this first address addressing line contacts with substrate by the first contact channels hole (290a);

The second address addressing line subregion (B) contains at least one second address addressing line (293e), this second address addressing line is identical in this residing position of first address addressing line subregion with this this first address addressing line in this residing position of second address addressing line subregion, and this second address addressing line contacts with substrate by the second contact channels hole (290e);

In this interconnection line layer, the space between the described first and second contact channels holes allows at least one interconnection line (175a) to pass through.

4. high density integrated circuit is characterized in that containing:

One substrate (10) and be positioned at substrate integrated circuit layer (SUIC000) on this substrate, this substrate integrated circuit layer contains a substrate memory array (90);

At least one being stacked and placed on is higher than substrate integrated circuit layer (ASIL100) on this substrate, this element that is higher than in the substrate integrated circuit layer is made of non-single crystalline semiconductor material, and this is higher than the substrate integrated circuit layer and contains at least one substrate memory array (196aa...) that is higher than;

A plurality ofly be higher than contact channels hole (190a...) between the substrate integrated circuit layer at this substrate and this, describedly be higher than the substrate memory array and described substrate memory array is carried out handshaking by described contact channels hole, and can near small part its information stores of being stored in described substrate memory array to small part, described substrate memory array is classified the described buffer that is higher than the substrate memory array as.

5. high density integrated circuit according to claim 4 is characterized in that: the described substrate memory array that is higher than contains at least one active element.

6. high density integrated circuit according to claim 5 is characterized in that: described active element is a thin-film transistor.

7. high density integrated circuit according to claim 4 is characterized in that: described thin-film transistor is an inversion thin-film transistor.

8. high density integrated circuit according to claim 4 is characterized in that: the described substrate memory array that is higher than contains at least one passive component.

9. high density integrated circuit according to claim 5 is characterized in that: described passive component is a nonlinear resistance.

10. high density integrated circuit according to claim 4 is characterized in that: described substrate memory array contains at least one random access memory unit (RAM) and/or non-volatile memories unit (NVM).

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