CN1567482A - Automatic variable timing structure for recovering writing using low speed tester - Google Patents
Automatic variable timing structure for recovering writing using low speed tester Download PDFInfo
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- CN1567482A CN1567482A CN 03142980 CN03142980A CN1567482A CN 1567482 A CN1567482 A CN 1567482A CN 03142980 CN03142980 CN 03142980 CN 03142980 A CN03142980 A CN 03142980A CN 1567482 A CN1567482 A CN 1567482A
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- 238000012360 testing method Methods 0.000 claims abstract description 102
- 238000000034 method Methods 0.000 claims abstract description 35
- 239000003990 capacitor Substances 0.000 claims description 22
- 230000004087 circulation Effects 0.000 claims description 17
- 238000007600 charging Methods 0.000 claims description 10
- 239000000523 sample Substances 0.000 claims description 10
- 238000011084 recovery Methods 0.000 claims description 9
- 230000006870 function Effects 0.000 claims description 8
- 230000001360 synchronised effect Effects 0.000 claims description 7
- 230000007423 decrease Effects 0.000 claims description 6
- 230000004048 modification Effects 0.000 claims description 5
- 238000012986 modification Methods 0.000 claims description 5
- 238000010998 test method Methods 0.000 claims description 5
- 230000001351 cycling effect Effects 0.000 claims 2
- 230000000977 initiatory effect Effects 0.000 claims 2
- 230000000873 masking effect Effects 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 9
- 230000003068 static effect Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 238000013500 data storage Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 230000004083 survival effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
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Abstract
This invention can provide a new method to test the DRAM cell by using slow run tester. It can provide a kind of adjustable automatic timing structure to resume writing when using slow run tester to test the DRAM element. The automatic timing controlled CSL and WL pulse wave can simulate the operation of DRAM by this mean under different condition. The adjustable automatic timing structure can mask resuming writing (twr) according to the on-site requirement of DRAM cell. The slow run tester can exert the masking function.
Description
Technical field
The invention relates to a kind of making of integrated circuit component, in particular to a kind of when carrying out chip probe test (chip probe testing), the method that is used to test DRAM component failure position (failing bits).
Technical background
" Dynamic Random Access Memory " (DRAM, Dynamic Random Access Memory) chip with " SRAM " (SRAM, Static Random Access Memory) is data storage and the memory means that are widely used in the semiconductor technology.One single DRAM unit (cell) stores one data as electric charge on a capacitor, and typical DRAM unit comprises the single capacitor that " gold oxygen semiconductor field effect electric crystal " (MOSFET, a Metal Oxide Semiconductor Field EffectTransistor) and who is used for doing data access is used for doing data storage.For these storage elements, its result of characteristic dimension (feature size) who continues the reduction element can strict limit the data storage ability that is increased.Between decades, make the program technic of SRAM and DRAM and transfer to 0.18 micron 256M memory body in the past, and the size of the minimizing mnemon that continues also increases memory capacity simultaneously from 0.8 micron 4M memory body.Because of these DRAM elements need less substrate surface space than other similar elements, so a large amount of use of quilt that the DRAM element continues.
The operating speed of semiconductor element constantly increases at present, so the operating speed of memory body chip also and then increases.This makes to the increase in demand of memory cell test, and the development of tester faster will cause the more expensive method of testing of memory cell.Improve the production capacity of memory cell, the memory body chip must be done test when still belonging to wafer (wafer) a part of.The memory body chip is to test at the chip that lost efficacy, the memory body chip in by this test then the performance according to element screened.
United States Patent (USP) 6,237,115 (Ting et al.) but the design of a test pole high speed memory body unit is provided.This invention provides a test circuit that is formed in the high speed memory body chip, can be to the time still for wafer a part of or the memory body chip after having encapsulated carry out performance test.Also can use a low speed tester to reduce the impact of test operation on cost according to the method.This test circuit can produce a sequential and postpone (timing delay), can be as the reference of test.
Again, United States Patent (USP) 5, it is a kind of by allowing the part display to use " static authenticate technology " (Static Evaluation technique) to be used for testing the System and method for of self-clocking memory body display (self-timed memory arrays) that 896,399 (Lattimore et al.) provide.The influence that the sequential of this display area and display can not be tested, thus can be under normal condition continuous action, first partly become " virtual static state " (pseudo-static) and its function and data may circulate (clockcycle) at clock pulse.
In addition, United States Patent (USP) 6,230,292 (Duesman et al.) provide one at test data (test information) turnover memory cell with in the middle of reading and writing, the method that memory cell is tested.The operating parameter of element (operational parameter) be carried out that control is adjusted so that on the bit line viewed voltage difference (voltage differential) produce uneven or it changed.Be stored in the detecting information that is intended in the memory cell by detecting mistakenly, the defective of memory cell has been pointed out in the reaction of sensing amplifier (sense amplifier).
The present invention can be when carrying out the chip probe test, inefficacy bit in the DRAM unit is detected, can save the test duration and accurately detect the inefficacy bit with this mode, and then means that are used for repairing memory cell when carrying out the chip probe test are provided.Column selection (column select; CSL) with character line (wordline; WL) pulse wave is controlled by automatic timing method, and allows to imitate the DRAM operation under various different conditions.
Again, United States Patent (USP) 6,237,112 (Ting et al.) exposure one is used for testing the test circuit of high speed memory body chip performance on a low speed tester.This test circuit produces a sequential to postpone, and this sequential postpones to be the test reference benchmark of memory body chip.
United States Patent (USP) 5,896, a self-clocking memory body array test method is described in 399 (US Patent 5,896,399).Functional operation and data can be virtual static state partly in clock pulse round-robin first.
United States Patent (USP) 6,230, the method for testing in memory cell limit (cell margin) in 292 (US Patent 6,230,292) the instruction memory cell.Main voltage and sequential can be used the performance of handling test cell.
Summary of the invention
Fundamental purpose of the present invention is the chip in the DRAM unit when carrying out probe test, and the method for a detecting inefficacy bit is provided.
Another object of the present invention is saved the test duration when the DRAM unit is provided in test method.
Further aim of the present invention provides inefficacy DRAM unit can be repaired in the DRAM unit when chip probe is tested method.
According to purpose of the present invention, provide one to use the low speed tester to test the method for DRAM unit.One variable self-clocking structure (adjustable self-time scheme) ties up to when using low speed tester test DRAM element provides one to write formula mistake reparation (write-recovery) function.CSL is subjected to self-clocking to control and imitate the running of DRAM under different running situations with the WL pulse wave.Variable self-clocking structure of the present invention can be used for covering according to the field of DRAM unit demand and writes formula reparation (screen write recovery; Twr), the low speed tester execution that can be used for covering.
Description of drawings
Fig. 1 is the common sensing amplifier with a cells D RAM bit line;
Fig. 2 a～Fig. 2 f is the operation signal general schematic view of a common DRAM bit element line sensing amplifier;
Fig. 3 is the comprehensive synoptic diagram of pulse wave that the present invention paid close attention to;
Fig. 4 a and Fig. 4 b are the WL and the CSL pulse wave synoptic diagram of the self-clocking control that the present invention influenced;
Fig. 5 is for implementing to carry out memory body chip of the present invention and the self-clocking WL of tester interface and the general survey synoptic diagram of CSL pulse wave.
Fig. 6 a and Fig. 6 b are the operational flowchart that the invention process is carried out.
Embodiment
In test pattern, CSL can effectively be controlled by many working storages and WL starts width (on-width) pulse wave.In this mode can in as 4 or 5 how second (nanosecond) adjust CSL startup width pulse wave the time in.Same reason, be that the sequential with the CMD rise time is relevant and can be adjusted the fall time of WL.These adjustment are applied to the sensing amplifier of general DRAM unit, and at first emphasize in Fig. 1.
Emphasize following elements among Fig. 1, the DRAM bit line sense amplifier that these a little elements all are the formation standards drives the complete row that are of a DRAM unit:
-10, one first data lead input DLB
-12, one second data lead input DL
-14, one column selection input CSL
-16, one character line input WL
-18, one first bit line output BLB
-19, one second bit line is exported BL, is connected to the source/drain of electric crystal 27
-20 and 22, the CSL electric crystal
-24 and 26, be respectively applied for the phase inverter (inverter) of DLB and DL input data lead
-27, character line is selected electric crystal
-28, one DRAM unit
-30, the ground connection of DRAM unit connects
Running (write operation) the correlation timing figure that writes of Fig. 1 sensing amplifier is illustrated in Fig. 2 a to Fig. 2 f, and is as follows:
The DL signal 32 of-Fig. 2 a pictorial image 1 end points 12
The DLB signal 34 of-Fig. 2 b pictorial image 1 end points 10
The WL signal 36 of-Fig. 2 c pictorial image 1 end points 16
The CSL signal 38 of-Fig. 2 d pictorial image 1 end points 14
BL sequential Figure 40 of-Fig. 2 e pictorial image 1 end points 19
BLB sequential Figure 42 of-Fig. 2 f pictorial image 1 end points 18
The running of sensing amplifier shown in Figure 1 can be complied with following narration: a rising CSL pulse wave inputs to electric crystal 20 and 22 from end points 14, makes electric crystal be in conducting state (conductive state).Place the data DL of input endpoint 12 to input to phase inverter 26 and convert the BLB signal to and offer end points 18.Place the data DLB of input endpoint 10 to input to phase inverter 24 and convert the BLB signal to and offer unit 28.Pulse wave shown in Fig. 2 e provides to the unit 28, forms the charging curve of the cell voltage shown in Fig. 2 e.Pulse wave DL and DLB drive BL and BLB respectively.The startup of the character line curve shown in Fig. 2 c running is by the gate voltage that promotes electric crystal 27, with access unit 28 and make unit 26 chargings.Shown in Fig. 2 c, the present invention paid close attention to and illustrated be before the WL pulse wave available effective time can close, to such an extent as to the charging that unit 28 can be suitable.
Therefore must be pointed out the enforceability that the CSL instruction provides data to write shown in Fig. 2 d, write-in program running is carried out to be followed automatic first charging procedure running (auto-precharge operation) to carry out.Just the substrate conductor loop is around the pulse wave curve shown in Fig. 2 a and Fig. 2 b, and BL used by expression substrate lead and BLB is set at a 1/2Vcc magnitude of voltage earlier, makes these leads in response to following a succession of little signal sensing operation procedure at this in order to prepare.
Further, the CSL pulse wave frequency shown in Fig. 2 d is controlled by the clock pulse frequency of tester.The test of the wafer stage of DRAM element is to use the relatively slow test speed of 50MHz, and the CSL pulse wave continues to carry out running about 20 how second (nanoseconds).To be design be executed in 200 or the execution speed of 250MHz with running to this tested chip.Therefore the method for DRAM element test must be provided, and this method can provide the otherness of adjusting on tester and the tested chip operation frequency speed.
The combination that is to highlight sequential chart shown in Figure 3 that the present invention is further paid attention to.In this icon is the preceding timing curve narrated emphasized, does not therefore need to be described in further detail once more in this.Sequential chart curve shown in Figure 3 is that mainly these curves start the relative timing framework of carrying out.From the present invention will in response on the problem that satisfies above-mentioned concern further limit be Fig. 4 a and the illustrated curve of Fig. 4 b, point out thus the present invention satisfy CSL pulse wave survival conducting round-robin sequential (the lasting width of CSL pulse wave), shown in Fig. 4 a signal 38, with the closing timing of WL pulse wave, shown in Fig. 4 b signal 36.This both direction of the present invention is in conjunction with the target that necessity of the present invention is provided, and just provides one can adjust the self-clocking frame mode and write the formula reparation and the running of DRAM element is executed in the speed that quite is higher than test DRAM element test device to reach.
As emphasizing in Fig. 4 a and with reference to United States Patent (USP) 6,237,115 B1 (Ting et al.) can satisfy first direction of the present invention.Details with reference to United States Patent (USP) is provided by the sequential time delay enforcement that provides needn't repeat to describe in detail at this.United States Patent (USP) 6,237,115 provide one about the method for pulse bandwidth generator (pulse width generator) and emphasize as follows:
----one embeds the test circuit of memory body chip, and this test circuit is the sequential circuit (timing circuits) that is connected in the memory body chip;
----a tester utilizes probe to survey the memory body chip form and is connected to the memory body chip;
----tester provides the sequential circuit of a tester clock pulse pulse wave to the memory body chip; This tester also provides other signal to the memory body chip, and as I/O signal, position addressing signal and controlling signal, these a little signals of the latter and the present invention there is no substantial connection.
----the test circuit circuit uses a synchronous pulse wave (sync pulse), and this develops in the memory body chip internal and makes with the tester clock pulse reaches synchronizing function;
----the forward position of synchronization pulse directly passes through to the output of test circuit, and the back edge of synchronization pulse then postpones
----one starts test circuit
----the back edge of the synchronization pulse of delay is the test pole that is connected in test circuit
----by having inputed to test circuit in conjunction with the input synchronization pulse and this pulse wave that postpone, this test circuit generation one comprises the pulse wave of sequential time delay window ranges (timing delay window); Test memory body chip can be under the state of generation sequential time delay window ranges; Can adjust the back edge of the synchronization pulse that capacitor that clock pulse circulation that the sequential time delay window ranges is lower than tester can connect test circuit by fusible (fuse) mode of connection postpones with the sequential time delay window ranges of adjusting test chip and can be used for the forward position that test circuit is exported next test loop.
United States Patent (USP) 6,237,115 B1 at first assemble the memory body chip in the time of can further extending in punch die encapsulation (die package), after this can test completed packaged chip.The delay on the back edge of synchronization pulse is to use a RC delay circuit network to reach, and this circuit network is the some of sequential circuit in the test circuit, the size that may command postpones by selecting the RC different capacitance of delay circuit network.
In brief, United States Patent (USP) 6,237,115 provide a pulse bandwidth generator with one produce pulse wave use make pulse wave variable-length more with adjustment.This is for how need just adjusting the length of CSL pulse wave by the invention creation of emphasizing the tool urgency as preceding Fig. 4 a to a certain extent.
As second portion of the present invention, but the shut-in time of WL is Be Controlled and adjustment.This emphasizes in relevant United States Patent (USP) 6,058,069 (Ting et al.) and provides one to close the method that postpones generator about pulse wave that this can provide a holding circuit to guarantee that the DRAM signal is in writing circulation.Before these methods are given security and finished before the bit line restarts, in DRAM row circulations (column cycle), write executive routine at last and can't be closed termination, therefore avoid data when access next time, to be destroyed.United States Patent (USP) 6,058,069 illustratedly emphasizes that total knot is as follows:
----delegation's enabled instruction (row activation command) is received, and produces delegation and start flag (row-activation flag) when this journey enabled instruction receives;
----row circulation (column cycle) initialization;
----in when running row circulation, produce a numeral " n " write pulse wave WRPLS;
----this is provided " n " the WRPLS pulse wave is used as one and inputs to TWR timing reference element (TWR timingreference component);
----this TWR reference element produces " n " the WRPLS pulse wave;
----this " n " the TWR_PRO pulse wave provides and is applied to a capacitor; " n " the decline ripple of TWR_PRO pulse wave charge to capacitor along (falling edges); this capacitor is the some of TWR reference element; when " n " and the TWR_PRO pulse wave after the edge discharge from capacitor; so never allow a charge charging in capacitor, go amplification and in " n " the back-page phenomenon of TWR_PRO pulse wave is provided on the electric capacity; at this moment the decline ripple of last pulse wave along to the capacitor charging owing on the capacitor of TWR reference element, charge, so the therefore decline of TWR_PRO pulse wave.
It is in United States Patent (USP) 6 that the above-mentioned illustrated characteristic of emphasizing is used; 058; in 069; and at a row circulation time; this is provided " n " the WRPLS pulse wave gives a sequential reference element with initial " n " write operation procedure; be reaction " n " the WRPLS pulse wave sets up " n " the TWR_PRO pulse wave; receive and temporary pre-charge instruction; " n " decline of TWR_PRO pulse wave descended in and produce pre-charge instruction after; the line pre-charge of one bit line unit also finishes; increase memory internal body member TWR sequential by reducing inner member TRP sequential, therefore to protect last data to write.The present invention is applicable to each " n " application on the TWR_PRO pulse wave, and this pulse wave has the pulse bandwidth that exceeds inner TWR sequential specification, this inner TWR sequential specification is for finishing the minimum time of the data of writing to whole cell capacitance fully.When the pre-charge instruction is the pulse bandwidth variation purpose of TWR_PRO pulse wave, before all the bit line recovers conducting again, the pre-charge instruction can be received with temporary, and these are all caused and mutual tracking influence with the transformation period that the data that writes enters whole capacitors by the variation in timing reference element program.
In brief, United States Patent (USP) 6,058,069 provides a pulse wave to close generator (pulse turn-off generator) uses a signal, and the WL pulse wave shown in Fig. 4 b is reached the drop-out value that prevents in the time delay of a controlled range.
How to Figure 5 shows that in conjunction with two methods of previous citation with reference to United States Patent (USP) 6,237,115 and the icon of United States Patent (USP) 6,058,069.As follows:
----44 1 testers are used to test memory cell; Tester offers the memory body chip and highlights the test signal of emphasizing, as controlling signal (47), position signal (49), I/O signal (51), CSL (41) and WL (43) signal, with time pulse signal (45);
----46, memory body chip, the memory body chip that tester 44 is tested;
----48 and 52, the theme of emphasizing illustrated in the pulse bandwidth generator, Fig. 4 a;
----50, pulse wave open to postpone generator, the theme of emphasizing illustrated in Fig. 4 b;
----54, the WL signal has been had late release (delayed turn-off) compared to provided WL signal 43 different to the signal of memory body chip 46 by tester;
----56, CSL signal tool is controlled ON cycle (controlled-on period) compared to providing CSL signal 41 different to the signal of memory body chip 46 by tester 44.
When final method is consulted and used described in the invention carrying out, use follow procedure can reach of the pulse bandwidth adjustment of the sequential time delay of generation WL signal in conjunction with the CSL signal.Be described below and flowchart illustrations in Fig. 6 a and Fig. 6 b:
● a test circuit, Fig. 6 a, step 60, be to be formed on the memory body chip, the conducting circulation (first signal of the on-period) that test circuit has been connected to the sequential circuit of memory body chip and provides a pulse bandwidth generator to be controlled first signal;
● a pulse wave is closed generator, and Fig. 6 a, step 61 are to be formed on the memory body chip with test circuit, and this closes generator can postpone closing of second signal;
● it is the sequential circuit that is connected to the memory body chip that pulse bandwidth produces circuit, in step 62, Fig. 6 a;
● the probe test wafer, Fig. 6 a, step 63, by connecting tester to the memory body chip, this connection is included in the crystal column surface or on the surface;
● providing of clock pulse is to offer the memory body chip by the tester clock pulse, and therefore Fig. 6 a, step 64 can use test circuit;
● connect the CSL signal, Fig. 6 a, step 65, when first signal from tester to the pulse bandwidth generator, produce a CSL signal that changes the signal width
● the CSL pulse wave is transmitted from pulse bandwidth generator input end pass through to output terminal step 66, Fig. 6 b;
● in the pulse bandwidth generator, postpone the back edge of CSL pulse wave, step 67, Fig. 6 b;
● start the pulse bandwidth generator, step 68, Fig. 6 b;
● the edge is to the output stage of pulse bandwidth generator, step 69, Fig. 6 b behind the CSL pulse generator of connection delay;
● in conjunction with the back edge of the CSL pulse wave of CSL pulse wave and delay, step 70, Fig. 6 b;
● connect a WL signal, Fig. 6 b, step 65 are used as second signal and are closed the delay generator from tester to pulse wave, step 71, Fig. 6 b, but produce the WL signal that a Be Controlled is closed;
● provide " n " WRPLS pulse wave to pulse wave closes the timing reference means that postpone generator, step 72, Fig. 6 b are to produce in the row circulation time " n " write operation procedure;
● respond " n " the WRPLS pulse wave and produce " n " the TWR_PRO pulse wave, step 73, Fig. 6 b;
● receive with temporary by closing the pre-charge instruction that postpones the generator generation;
● only exist " n " after the last signal of TWR_PRO pulse wave descended, finish the pre-charge of bit line, step 75, Fig. 6 b; And
● change the WL signal that the CSL signal of signal width is closed in conjunction with control, recovering to write circulation for producing a memory body chip on the effect test, Fig. 6 b, step 78, memory body chip to its recovery writes the round-robin sequential.
But the above only is a preferred embodiment of the present invention, is not to be used for limiting scope of the invention process.Be that the equalization that all the present patent application claims are done changes and modification, be all the contained lid of claim of the present invention.
Symbol description
60,61,62,63,64,65,66,67 steps
68,69,70,71,72,73,74,75,78 steps
10,12,14,16,18 end points
19 leads
20,22,27 electric crystals
24,26 phase inverters
28 DRAM unit
30 ground connection links
32,34,35,36,38,40,42, signal waveform
41 CSL signals
43 WL signals
44 testers
45 time pulse signals
46 memory body chips
47 controlling signal
48,52 pulse bandwidth generators
49 position signals
50 pulse waves are opened and are postponed generator
51 I/O signals
54,56 signals
Claims (18)
1. one kind is used a low speed tester to carry out the method for high speed memory body test, may further comprise the steps:
Form on the memory body chip of a test circuit in a wafer, this test circuit produces the circulate column selection signal of (controlled time-on period) of a tool control timing conducting by a synchronous pulse wave of revising on the memory body chip to carry out a pulse bandwidth generator function (pulse-width generatorfunction);
Form a pulse wave and close on the memory body chip of generator in this wafer, this pulse wave is closed generator and is revised the writing line signal that delay is closed in tool control;
By connecting a clock pulse signal and a synchronous signal from this tester to this test circuit to start this test circuit;
This pulse wave of this test circuit is closed generator and is connected a column selection signal from this tester to this memory body chip, forms a tool control timing conducting round-robin column selection signal;
Connect a writing line this pulse wave to the memory body chip from this tester and close generator, form the modification writing line signal that delay is closed in tool control;
This modification writing line signal that delay is closed in this column selection signal of tool control timing conducting round-robin and tool control combines, and writes circulation with the recovery of setting up a memory body chip; And
Test this memory body chip and write circulation to this recovery.
2. use one low speed tester as claimed in claim 1 is to carry out the method for high speed memory body test, and it is characterized in that: described method of testing is to carry out at the wafer probe test period.
3. use one low speed tester as claimed in claim 1 is to carry out the method for high speed memory body test, and it is characterized in that: described method of testing is to use the test period of a low speed tester to carry out at a memory chip mat that has encapsulated.
4. use one low speed tester as claimed in claim 1 is characterized in that to carry out the method for high speed memory body test: described recovery write cycle is the clock pulse cycle that is less than this tester.
5. use one low speed tester as claimed in claim 1 is to carry out the method for high speed memory body test, and it is characterized in that: described pulse bandwidth generator comprises following function:
Receive for the moment affectionately ripple from this tester;
Receive a synchronous pulse wave from this memory body chip;
Synchronization pulse on this memory body chip is sent to the output terminal of this pulse bandwidth generator from input end; And the back edge (trailing edge) of this synchronizing pulse of delay.
6. use one low speed tester as claimed in claim 5 is to carry out the method for high speed memory body test, it is characterized in that: the back edge of described this synchronizing pulse of delay " function be in a sequential circuit (timer circuit), to reach, its can be apace by a forward position and postpone this edge, back.
7. use one low speed tester as claimed in claim 5 is to carry out the method for high speed memory body test, it is characterized in that: the function on described " the back edge that postpones this synchronizing pulse " is to reach in a RC delay network of a sequential circuit, and this delay is adjusted by the capacitor of selecting a different capabilities.
8. use one low speed tester as claimed in claim 1 is to carry out the method for high speed memory body test, and it is characterized in that: described pulse wave is closed generator and comprised:
Receive delegation (row) enabled instruction;
After receiving capable enabled instruction, set up delegation and start flag (flag);
Initialization one row circulations (initiating a column cycle);
In the middle of the row cycling, write several " n " the WRPLS pulse wave;
Should " n " the WRPLS pulse wave is used as an input and is applied to a TWR reference element;
Produce by this TWR reference element " n " individual TWR_PRO pulse wave;
To be somebody's turn to do " n " individual TWR_PRO pulse wave is applied to a capacitor of the part of this TWR reference element, should " n " the decline ripple of TWR_PRO pulse wave is along charging to capacitor, should " n " the back edge of TWR_PRO pulse wave discharges capacitor, one should " n " individual TWR_PRO pulse wave descends ripple at last along being applied to capacitor and to its charging;
Inner generation one pre-charge instruction; And
At this " n " after the last pulse wave of individual TWR_PRO descended, finish the pre-charge of a bit line at once.
9. use one low speed tester as claimed in claim 8 is to carry out the method for high speed memory body test, it is characterized in that: described each should " n " individual TWR_PRO pulse wave has an adjustable pulse bandwidth, covers the inefficacy bit of stipulating in the TWR specification so that reach.
10. one kind is used a low speed tester to carry out the test circuit of high speed memory body test, comprising:
Form on the memory body chip of a test circuit in a wafer, this test circuit produces the circulate column selection signal of (controlled time-on period) of a tool control timing conducting by a synchronous pulse wave of revising on the memory body chip to carry out a pulse bandwidth generator function (pulse-width generatorfunction);
Form a pulse wave and close on the memory body chip of generator in this wafer, this pulse wave is closed generator and is revised the writing line signal that delay is closed in tool control;
By connecting a clock pulse signal and a synchronous signal from this tester to this test circuit to start this test circuit;
This pulse wave of this test circuit is closed generator and is connected a column selection signal from this tester to this memory body chip, forms a tool control timing conducting round-robin column selection signal;
Connect a writing line this pulse wave to the memory body chip from this tester and close generator, form the modification writing line signal that delay is closed in tool control;
This modification writing line signal that delay is closed in this column selection signal of tool control timing conducting round-robin and tool control combines, and writes circulation with the recovery of setting up a memory body chip; And
Test this memory body chip and write circulation to this recovery.
11. use one low speed tester as claimed in claim 10 is to carry out the test circuit of high speed memory body test, it is characterized in that: describedly survey this wafer with probe and replaced, to test a memory body chip that has encapsulated by this memory body chip being connected to a memory body module (memory module).
12. use one low speed tester as claimed in claim 10 is characterized in that to carry out the test circuit of high speed memory body test: it is to be less than this tester clock pulse circulation that described recovery writes circulation.
13. use one low speed tester as claimed in claim 10 is to carry out the test circuit of high speed memory body test, it is characterized in that: described pulse bandwidth generator comprises:
Receive for the moment the affectionately means of ripple from this tester;
Receive the means of a synchronous pulse wave from this memory body chip;
Synchronization pulse on this memory body chip is sent to the means of the output terminal of this pulse bandwidth generator from input end; And
The means that postpone edge behind this synchronizing pulse.
14. use one low speed tester as claimed in claim 13 is to carry out the test circuit of high speed memory body test, it is characterized in that: the means of described " postpone this synchronizing pulse after along " are a sequential circuit (timercircuit), its can be apace by a forward position and postpone this edge, back.
15. use one low speed tester as claimed in claim 13 is to carry out the test circuit of high speed memory body test, it is characterized in that: the means on described " the back edge that postpones this synchronizing pulse " are to reach in a RC delay network of a sequential circuit, and this delay is adjusted by the capacitor of selecting a different capabilities.
16. use one low speed tester as claimed in claim 10 is to carry out the test circuit of high speed memory body test, it is characterized in that: described pulse wave is closed generator and is comprised:
Be used for receiving the means of delegation (row) enabled instruction;
Be used for after receiving capable enabled instruction, setting up the means that delegation starts flag (flag);
Be used for the means of initialization one row circulations (initiating a column cycle);
Be used in the middle of the row cycling, writing several " n " means of WRPLS pulse wave;
Be used for and will be somebody's turn to do " n " the WRPLS pulse wave is used as an input and is applied to the means of a TWR reference element;
Be used for producing by this TWR reference element " n " means of individual TWR_PRO pulse wave;
Be used for and will be somebody's turn to do " n " individual TWR_PRO pulse wave is applied to a capacitor of the part of this TWR reference element, should " n " the decline ripple of TWR_PRO pulse wave is along charging to capacitor, should " n " the back edge of TWR_PRO pulse wave discharges capacitor, one should " n " individual TWR_PRO pulse wave descends ripple at last along being applied to capacitor and to the means of its charging;
Be used for the inner means that produce pre-charge instruction; And
Be used at this " n " after the last pulse wave of individual TWR_PRO descended, finish the means of the pre-charge of a bit line at once.
17. use one low speed tester as claimed in claim 16 is to carry out the test circuit of high speed memory body test, it is characterized in that: described each should " n " individual TWR_PRO pulse wave has an adjustable pulse bandwidth, covers the inefficacy bit of stipulating in the TWR specification so that reach.
18. use one low speed tester as claimed in claim 16 is characterized in that: described to carry out the test circuit of high speed memory body test " n " pulse bandwidth of individual TWR_PRO pulse wave changes is that handling procedure by this timing reference element changes the required time that enters whole capacitors of mutual tracking influence with the data that writes and caused.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031429807A CN100440381C (en) | 2003-06-13 | 2003-06-13 | Automatic variable timing structure for recovering writing using low speed tester |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031429807A CN100440381C (en) | 2003-06-13 | 2003-06-13 | Automatic variable timing structure for recovering writing using low speed tester |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1567482A true CN1567482A (en) | 2005-01-19 |
| CN100440381C CN100440381C (en) | 2008-12-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031429807A Expired - Fee Related CN100440381C (en) | 2003-06-13 | 2003-06-13 | Automatic variable timing structure for recovering writing using low speed tester |
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| CN (1) | CN100440381C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101137965B (en) * | 2005-03-11 | 2010-05-19 | 罗伯特·博世有限公司 | System and method for testing a control apparatus assembly |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19819570C2 (en) * | 1998-04-30 | 2000-06-15 | Siemens Ag | Arrangement for testing multiple memory chips on a wafer |
| US6237115B1 (en) * | 1999-03-08 | 2001-05-22 | Etron Technology, Inc. | Design for testability in very high speed memory |
-
2003
- 2003-06-13 CN CNB031429807A patent/CN100440381C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101137965B (en) * | 2005-03-11 | 2010-05-19 | 罗伯特·博世有限公司 | System and method for testing a control apparatus assembly |
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| Publication number | Publication date |
|---|---|
| CN100440381C (en) | 2008-12-03 |
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