CN1567479A - High-speed nonvolatile memory device - Google Patents
High-speed nonvolatile memory device Download PDFInfo
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- CN1567479A CN1567479A CN 03137421 CN03137421A CN1567479A CN 1567479 A CN1567479 A CN 1567479A CN 03137421 CN03137421 CN 03137421 CN 03137421 A CN03137421 A CN 03137421A CN 1567479 A CN1567479 A CN 1567479A
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- voltage
- structure cell
- induction amplifier
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Abstract
This inventing provides a kind of high-speed volatile memory apparatus. Especially it is a kind of double reference crystal cell inductive structure of non-volatile memory. The high voltage reference crystal cell and the low voltage reference crystal cell are respectively coupled with two induction amplifiers to provide different reference voltage to compare with the voltage of memory crystal cell. The output of the two induction amplifiers connects to the second phase induction amplifier, so to judge the state of this memory. The double reference crystal cell inductive structure enlarges the inductive window, improves the performance under the low voltage application. The double reference crystal cell inductive structure can be executed by the voltage type, current type and grounding type.
Description
Technical field
The invention relates to a kind of non-volatility memorizer device, and particularly respond to framework with reference to structure cell relevant for the two of a kind of non-volatility memorizer.
Background technology
But the non-volatility memorizer device can be under powering-off state the storage arrangement of storage data still.These non-volatility memorizer devices are particularly useful in the portable device, with store operation system and user's data.Recently, because its adaptability and use dirigibility, and obtain hig diligence and research.For the non-sanction property storer of waving, memory speed is very important.
The electricity formula programmble read only memory PROM (EPROM) of erasing is a kind of non-volatile storage integrated circuit of quick growth, because of it has electrically sequencing and the ability that reads memory crystal cell in wafer.EPROM often uses memory crystal cell, and it has the electrical isolation grid that is called the suspension joint grid.The frequent oxide of these suspension joint grids institute around, and formed by polycrystal silicon thing (such as polysilicon) layer.Information system is stored in memory crystal cell or the device with the form of electrical charges on the suspension joint grid.Electric charge is to be sent to the suspension joint grid by variety of way, injects (avalanche injection), passage such as collapse and injects (channel injection), tunnel logical (tunneling) etc., depends on cell configuration.These structure cells generally are to erase by array being exposed under the ultraviolet ray (UV).
EPROM is for can electrically erasing and electrically sequencing.Electric charge is logical by the electronics tunnel, is positioned on the suspension joint grid through being formed at the thin gate oxide area on the base stage, or from removing from the suspension joint grid.In other example, electric charge is to remove via last control electrode.
Recently, invented out a kind of new device of electrically erasing, and this device often is called " quickflashing " EPROM or " quickflashing " EEPROM.In these storeies, memory crystal cell is for can electrically erasing, and these structure cells itself, each structure cell includes only a device.Equally, can finish the memory crystal cell in erase whole array or whole zone.
Finish erase with program verification in, various induction amplifiers are to be used for known technology, with the state of sensing memory structure cell.Apply the character line of grid voltage for utilizing induction to finish checking, utilizing, can produce electric current by memory crystal cell to be verified to memory crystal cell to be verified.This electric current of induction amplifier comparison with by one with reference to electric current that structure cell produced.Generally speaking, the UV-that EPROM the uses delegation structure cell of erasing, it structurally is same as memory crystal cell, and it is as above-mentioned reference structure cell.Whether induction amplifier determines memory crystal cell to be verified than the reference structure cell of weighted draws and more manys or less electric current with certain relational expression.Thus, this induction amplifier is verified the sequencing state of this memory crystal cell.Following equation defines the potential change of single structure cell frame of reference:
Δ V
Single=V
Ref (H)-V
CellOr Δ V
Single=V
Cell-V
Ref (L)(1)
The reading speed of non-volatility memorizer is relevant for the induction framework of induction amplifier.The induction amplifier of known technology utilizes single structure cell frame of reference, thus itself and be not suitable for low-voltage because the narrow induction window of unsettled reference voltage and single structure cell frame of reference.Even the used setting of known technology is expensive and incorrect with reference to the unnecessary structure cell method and the adjustment mode of structure cell.Thereby, the non-volatility memorizer that need have the high speed reading speed.
Summary of the invention
According to one of purpose of the present invention, provide a kind of non-volatility memorizer of high reading speed.
According to another object of the present invention, the induction window (window) of this non-volatility memorizer is increase.
According to another object of the present invention, can set reference voltage easily.
According to another object of the present invention, the noise immunity of this non-volatility memorizer system increases.
The invention provides a kind of twin crystal born of the same parents frame of reference of non-volatility memorizer.Use two to amplify so that induction to be provided simultaneously with reference to structure cell and two induction amplifiers.With reference to one of structure cell is high voltage (HVT) structure cell, and another is low-voltage (LVT) structure cell.The HVT structure cell can be ground connection, suspension joint ground connection or reference current source, and the LVT structure cell can be quickflashing structure cell and reference current source.HVT structure cell and LVT structure cell are coupled to induction amplifier respectively, and it all more is connected to common induction amplifier to determine the state of this memory crystal cell.Two potential change with reference to structure cell induction framework are shown in following equation:
ΔV
dual＝(V
ref(H)-V
cell)+(V
cell-V
ref(L))＝2ΔV
single (2)
Equation (2) shows that two voltage varieties with reference to structure cell induction framework are the single twice of responding to the voltage variety of framework with reference to structure cell.Utilization provides big input signal difference as induction, Δ V
DualIncrease strengthened the induction window.Δ V
DualIncrease also increase the reading speed of non-volatility memorizer widely.Even because the induction window strengthens, the correctness of low voltage application is for improving greatly.In low voltage application, the induction window is very narrow, thereby its reading speed and correctness are restricted.Twoly also do not have an inactive area with reference to structure cell induction framework, it has improved performance greatly.
Because Δ V
DualIncrease, reference voltage system sets easily, thereby need very correctly not determine reference voltage in the zone line between high voltage and low-voltage.Because use two with reference to structure cell, the zone that decision belongs to high voltage or low-voltage can obviously go out respectively, thereby if necessary, and these two can be adopted different value with reference to structure cell.The initial fixation reference voltage of manufacturing storer can reduce cost to respond in the framework with reference to structure cell this pair as reference voltage.
Respond to framework with reference to structure cell for of the present invention pair and can be applied to any non-volatility memorizer, such as EEPROM, EPROM, MASK ROM, FLASH ROM, or in the composite set of volatile storage and non-volatility memorizer.
Description of drawings
Fig. 1 is according to the two icons with reference to structure cell induction framework of the current type of preferred embodiment of the present invention.
Fig. 2 is the two voltage patterns of responding to the high voltage structure cell of framework with reference to structure cell according to preferred embodiment of the present invention.
Fig. 3 is the two voltage patterns of responding to the low-voltage structure cell of framework with reference to structure cell according to preferred embodiment of the present invention.
Fig. 4 is according to the two icons with reference to structure cell induction framework of the voltage-type of preferred embodiment of the present invention.
Fig. 5 is according to the two icons with reference to structure cell induction framework of the voltage-type of another preferred embodiment of the present invention.
Fig. 6 is according to the two circuit diagrams with reference to structure cell induction framework of the voltage-type of preferred embodiment of the present invention.
Fig. 7 is according to the two circuit diagrams with reference to structure cell induction framework of the voltage-type of another preferred embodiment of the present invention.
102,106,110: current source
104,108,112: electric capacity
114,116,118: induction amplifier
402,406,410: resistance
404,408,412: current source
414,416,418: induction amplifier
512,518: resistance
514,519: current source
522,524,526: induction amplifier
610,620: transistor
710,720: transistor
Embodiment
Fig. 1 shows the two with reference to structure cell induction framework of preferred embodiment of the present invention.Reference symbol 102,106 and 110 is represented the current source of memory crystal cell (CELL among Fig. 1) respectively, and high voltage (HVT) is with reference to the current source of structure cell and low-voltage (LVT) current source with reference to structure cell.Current source 102,106 and 110 is connected to electric capacity 104,108 and 112 respectively.Electric capacity 104,108 and 112 is in order to holding current source 102,106 and 110 electric charges that transmitted, till it arrives required current potential.The current source 102 of memory crystal cell is sent signal CMI to the positive input terminal of induction amplifier 114 and the negative input end of induction amplifier 116 via common node.The signal TREF HVT that is sent by the high reference voltage structure cell delivers to the negative input end of induction amplifier 114.The signal TREF LVT that is sent by the low reference voltage structure cell delivers to the positive input terminal of induction amplifier 116.The signal TREF HVT that induction amplifier 114 comparison signal CMI and high reference voltage structure cell are sent; And the signal TREF LVT that induction amplifier 116 comparison signal CMI and low reference voltage structure cell are sent.The output signal Δ SA1 of induction amplifier 114 more is connected to induction amplifier 118, and the output signal Δ SA2 of induction amplifier 116 more is connected to the state of induction amplifier 118 with the decision memory crystal cell.
When Fig. 2 and Fig. 3 are presented at the operating period of non-volatility memorizer, the induction amplifier 114 of Fig. 1 and 116 voltage pattern.Induction amplifier 114 comparator input signal CMI and TREFHVT, and export Δ SA1 according to following equation:
ΔSA1＝Av*(CMI-TREF?HVT) (3)
Wherein Av represents the bias voltage adjusted according to induction amplifier 114, and Δ SA1 represents the voltage variety of induction amplifier 114.Similarly, induction amplifier 116 comparator input signal CMI and TREF LVT, and export Δ SA2 according to following equation:
ΔSA2＝Av*(TREF?LVT-CMI) (4)
Wherein Av represents the bias voltage adjusted according to induction amplifier 116, and Δ SA2 represents the voltage variety of induction amplifier 116.Signal delta SA1 and Δ SA2 input to induction amplifier 118 and compare, to determine whether voltage is in high voltage region or low-voltage area.As shown in Figure 2, when reading HVT with reference to structure cell, the branch voltage of top goes out the small electric pressure reduction of Δ SA1, and the branch voltage of below goes out the remarkable voltage difference of Δ SA2, thereby voltage is drop-down with sensed amplifier 118, and the data decision is 1.Similarly, as shown in Figure 3, the branch voltage of top goes out the small electric pressure reduction of Δ SA2, and the branch voltage of below goes out the remarkable voltage difference of Δ SA1, thereby voltage will draw on the sensed amplifier 118, and the data decision is 0.Respond in the framework with reference to structure cell at of the present invention pair, so determine the state of memory crystal cell.
Below enumerate an embodiment, with describe among above-mentioned Fig. 2 and Fig. 3 shown it, the duty that the operating period of non-volatility memorizer is possible.But present embodiment is not in order to limit scope of the present invention.When the operating voltage (VDD) of memory crystal cell is 3V, in one embodiment, in equation (3), if the bias voltage adjusted Av=0.2V according to induction amplifier 114, comparator input signal CMI=0.1V and TREF HVT=0.05V are then according to output Δ SA1=Av* (CMI-TREF the HVT)=0.1V of equation (3).Similarly, in another embodiment, in equation (4), as if the bias voltage adjusted Av=0.2V according to induction amplifier 116, comparator input signal CMI=0.1V and TREF LVT=0.2V are then according to output Δ SA2=Av* (TREF the LVT-CMI)=0.2V of equation (4).
The reading speed of non-volatility memorizer is directly relevant for the Δ V of induction amplifier.Though the output of induction amplifier 118 can be adjusted by bias voltage Av in equation (3) and (4), original induction window can't only be adjusted bias voltage Av and just obtain expansion, thereby the storage arrangement of known technology is under the low voltage application situation, its limited by practical.If bias voltage Av value is too big, noise problem can take place, and responds in the framework with reference to structure cell single, and performance will descend.Respond to framework with reference to structure cell for of the present invention pair and can not need to increase the induction window under the high power situation.Bias voltage Av can tune to minimum value, and avoids original noise problem widely.Even, twoly be specially adapted in the low voltage application, because its induction window will increase because of Δ V with reference to structure cell induction framework.Following equation satisfies speed to be increased because voltage increases:
ΔV＝ΔI×t (5)
Wherein Δ V is a voltage variety, and Δ I is a current change quantity, and t is the time.Thereby, respond in the framework with reference to structure cell at of the present invention pair, if Δ V increases or doubles, need reach the time decreased of identical Δ I.Thereby, twoly improve reading speed widely, especially under low voltage application with reference to structure cell induction framework.
Fig. 4 is an another embodiment of the present invention, and it is two with reference in the structure cell induction framework that it is used in voltage-type.Reference symbol 402,406 and 410 is represented the resistance of the operating voltage (VDD) that is connected to memory crystal cell respectively, is connected to high voltage (HVT) with reference to the resistance of structure cell and low-voltage (LVT) resistance with reference to structure cell.The resistance 402,406 and 410 that is connected to VDD is coupled to current source 404,408 and 412 respectively, so that voltage transitions is become electric charge.Current source 404 produces signal CMI to the positive input terminal of induction amplifier 414 and the negative input end of induction amplifier 416.The high reference voltage structure cell produces the negative input end of signal TREF HVT to induction amplifier 414.The low reference voltage structure cell produces the positive input terminal that signal TREF LVT delivers to induction amplifier 416.Induction amplifier 418 is delivered in induction amplifier 414 and 416 output, by induction amplifier 414 relatively and 416 output Δ SA1 and Δ SA2, to determine the state of memory crystal cell.The equation that calculates Δ SA1 and Δ SA2 is same as equation (3) and (4).It is two with reference to structure cell induction framework that the voltage-type pair voltage patterns with reference to structure cell induction framework are same as current type, and the voltage-type of Fig. 4 is two responds to framework with reference to structure cell so Fig. 2 and Fig. 3 also can be applied to.
Fig. 5 is an another embodiment of the present invention, and it treats as the high reference voltage structure cell with earth terminal.Resistance 512 and current source 514 apply a current potential to memory crystal cell and export a signal CMI.Signal CMI then delivers to the positive input terminal of induction amplifier 522 and the negative input end of induction amplifier 524.High reference voltage (HVT) structure cell is the ground signalling that is coupled to the negative input end of induction amplifier 522.The resistance 518 that is connected to VDD and current source 519 applies a current potential to the low reference voltage structure cell, and exports the positive input terminal of a signal TREF LVT to induction amplifier 514. Induction amplifier 522 and 524 output are connected to the input end of induction amplifier 526 to decide the state of memory crystal cell by comparison signal Δ SA1 and Δ SA2.The equation that calculates Δ SA1 and Δ SA2 is same as equation (3) and (4).It is two with reference to structure cell induction framework that the voltage-type pair voltage patterns with reference to structure cell induction framework are same as current type, and the voltage-type of Fig. 5 is two responds to framework with reference to structure cell so Fig. 2 and Fig. 3 also can be applied to.
Fig. 6 is the two circuit diagrams with reference to structure cell induction framework of the current type of Fig. 1.Reference symbol 116 representative is coupled to high voltage (HVT) among Fig. 1 with reference to the induction amplifier 116 of structure cell and memory crystal cell.Reference symbol 114 representative is coupled to low-voltage (LVT) among Fig. 1 with reference to the induction amplifier 114 of structure cell and memory crystal cell.At this, some transistor merges together to control the input signal of induction amplifier.In this embodiment, the bias of induction amplifier is set. Induction amplifier 114 and 116 output are respectively via two transistors 610 and 620 and be connected to induction amplifier 118.Induction amplifier 118 receipts and comparison Δ SA1 and Δ SA2 close the input transistors of induction amplifier 118 with decision signal SA1OFF or SA2OFF.Final signal OUT is 1 or 0 for the data in the decision memory crystal cell.
Fig. 7 is the two circuit diagrams with reference to structure cell induction framework of current type of the tool variable bias Av of Fig. 1.Reference symbol 116 representative is coupled to high voltage (HVT) among Fig. 1 with reference to the induction amplifier 116 of structure cell and memory crystal cell.Reference symbol 114 representative is coupled to low-voltage (LVT) among Fig. 1 with reference to the induction amplifier 114 of structure cell and memory crystal cell.At this, some transistor merges together to control the input signal of induction amplifier.In this embodiment, the bias of induction amplifier is adjustable.Induction amplifier 114 and each input signal of 116 all can receive adjustable bias voltage Av value (adjustable bias voltage Av value is expressed as " BiasA " in Fig. 7). Induction amplifier 114 and 116 output are respectively via two transistors 710 and 720 and be connected to induction amplifier 118.Induction amplifier 118 receipts and comparison Δ SA1 and Δ SA2 close the input transistors of induction amplifier 118 with decision signal SA1OFF or SA2OFF.Data in the final signal OUT decision memory crystal cell are 1 or 0.
Claims (9)
1. high speed non-volatility memorizer device is characterized in that this device comprises:
At least one memory crystal cell;
One first with reference to structure cell;
One second with reference to structure cell;
One first induction amplifier, its be coupled to this first with reference to structure cell and this memory crystal cell to determine this first with reference to the voltage difference between structure cell and this memory crystal cell;
One second induction amplifier, its be coupled to this second with reference to structure cell and this memory crystal cell to determine this second with reference to the voltage difference between structure cell and this memory crystal cell; And
One the 3rd induction amplifier, it is coupled to this first induction amplifier and this second induction amplifier, determines the state of this memory crystal cell with the voltage difference according to this first induction amplifier and this second induction amplifier.
2. device as claimed in claim 1 is characterized in that, this first comprises a current source and an electric capacity with reference to structure cell, and it produces one first voltage reference signal.
3. device as claimed in claim 1 is characterized in that, this first comprises a current source and an electric capacity with reference to structure cell, and it produces one second voltage reference signal.
4. device as claimed in claim 1 is characterized in that, this first comprises a current source and be connected to the resistance of VDD that with reference to structure cell it produces one first voltage reference signal.
5. device as claimed in claim 1 is characterized in that, this second comprises a current source and be connected to the resistance of VDD that with reference to structure cell it produces one second voltage reference signal.
6. device as claimed in claim 1 is characterized in that, this is first with reference to structure cell ground connection, and this second comprises a current source and a resistance that is connected to VDD with reference to structure cell, and it produces one first voltage reference signal.
7. a high speed non-volatility memorizer device is characterized in that, comprising:
At least one memory crystal cell;
One first with reference to structure cell, and it comprises a current source and an electric capacity;
One second with reference to structure cell, and it comprises a current source and an electric capacity;
One first induction amplifier, its be coupled to this first with reference to structure cell and this memory crystal cell to determine this first with reference to the voltage difference between structure cell and this memory crystal cell;
One second induction amplifier, its be coupled to this second with reference to structure cell and this memory crystal cell to determine this second with reference to the voltage difference between structure cell and this memory crystal cell; And
One the 3rd induction amplifier, it is coupled to this first induction amplifier and this second induction amplifier, determines the state of this memory crystal cell with the voltage difference according to this first induction amplifier and this second induction amplifier.
8. a high speed non-volatility memorizer device is characterized in that, comprising:
At least one memory crystal cell;
One first with reference to structure cell, and it comprises a current source and a resistance that is connected to VDD;
One second with reference to structure cell, and it comprises a current source and a resistance that is connected to VDD;
One first induction amplifier, its be coupled to this first with reference to structure cell and this memory crystal cell to determine this first with reference to the voltage difference between structure cell and this memory crystal cell;
One second induction amplifier, its be coupled to this second with reference to structure cell and this memory crystal cell to determine this second with reference to the voltage difference between structure cell and this memory crystal cell; And
One the 3rd induction amplifier, it is coupled to this first induction amplifier and this second induction amplifier, determines the state of this memory crystal cell with the voltage difference according to this first induction amplifier and this second induction amplifier.
9. a high speed non-volatility memorizer device is characterized in that, comprising:
At least one memory crystal cell;
One first with reference to structure cell, its ground connection;
One second with reference to structure cell, and it comprises a current source and a resistance that is connected to VDD;
One first induction amplifier, its be coupled to this first with reference to structure cell and this memory crystal cell to determine this first with reference to the voltage difference between structure cell and this memory crystal cell;
One second induction amplifier, its be coupled to this second with reference to structure cell and this memory crystal cell to determine this second with reference to the voltage difference between structure cell and this memory crystal cell; And
One the 3rd induction amplifier, it is coupled to this first induction amplifier and this second induction amplifier, determines the state of this memory crystal cell with the voltage difference according to this first induction amplifier and this second induction amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03137421 CN1567479A (en) | 2003-06-20 | 2003-06-20 | High-speed nonvolatile memory device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03137421 CN1567479A (en) | 2003-06-20 | 2003-06-20 | High-speed nonvolatile memory device |
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|---|---|
| CN1567479A true CN1567479A (en) | 2005-01-19 |
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|---|---|---|---|
| CN 03137421 Pending CN1567479A (en) | 2003-06-20 | 2003-06-20 | High-speed nonvolatile memory device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103888A (en) * | 2009-12-18 | 2011-06-22 | Nxp股份有限公司 | Voltage control circuit for phase change memory |
| CN102201806A (en) * | 2010-03-25 | 2011-09-28 | 台湾积体电路制造股份有限公司 | Circuit with current control mechanism and current control method |
-
2003
- 2003-06-20 CN CN 03137421 patent/CN1567479A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103888A (en) * | 2009-12-18 | 2011-06-22 | Nxp股份有限公司 | Voltage control circuit for phase change memory |
| CN102103888B (en) * | 2009-12-18 | 2014-05-28 | Nxp股份有限公司 | Voltage control circuit for phase change memory |
| CN102201806A (en) * | 2010-03-25 | 2011-09-28 | 台湾积体电路制造股份有限公司 | Circuit with current control mechanism and current control method |
| CN102201806B (en) * | 2010-03-25 | 2014-04-16 | 台湾积体电路制造股份有限公司 | Circuit with current control mechanism and current control method |
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Open date: 20050119 |