CN1567092A - Exposure process for different levels - Google Patents
Exposure process for different levels Download PDFInfo
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- CN1567092A CN1567092A CN 03142545 CN03142545A CN1567092A CN 1567092 A CN1567092 A CN 1567092A CN 03142545 CN03142545 CN 03142545 CN 03142545 A CN03142545 A CN 03142545A CN 1567092 A CN1567092 A CN 1567092A
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Abstract
It is a different-level exposure method to take multiple-level exposure to the chip with multiple integration circuit layers by a micro-image machine platform. The method are the following: A, to locate the light cover with multiple out-of-phase circuit images on the micro image machine platform; B, to locate the chip one the micro image machine platform; C, to form a integration circuit layer in the chip from a circuit image in the light cover; D, to re-locate the chip on the micro image machine and furthermore to form another integration circuit layer in the chip form the other circuit image in the cover. This invention adopts only one calibration mark on the cover to relevantly locate on the micro image machine, that is to selectively transfer the images separately on the pre-coat photoresist layer and to relevantly form at least one integration layer on the chip to lower the calibration errors of light cover.
Description
[technical field]
The present invention relates to a kind of exposure method of integrated circuit manufacture process, particularly relate to and a kind ofly can accurately locate light shield, with the exposure method of the different levels that reduce exposure back circuit image error.
[background technology]
Micro-photographing process (photolithography) is one of most crucial steps in the manufacture of semiconductor, and is every and the MOS structurally associated, and for example the image of each layer film (pattern), doped region (dopants) or the like all are processing procedure decisions thus.And, the hierarchy of skill of micro-photographing process, generally not only determined by required use light shield (mask) quantity, and since the light shield usage quantity the more, i.e. the number of times that representative needs the location light shield is the more, and more may cause the positioning correcting error, and then influence the integration (integration) of assembly, therefore, how to reduce the positioning error of location light shield, to promote the Aligning degree of image, be one of striving direction of industry lifting micro-photographing process yield.
Little shadow exposure machine with ASML is an example, as shown in Figure 1, the light shield 1 that is used in micro-photographing process at present comprises most identical circuit images 11, and most M shape coarse positioning marks 12 in corner all around that are divided into, (general employed light shield is identical with icon for matrix pattern alignment mark 14, circuit image with six each intervals, this example is the example explanation with six images also), the chromium film of 11 general plating one layer thickness approximate number hundred of these circuit images forms non-photic zone 13, the phase mutual interference when avoiding exposing between circuit image.
As shown in Figure 2, the micro-photographing process 2 that present semiconductor industry is adopted, be to carry out step 21 earlier above-mentioned light shield 1 with most same line images 11 is placed in the little shadow board, and the locator meams that cooperates board and light shield 1 to preset, the M shape setting mark 12 of light shield 1 and the relative positioning mark (scheming not shown) of board are mated with each other, with relative positioning this light shield 1 and this little shadow board.
Then most chips are disposed into respectively in this little shadow board, and distinguish a relative positioning chip wherein and this little shadow board in regular turn with step 22.
Then carry out step 23,, be exposed on the photoresist layer pre-coated on this chip, form latent image (latent) the circuit image on the light shield 1 11; With step 24, the chip that has had latent image after those exposures is withdrawed from little shadow board again; Then carrying out step 25 carries out the existing development of industry, cleaning, hard roasting, removing photoresistance or mixes (other predetermined metal) ... etc. process, form an integrated circuit layer that corresponds to this circuit image 11; Then, optionally repeat step 21 in regular turn to 25, last, promptly can step 26 on those chips, form most integrated circuit layers respectively, finish the preparation of chip with most integrated circuit layers.
Being familiar with the micro-photographing process personage all knows, because each chip is sent in little shadow board, during little relatively again shadow board location, its issuable positioning error is to be moved and produced with respect to the light shield location by machinery, therefore, the relative board of light shield 1 location is real is the micro-photographing process time error topmost factor of originating of exposing.
Because the volume production cost is required, it is designed that most circuit images 11 on the light shield 1 are the same integrated circuit layer of formation, and can use those images 11 formation latent image that exposes simultaneously in same chip many places simultaneously, and expend time in significantly to reduce exposure, save production cost; Therefore, exposure forms a predetermined integrated circuit layer on the chip, promptly must use at least one light shield (if consider the complexity of integrated circuit, also have and use most light shield multiexposure, multiple exposures to form one deck integrated circuit), and using a slice light shield, then necessary relative positioning light shield and little shadow board are once; Integration with present assembly, general chip must form the integrated circuit layer more than at least six layers, that is to say, necessary relative positioning light shield and little shadow board are more than at least six times, and accumulative total forms uncontrollable alignment error, directly influences chip integration and yield.
Moreover because the manufacturing cost of light shield is very high, therefore, the current chip foundries is all only carried out volume production production in enormous quantities, and the chip that has same components by a large amount of productions is shared the light shield cost, to obtain commercial profit.And for the not rich design corporation of general fund (design house), since its purpose of making assembly be generally its design of experiment integrated circuit quality whether, and the feasibility assessment of volume production listing, so its required manufacturing chip is all based on short run, diversity, therefore, the existing mass production method of most light shields that must use also can't be suitable for; Simultaneously, the accumulative total positioning error of location light shield and little shadow board in micro-photographing process also can influence the degree of accuracy that its experiment is produced, and is difficult to assess the quality of its integrated circuit of testing more.
Therefore, how improving processing procedure, make it be applicable to production short run diversity chip, and can meet more dealers' demand, is that manufacture of semiconductor is studied improved other direction.
[summary of the invention]
The objective of the invention is to be to provide a kind of multi-level exposure method, with the positioning error of light shield and little shadow board in the minimizing micro-photographing process.
Another object of the present invention is to be to provide a kind of can the minimizing to use light shield number, reduction light shield cost, and is applicable to the exposure method of the different levels of production short run diversity chip.
In order to achieve the above object, the invention provides a kind of exposure method of different levels, with a little shadow board one chip is exposed at many levels, this chip has most integrated circuit layers, it is characterized in that:
This method comprises the following steps:
(A) light shield with most different circuit images is positioned on this little shadow board;
(B) this chip is positioned on this little shadow board;
(C) this light shield circuit image correspondence wherein is shaped this chip integrated circuit layer wherein;
(D) this chip is re-positioned on this little shadow board, and then with this light shield another circuit image correspondence this chip another integrated circuit layer wherein that is shaped wherein.
The exposure method of described different levels is characterized in that: this method also comprises the step (E) that repeats this step (D).
The exposure method of described different levels is characterized in that: this step (C) also has step following time:
(C1) this light shield circuit image wherein is transferred on the pre-coated photoresist layer of this chip;
(C2) this chip is withdrawed from this little shadow board;
(C3) correspondence this circuit image that is shaped.
The exposure method of described different levels is characterized in that: this step (C3) is selectively developed, baking, removing photoresistance, and/or the doping process.
The exposure method of described different levels is characterized in that: this step (D) also has step following time:
(D1) with this light shield wherein another circuit image shift on another pre-coated photoresist layer of this chip;
(D2) this chip is withdrawed from this little shadow board;
(D3) correspondence this another circuit image that is shaped.
The exposure method of described different levels is characterized in that: this step (D3) is selectively developed, baking, removing photoresistance, and/or the doping process.
The exposure method of described different levels is characterized in that: this light shield is a binary mask, and/or the phase transfer light shield.
The present invention also provides a kind of exposure method of different levels, with a little shadow board one chip is exposed at many levels, and this chip has most integrated circuit layers, it is characterized in that:
This method comprises the following steps:
(a) light shield with most circuit images is positioned on this little shadow board;
(b) this chip is positioned on this little shadow board;
(c) this light shield circuit image correspondence wherein is shaped the integrated circuit of this chip layer segment wherein;
(d) this chip is re-positioned on this little shadow board, so with this light shield wherein another circuit image correspondence be shaped this chip this integrated circuit layer another partly.
The exposure method of described different levels is characterized in that: this method also comprises the step (e) that repeats this step (d), this integrated circuit layer of this chip that is shaped.
The exposure method of described different levels is characterized in that: this step (c) also has step following time:
(c1) this light shield circuit image wherein is transferred on the pre-coated photoresist layer of this chip;
(c2) this chip is withdrawed from this little shadow board;
(c3) correspondence this circuit image that is shaped.
The exposure method of described different levels is characterized in that: this step (c3) is selectively developed, baking, removing photoresistance, and/or the doping formality.
The exposure method of described different levels is characterized in that: this step (d) also has step following time:
(d1) with this light shield wherein another circuit image shift on another pre-coated photoresist layer of this chip;
(d2) this chip is withdrawed from this little shadow board;
(d3) correspondence this another circuit image that is shaped.
The exposure method of described different levels is characterized in that: this step (d3) is selectively developed, baking, removing photoresistance, and/or the doping formality.
The exposure method of described different levels is characterized in that: this light shield is a binary mask, and/or the phase transfer light shield.
In sum, the exposure method 3 of different levels of the present invention, circuit image with most layer integrated circuit layer, be formed in the single light shield 4, and only with relative positioning light shield and little shadow board or corresponding identical light shield alignment mark, get final product the most layer lines of repetitive displacement road image, and corresponding most layer integrated circuit layer that are shaped, not only can reduce to the error of location light shield and little shadow board minimum, also can reduce simultaneously the quantity of using light shield, and can significantly reduce production costs, be specially adapted to the procedure for producing of small-lot chips, and reach purpose of the present invention really.
[description of drawings]
The present invention is described in detail below in conjunction with drawings and Examples:
Fig. 1 is a synoptic diagram, illustrates that one has the light shield of most same line images;
Fig. 2 is a process flow diagram, and existing micro-photographing process is described;
Fig. 3 is a synoptic diagram, and the light shield with most different circuit diagram pictures of the exposure method that is used in different levels of the present invention is described;
Fig. 4 is a process flow diagram, and the exposure method of different levels of the present invention is described.
[embodiment]
The exposure method 3 of different levels of the present invention is suitable for and makes the most chips of short run, and with a little shadow board chip exposed at many levels, and this each chip has plural integrated circuit layer respectively, and this example will be the example explanation to form six layers of integrated circuit layer.
As shown in Figure 3, light shield 4 used in the present invention can be binary mask, or phase transfer light shield, comprise six different circuit images 41,42,43,44,45,46, and the cruciform in corner or M shape setting mark 47 around most being divided into (in the icon be example explanation with the M shape), this each circuit image 41,42,43,44,45, the 46th, design at each layer integrated circuit, and these circuit images 41,42,43,44,45,46 also the chromium film of plating one layer thickness approximate number hundred form non-photic zone 48, the phase mutual interference when avoiding exposing between circuit image.
As shown in Figure 4, the exposure method 3 of different levels of the present invention, earlier have six different circuit diagrams as 41,42,43,44,45,46 light shield 4 with above-mentioned with step 31, be placed in the little shadow board, the shadow board that declines of the stepping/scanning of the labels such as ASML, Nikon that adopt of industry now for example, and the locator meams that cooperates board and light shield 4 to preset, M shape (or cruciform) setting mark 47 of light shield 4 and the relative positioning mark (scheming not shown) of board are mated with each other, with relative positioning this light shield 4 and this little shadow board; Then most chips are disposed into respectively in this little shadow board with step 32, and relatively move the in regular turn respectively wherein chip and this little shadow board relative positioning of a predetermined exposure.
Then carry out step 33,, be exposed on the photoresist layer pre-coated on this chip, form first latent image the circuit image on the light shield 4 41; With step 34, the chip that has had first latent image after those exposures is withdrawed from little shadow board again; Then with step 35, carry out the existing development of industry, cleaning, toast, mix or etching (different predetermined metal), carry out removing photoresistance (normally removing predetermined useless photoresistance) again with etching mode ... etc. process, formation corresponds to the ground floor integrated circuit of this circuit image 41, owing to development, cleaning, baking, removing photoresistance in the step 35, mix ... etc. process, think that industry knows, and non-emphasis of the present invention place, so do not add to describe in detail at this.
Then, repeat step 32, step 33, step 34, and step 35, those chips are conveyed in this little shadow board once more, again in regular turn behind relative positioning one chip and this little shadow board, again in regular turn with other the most circuit images 42,43,44,45,46 on the light shield 4 of little relatively shadow board location, exposure forms second and third respectively ..., six latent images, be formed separately out more corresponding second and third ..., six layers of integrated circuit layer, at last, then, finish the preparation that those have the chip of six layers of integrated circuit layer as step 36.
Following tabulation 1 as can be known, the exposure method 3 prepared chips of finishing of different levels of the present invention, the maximum aliasing error of x direction (overlay error) of its second layer integrated circuit (i.e. PL1 in the table) is 12nm, the maximum aliasing error of y direction is 31nm, the maximum aliasing error of x direction of the 3rd layer of integrated circuit (i.e. PL4 in the table) is 25nm, and the maximum aliasing error of y direction then is 10nm; And existing replacing 6 light shields that need, locate the processing procedure of six light shields and little shadow board, the maximum aliasing error of x direction of its second layer integrated circuit (i.e. PL1 in the table) is 53nm, the maximum aliasing error of y direction is 42nm, the maximum aliasing error of x direction of the 3rd layer of integrated circuit (i.e. PL4 in the table) is 43nm, the maximum aliasing error of y direction is 28nm, obviously, the exposure method 3 of different levels of the present invention, in the most important exposure image accuracy, more existing micro-photographing process 2 has improvement significantly in micro-photographing process.
Table 1
Because, the exposure method 3 of different levels of the present invention, circuit image 41,42,43,44,45,46 with most layer integrated circuit, be formed in the single light shield 4, therefore, only need repeated exposure to finish six layer line road images 41,42,43,44,45,46, therefore can reduce to minimum with the error of little shadow board manually locating light shield 4 with the corresponding identical light shield 4 of step 31 and little shadow board; Simultaneously, because circuit image 41,42,43,44,45,46 is all inequality, though therefore the time shutter uses the light shield 1 with most same line images 11 to increase, but when most chip of production short run, time cost difference is little, thereby for IC design corporation (designhouse), because whether the quality of the integrated circuit that its purpose of making assembly only is its design of experiment, and the feasibility assessment of volume production listing, the general equal minute quantity of the quantity of required manufacturing chip, so artificial positioning error that the exposure method 3 of different levels of the present invention not only can be minimum, promote the degree of accuracy that its experiment is produced, can reduce simultaneously the number of its light shield that uses, reduce investment amount,, use the cost of processing procedure of the present invention approximately only to need 4,000,000 New Taiwan Dollar to produce the chip of six layers of integrated circuit, the cost of investment more than 5,000,000 yuan is significantly saved in existing 9,000,000 cost budgetings that must use the existing processing procedure of six light shields.
In addition, being familiar with the manufacture of semiconductor personage can be learnt easily by above-mentioned explanation, little shadow board of all use TTLAlignment (Through The Lens) location light shield, all can simply use the exposure method 3 of different levels of the present invention, use the light shield number and can significantly reduce, reduce positioning error, and be not limited to stepping/scanning shadow board that declines, little shadow board that other for example uses contact (contact), close induction type (proximity) exposure similarly also can use the present invention.
Moreover, what specify is, because the circuit image 41,42,43,44,45,46 on the light shield 4 used in the present invention is all inequality, therefore, can design those circuit images 41,42,43,44,45,46 in advance, after using wherein most circuit images 41,42,43,44,45,46 to be exposed to a pre-coated photoresist layer of chip respectively jointly, form the wherein integrated circuit layer of one deck of chip accordingly, form more complicated integrated circuit layer with higher yield; Also can be behind light shield 4 location, use on the light shield most video picture patterns 41,42,43,44,45,46 to be exposed to each presumptive area of chip simultaneously simultaneously, and on chip respectively should the zone, make the different most chips of functional configuration, produce the assembly of more kinds of designs with combination system on one chip, to meet productivity effect.
In sum, because semiconductor industry is the industry of a fund highly dense, therefore, the research of its all processing procedures improves, all develop according to mass production, phase is to produce in enormous quantities to reduce production costs, obtain commercial profit, also therefore, for the not rich design corporation of general fund, to the existing micro-photographing process 2 that must carry out with most light shields easily, really be a white elephant, and the exposure method 3 of different levels of the present invention, the circuit image with most layer integrated circuit layer is formed in the single light shield 4, and only with relative positioning light shield and little shadow board or corresponding identical light shield alignment mark, get final product the most layer lines of repetitive displacement road image, and corresponding most layer integrated circuit layer that are shaped not only can be reduced to the error of location light shield and little shadow board minimum, also can reduce simultaneously the quantity of using light shield, and can significantly reduce production costs, be specially adapted to the procedure for producing of small-lot chips, and reach purpose of the present invention really.
Claims (14)
1. the exposure method of different levels exposes to a chip at many levels with a little shadow board, and this chip has most integrated circuit layers, it is characterized in that:
This method comprises the following steps:
(A) light shield with most different circuit images is positioned on this little shadow board;
(B) this chip is positioned on this little shadow board;
(C) this light shield circuit image correspondence wherein is shaped this chip integrated circuit layer wherein;
(D) this chip is re-positioned on this little shadow board, and then with this light shield another circuit image correspondence this chip another integrated circuit layer wherein that is shaped wherein.
2. the exposure method of different levels as claimed in claim 1, it is characterized in that: this method also comprises the step (E) that repeats this step (D).
3. the exposure method of different levels as claimed in claim 1, it is characterized in that: this step (C) also has step following time:
(C1) this light shield circuit image wherein is transferred on the pre-coated photoresist layer of this chip;
(C2) this chip is withdrawed from this little shadow board;
(C3) correspondence this circuit image that is shaped.
4. the exposure method of different levels as claimed in claim 3 is characterized in that: this step (C3) is selectively developed, baking, removing photoresistance, and/or the doping process.
5. the exposure method of different levels as claimed in claim 1, it is characterized in that: this step (D) also has step following time:
(D1) with this light shield wherein another circuit image shift on another pre-coated photoresist layer of this chip;
(D2) this chip is withdrawed from this little shadow board;
(D3) correspondence this another circuit image that is shaped.
6. the exposure method of different levels as claimed in claim 5 is characterized in that: this step (D3) is selectively developed, baking, removing photoresistance, and/or the doping process.
7. the exposure method of different levels as claimed in claim 1, it is characterized in that: this light shield is a binary mask, and/or the phase transfer light shield.
8. the exposure method of different levels exposes to a chip at many levels with a little shadow board, and this chip has most integrated circuit layers, it is characterized in that:
This method comprises the following steps:
(a) light shield with most circuit images is positioned on this little shadow board;
(b) this chip is positioned on this little shadow board;
(c) this light shield circuit image correspondence wherein is shaped the integrated circuit of this chip layer segment wherein;
(d) this chip is re-positioned on this little shadow board, so with this light shield wherein another circuit image correspondence be shaped this chip this integrated circuit layer another partly.
9. the exposure method of different levels as claimed in claim 8, it is characterized in that: this method also comprises the step (e) that repeats this step (d), this integrated circuit layer of this chip that is shaped.
10. the exposure method of different levels as claimed in claim 8, it is characterized in that: this step (c) also has step following time:
(c1) this light shield circuit image wherein is transferred on the pre-coated photoresist layer of this chip;
(c2) this chip is withdrawed from this little shadow board;
(c3) correspondence this circuit image that is shaped.
11. the exposure method of different levels as claimed in claim 10 is characterized in that: this step (c3) is selectively developed, baking, removing photoresistance, and/or the doping formality.
12. the exposure method of different levels as claimed in claim 8 is characterized in that: this step (d) also has step following time:
(d1) with this light shield wherein another circuit image shift on another pre-coated photoresist layer of this chip;
(d2) this chip is withdrawed from this little shadow board;
(d3) correspondence this another circuit image that is shaped.
13. the exposure method of different levels as claimed in claim 12 is characterized in that: this step (d3) is selectively developed, baking, removing photoresistance, and/or the doping formality.
14. the exposure method of different levels as claimed in claim 8 is characterized in that: this light shield is a binary mask, and/or the phase transfer light shield.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031425453A CN100478782C (en) | 2003-06-16 | 2003-06-16 | Exposure process for different levels |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031425453A CN100478782C (en) | 2003-06-16 | 2003-06-16 | Exposure process for different levels |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1567092A true CN1567092A (en) | 2005-01-19 |
| CN100478782C CN100478782C (en) | 2009-04-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB031425453A Expired - Fee Related CN100478782C (en) | 2003-06-16 | 2003-06-16 | Exposure process for different levels |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101989039B (en) * | 2009-08-05 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Method for fabricating photomask |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5573890A (en) * | 1994-07-18 | 1996-11-12 | Advanced Micro Devices, Inc. | Method of optical lithography using phase shift masking |
| CN1053065C (en) * | 1996-11-04 | 2000-05-31 | 合泰半导体股份有限公司 | Method for making integrated circuit |
| CN1206701C (en) * | 2001-03-29 | 2005-06-15 | 华邦电子股份有限公司 | Optical mask structure and microphotograph process |
| CN1224078C (en) | 2001-03-30 | 2005-10-19 | 华邦电子股份有限公司 | Miniaturization process for multi-layer thin photoresist |
-
2003
- 2003-06-16 CN CNB031425453A patent/CN100478782C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101989039B (en) * | 2009-08-05 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Method for fabricating photomask |
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| CN100478782C (en) | 2009-04-15 |
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