CN1564318A - Design method of 0.35 um LDMOS high vltage power displaying driving element - Google Patents

Abstract

Base on compatible standard 0.5 micro technique, two times of ion implantation in P, N channel regions, and two times of ion implantation in P, N drift regions are added in the invention. The procedures adopted in the invention are as following: reaching thickness in 100 Angstrom of gate oxidizing layer; injecting boron and phosphorus impurities after forming polysilicon gate; forming channels in 0.3-0.4 micro, short drift region and P, N MOS devices through transverse diffusion and self alignment. On P trap, one time of ion implantation in drift region and one time of doping injection in channel region produces PMOS device. One time of ion implantation in P drift region on N trap and one time of doping injection in channel region produces NMOS device. Features are small area of tube core, and large driving current.

Description

0.35 the method for designing of μ m LDMOS high-voltage power display drive device

Technical field

0.35 the method for designing of μ m LDMOS high-voltage power display drive device, belong to high-voltage power display drive device manufacture technology field, especially design the high-voltage power display driver technical field that Organic Light Emitting Diode OLED (Organic Light Emission Diode) black and white, colorful display screen are used.

Background technology

By retrieval, in State Intellectual Property Office's net, the patent in similar field is TFT (Thin Film Transistor) LCD (LiquidCrystal Display) drive circuit.Voltage is up to about 70V, and electric current is a milliampere level.Indivedual patents relate to PDP (PlasmaDisplay Panel) drive circuit, high pressure 80V, single tube output current 40mA.

Do not see the granted patent of relevant OLED drive circuit aspect.

Fig. 1 is article " High-Voltage Device for 0.5 μ m Standard CMOS Technology " report in 2002, utilizes standard 0.5 μ m CMOS technology to make the HV-NMOS high tension apparatus, and puncture voltage can reach 100V.Gate oxide 100 , channel length 3 μ m, drift region L _Dd=6.5 μ m.Need on standard 0.5 μ m CMOS technology basis, to increase by two mask and the injection of two secondary ions.Fig. 1 is the device architecture figure that paper provides, and wherein, Sub is a raceway groove substrate exit, and Ldd is a drift region diode length, and Lg is the geometric parameter that grid cover the drift region.The HV-PMOS device is not seen research report as yet.

Technique scheme is suitable for high voltage-small current LCD drive circuit.3 μ m raceway grooves will significantly reduce the mutual conductance of device.Improve electric current output, must strengthen channel width, thereby strengthen the device gross area.Long raceway groove, long drift region will make the device saturation voltage drop increase, and power consumption strengthens, and reduces current driving ability.

Domestic article " the HV-CMOS designs of pdp data chip for driving " has designed PDP display driver high tension apparatus based on 0.6 μ m standard CMOS process, single tube high pressure 80V, N pipe output current 40mA.High-pressure output tube raceway groove 1.5 μ m, drift region 7.5 μ m, N pipe gate oxide is 200 , P manages 1600 .The technical scheme of article introduction is suitable for middle electric current (40mA) PDP display driver circuit.

According to the technological process that Fig. 2 and article provide, high pressure N pipe is typical DMOS (Doublediffused MOSFET) device, rather than the LDMOS that mentions in the literary composition (Lateral Double diffusedMOSFET).In addition, HV-PMOS uses the thick grating oxide layer of 1600 , differs greatly with low-voltage tube 200 oxide layers, has increased technology difficulty, has reduced the device mutual conductance.

Existing OLED drive circuit has adopted the conventional raceway groove of 2 μ m and has leaked expansion technique or DMOS technology, the puncture voltage 20-40V of high-voltage power driving element, and real work voltage is mostly between 15-30V.

This shows:

1). the patent that can find and document are about in the display driver circuit now, the report that high-pressure output tube manufactures and designs, all adopted common double diffusion DMOS device, channel length is 1.5～3 μ m, uses drift region (drift), gently mixes up leakage (LDD) and expansion leakage structure drive currents such as (EDMOS) at 40mA or following.

2). the shortcoming of above structure:

A. raceway groove is long, and mutual conductance is low, and the electric current of unit channel width is little.

B. two trap diffusions are difficult to shorten channel length, and existing length is 1.5～3 μ m.

C. because of operating current big (150mA), number of devices many (more than 100), the tube core gross area is excessive.

Summary of the invention

The object of the present invention is to provide a kind of OLED of being used for display screen, drive current is big, die area is little, and conducting resistance is low, with 0.5 μ m CMOS process compatible, the method for designing of 0.35 μ m LDMOS high-voltage power display drive device.

The invention is characterized in: it is a kind of and 0.5 μ m standard CMOS process compatibility, the method for designing of autoregistration 0.3-0.4 μ m magnitude raceway groove, horizontal proliferation LD-NMOS device, and it contains following steps successively:

(1) on N type silicon chip, subregion forms P type and N moldeed depth trap, representative value 4-6 μ m;

(2) in the P trap, annotate phosphorus and form N drift region, typical doses 3.5-7.5E12, typical junction depth 0.8-2 μ m;

(3) selectivity field oxidation 4500 , on other parts of silicon chip, forming thickness is the gate oxide of 100 ;

(4) deposit polysilicon carries out phosphorous diffusion then and mixes up;

(5) etching forms silicon gate electrode, the N drift region intersection of gate electrode in P trap and trap, and the typical case covers the P trap and the N drift region is respectively 0-1 μ m and 1-2 μ m;

(6) in p type island region one side of polycrystalline gate electrode, inject boron impurity, typical doses is 2-4E13, and the horizontal proliferation autoregistration forms the raceway groove of 0.3-0.4 μ m magnitude;

(7) the N pipe is annotated phosphorus, forms the N type in the Si-gate both sides and gently mixes up the drain region, and promptly LDD and side wall carry out simultaneously with 0.5 μ m low voltage CMOS;

(8) in p type island region one side of polycrystalline gate electrode, inject phosphorus impurities, typical doses is 3E15, forms the source electrode;

(9) in the source electrode outside, inject boron impurity, typical doses 2E14 forms the raceway groove substrate contact region;

(10) raceway groove substrate contact region and source region form the alternate layout of N+, P+.

(11) in above-mentioned N drift region, in the place of distance raceway groove edge 2-5 μ m, implantation dosage is the phosphorus impurities of 3E15, forms the drain contact district, forms 2-5 μ m simultaneously and leaks the drift region;

(12),, in the source, leakage, grid metallization, and after the alloy annealing, form the LD-NMOS device with source region and raceway groove substrate contact region short circuit in when metallization.See Fig. 3 and Figure 10.

2. the method for designing of 0.35 μ m LD-PMOS high pressure display drive device, it is characterized in that, it is a kind of autoregistration 0.3-0.4 μ m magnitude raceway groove of and 0.5 μ m standard CMOS process compatibility, the method for designing of horizontal proliferation LDPMOS device, and it contains following steps successively:

(1) on N type silicon chip, subregion forms P type and N moldeed depth trap, representative value 4-6 μ m;

(2) on the N trap, annotate boron and form P trap, typical doses 3.5-7.5E12, typical junction depth 0.8-2 μ m;

(3) selectivity field oxidation 4500 , on other parts of silicon chip, forming thickness is the gate oxide of 100 ;

(4) deposit polysilicon then, expands phosphorus and mixes up;

(5) etching forms gate electrode;

(6) in the N district of polygate electrodes one side, inject N type foreign matter of phosphor, typical doses is 2-4e13, horizontal proliferation, autoregistration form the raceway groove of 0.3-0.4 μ m magnitude;

(7) the P pipe is annotated boron, forms the P type in the Si-gate both sides and gently mixes up the drain region, and promptly LDD and side wall carry out simultaneously with 0.5 μ m low voltage CMOS;

(8) in the N district of polycrystalline gate electrode one side, injecting typical doses is the boron impurity of 1E15, forms P ⁺The source region;

(9) in the outside, source region, inject phosphorus impurities, typical doses 2E15 forms N ⁺The raceway groove substrate contact region;

(10) N ⁺Raceway groove substrate contact region and P ⁺Form N between the source region ⁺, P ⁺Alternate layout;

(11) in above-mentioned P trap, in the place of distance raceway groove edge 2-5 μ m, injecting typical doses is the boron impurity of 1E15, forms P ⁺The drain contact district, the P type that forms 2-5 μ m length simultaneously leaks the drift region;

(12) when metallization with source region and raceway groove substrate contact region short circuit, after source, leakage, grid metallization and alloy annealing, form the LD-PMOS device.See Fig. 4 and Figure 10.

Experiment showed, that it can accomplish:

The drive circuit that is used for OLED, its current drive capability can reach 1～2mA/ μ m, and than the high magnitude of existing high drive current capacity 100～200 μ A/ μ m, area reduces more than the 50-60%.

Driving stage operating voltage 15～30V, LDNMOS pipe drive current 150mA, conducting resistance is less than 20 Ω, and area obviously dwindles than existing device.With standard 0.5 μ m CMOS process compatible.

LDPMOS device work low pressure 15～30V, drive current does not have specific (special) requirements.

Accompanying drawing proves

Fig. 1. existing HV-NMOS structure chart.

Fig. 2. existing common DMOS device architecture figure.

Fig. 3 .0.35 μ m LD-NMOS device architecture figure.

Fig. 4 .0.35 μ m LD-PMOS device architecture figure.

Fig. 5 .4 the driving element outside drawing that 0.35 μ m LD-NMOS unit composes in parallel.

Fig. 6. the source region design diagram.

Fig. 7. unit component plane graph and reticle schematic diagram.

Fig. 8 .0.35 μ m LDNMOS processing simulation result (SILVACO Athena) schematic diagram.

Fig. 9 .0.35 μ m LDNMOS virtual device breakdown characteristics (SILVACO ATLAS) curve chart.

Figure 10 .0.35 μ m LDPMOS and LDNMOS process flow diagram.

The compatible schematic diagram of Figure 11 high-voltage LDMOS device and low pressure 0.5 μ m CMOS.

The drive circuit schematic diagram that Figure 12 .OLED uses.

Embodiment:

The present invention adopts the LDMOS structure, with 0.5 μ m standard CMOS process compatibility, manufactures and designs the driving tube of high-voltage power driving stage, can significantly increase current driving ability, dwindles die area, reduces conducting resistance.

Embodiment:

Fig. 5 is 4 0.35 μ m, the domain of the actual use of the driving element that the LD-NMOS unit composes in parallel (for clarity sake, grid fall some details).Wherein the unit component channel length is L=0.35 μ m, overall width W=160 μ m, gate oxide d _Ox=100 , cut-in voltage V _T=0.7V.At gate voltage V _GDuring=4V, leakage current I _D=1mA/ μ m.160 row drive array, cellar area 28 * 40=1120 μ m ², the gross area 160 * 28 * 40=4480 * 40 μ m ²Can change 160 * 14 * 80=2240 * 80 μ m as required into ²Arrange.A kind of arrangement in back, current in wire density reaches 1.6 * 10 ⁶/ cm ², but since duty ratio less than 0.01, this programme is feasible.

Plane graph and the sectional structure chart of LDPMOS are similar, just mix up difference.Most important difference is that the raceway groove overall width of P pipe is about 20 μ m, is 1/8 of N pipe, because of it need not bear too big electric current.

Fig. 6 is the layout of the lead-in wire contact zone of source and raceway groove substrate.N+ is the contact zone, source, and P+ is the raceway groove substrate contact region.

Fig. 7 is 0.35 μ m LDMOS unit component plane graph and reticle schematic diagram, referring to figure (turning 90 degrees) in Fig. 5 square frame.Wherein, D is the drain region, and G is the polycrystalline grid, and empty frame is the channel dopant injection region, and mid portion is shown in Figure 6.

Fig. 8 is the process simulation figure of LDNMOS device.Promptly use the actual technology of using as initial conditions, carry out the virtual device profile (SILVACO, ATHENA process simulation software) that obtains behind the process simulation.

As seen from the figure, it has the raceway groove of 0.35 μ m, the drift head of district 2.5 μ m junction depths 0.8 μ m.

Basic technology parameter condition:

(1) P trap surface concentration 5E15/cm ³(5) raceway groove is annotated boron dosage 4e13/cm ², 40KeV

(2) phosphorus 4E12 is annotated in the drift region, and (6) source is leaked N+ and injected: annotate phosphorus dosage 1e15/cm ², 40KeV 40KeV

(3) oxygen: 4900

(7) P+ injects: annotate boron dosage 5e14/cn ², 40KeV

(8) N substrate

(4) grid oxygen: 100

Fig. 9 is to the result of virtual device spare test, shows among the figure that puncture voltage is 30V.Conform to actual test result.

Figure 10 is 0.35um LDPMOS and LDNMOS process flow diagram.Device fabrication process flow and device architecture forming process are described step by step.

Figure 11 has illustrated high-voltage LDMOS device and the compatible schematic diagram of low pressure 0.5 μ m CMOS.

The dotted portion of Figure 12 is one and is used for the basic circuit that OLED drives.P ₃, N ₃Be respectively PMOS and NMOS driving tube, form driving stage.

Claims (2)

1. the method for designing of 0.3-0.4 μ m magnitude LDNMOS high-voltage power display drive device is characterized in that,

It is a kind of and 0.5 μ m standard CMOS process compatibility, the method for designing of autoregistration 0.3-0.4 μ m magnitude raceway groove, horizontal proliferation (LD) nmos device, and it contains following steps successively:

(1) on N type silicon chip, subregion forms P type and N moldeed depth trap, representative value 4-6 μ m;

(2) in the P trap, annotate phosphorus and form N drift region, typical doses 3.5-7.5E12, typical junction depth 0.8-2 μ m;

(3) selectivity field oxidation 4500 , on other parts of silicon chip, forming thickness is the gate oxide of 100 ;

(4) deposit polysilicon carries out phosphorous diffusion then and mixes up;

(5) etching forms silicon gate electrode, the N drift region intersection of gate electrode in P trap and trap, and the typical case covers the P trap and the N drift region is respectively 0-1 μ m and 1-2 μ m;

(6) in p type island region one side of polycrystalline gate electrode, inject boron impurity, typical doses is 2-4E13, and the horizontal proliferation autoregistration forms the LDNMOS device channel of 0.3-0.4 μ m magnitude;

(7) the N pipe is annotated phosphorus, forms the N type in the Si-gate both sides and gently mixes up the drain region, and promptly LDD and side wall carry out simultaneously with 0.5 μ m low voltage CMOS;

(8) in p type island region one side of polycrystalline gate electrode, inject phosphorus impurities, typical doses is 3E15, forms the source electrode;

(9) in the source electrode outside, inject boron impurity, typical doses 2E14 forms the raceway groove substrate contact region;

(10) raceway groove substrate contact region and source region form the alternate layout of N+, P+.

(11) in above-mentioned N drift region, in the place of distance raceway groove edge 2-5 μ m, implantation dosage is the phosphorus impurities of 3E15, forms the drain contact district, forms 2-5 μ m simultaneously and leaks the drift region;

(12),, in the source, leakage, grid metallization, and after the alloy annealing, form the LD-NMOS device with source region and raceway groove substrate contact region short circuit in when metallization.

2. the method for designing of 0.3-0.4 μ m magnitude LD-PMOS high pressure display drive device, it is characterized in that, it is a kind of autoregistration 0.3-0.4 μ m magnitude raceway groove of and 0.5 μ m standard CMOS process compatibility, the method for designing of horizontal proliferation LDPMOS device, and it contains following steps successively:

(1) on N type silicon chip, subregion forms P type and N moldeed depth trap, representative value 4-6 μ m;

(2) in the N trap, annotate boron and form P trap, typical doses 3.5-7.5E12, typical junction depth 0.8-2 μ m;

(3) selectivity field oxidation 4500 , on other parts of silicon chip, forming thickness is the gate oxide of 100 ;

(4) deposit polysilicon then, expands phosphorus and mixes up;

(5) etching forms gate electrode;

(6) in the N district of polygate electrodes one side, inject N type foreign matter of phosphor, typical doses is 2-4e13, horizontal proliferation, autoregistration form the raceway groove of 0.3-0.4 μ m magnitude;

(7) the P pipe is annotated boron, forms the P type in the Si-gate both sides and gently mixes up the drain region, and promptly LDD and side wall carry out simultaneously with 0.5 μ m low voltage CMOS;

(8) in the N district of polycrystalline gate electrode one side, injecting typical doses is the boron impurity of 1E15, forms P ⁺The source region;

(9) in the outside, source region, inject phosphorus impurities, typical doses 2E15 forms N ⁺The raceway groove substrate contact region;

(10) N ⁺Raceway groove substrate contact region and P ⁺Form N between the source region ⁺, P ⁺Alternate layout;

(11) in above-mentioned P trap, in the place of distance raceway groove edge 2-5 μ m, injecting typical doses is the boron impurity of 1E15, forms P ⁺The drain contact district, the P type that forms 2-5 μ m length simultaneously leaks the drift region;

(12) when metallization with source region and raceway groove substrate contact region short circuit, after source, leakage, grid metallization and alloy annealing, form the LD-PMOS device.

Images