CN1564196A - VLSI realizing method of synchronous flowing arithmetic coder - Google Patents

Abstract

The invention discloses a method for designing structure and key circuit of synchronous pipelining arithmetic coder suitable to hardware of image compression and video processing. For instance, JPEG2000 chip is capable of coding N pieces of input within N+3 timing cycle based on context-sensitive self-adapting arithmetic coder. Thus, following change is taken: flow of arithmetic coder in JPEG2000 protocol is converted to pipeline structure in three steps and assistant steps; putting forward optimizing algorithm in second and third steps in pipeline, index selection logic of Qe table under continuous CX input etc. Optimized result meets requirement of 200M timing clock under .25 micro techniques.

Description

The VLSI implementation method of synchronous flowing water arithmetic encoder

Technical field

The invention belongs to the VLSI design field.Be specifically related to the VLSI implementation method of a kind of synchronous flowing water arithmetic encoder in the hardware of compression of images or Video processing is realized.

Background technology

That uses in the JPEG2000 standard is based on contextual adaptive arithmetic code device, but the flow process that is provided in the standard relatively is applicable to the serial of software and realizes, in the exploitation of JPEG2000 chip, as use flow process in the standard, realize arithmetic encoder with state machine, then need input of 4 clock codings at least, add byteout, then need 6-7 clock.M.Tarui has proposed to use pipeline to realize arithmetic coding among the JBIG in " High speed implementation ofJBIG Arithmetic coder " [1], mainly show to realize the renewal of CX table by improved Qe, Keng-Khai exists " A high throughput context-based adaptive arithmetic codec for JPEG2000 " in [2] when using The pipeline design, a kind of bitstuffing flow process has been proposed, and provide the summary structural design, K-F.Chen is providing the summary structural design simultaneously in " Analysis andarchitecture design of EBCOT in JPEG2000 " [3], proposition is divided into 16 and 12 to reduce critical path with register C (to call CREG in the following text), but [1] be primarily aimed at arithmetic encoder among the JBIG, and revising the Qe table has increased storer, is 4 step streamlines; [1] [2] [3] do not provide the operation of Key Circuit and CX table, do not consider complete optimization, Key Circuit realization and the additional step that realizes the critical path that institute must consider of arithmetic encoder flowing water simultaneously.

Summary of the invention

According to above-mentioned situation, the object of the invention is, a kind of VLSI implementation method of synchronous flowing water arithmetic encoder is provided, and this method has provided the complete structural design of synchronous flowing water arithmetic encoder and Key Circuit realizes and the optimization of critical path.

The technical solution that realizes above-mentioned purpose is: the VLSI implementation method of synchronous flowing water arithmetic encoder, carry out according to the following steps:

1) at first the flow process of the arithmetic encoder in the JPEG2000 agreement is converted into three step pipeline organizations and additional step (the flush flow process in the agreement is seen the agreement Figure C-11 of JPEG2000)

2) second step and the 3rd in the three step streamlines is gone on foot the optimization that proposes algorithm level.

3) index (index) acquisition methods that the Qe under a kind of continuous CX shows is proposed; This method makes not to be needed the Qe probability tables is made amendment.

4) a kind of first nonzero digit testing circuit that uses the register A of combinational logic realization is proposed, with the realization in second step of accelerating flow waterline.

5) adopt several different methods that its critical path is optimized to second step and the 3rd step.

Described three step streamlines and supporting process are meant the inquiry that the whole flow process of arithmetic encoder is divided into four operation: CX tables by implementation procedure, the reading of the inquiry of Qe table and qe value (first step), the renewal (second step) of low 20 renewals of the renewal of register A, register C and CX table, the renewal of register C and byte output (byteout) (the 3rd step), with a supporting process (flush), to finish last byte output, as shown in Figure 1.

Because in second step and the 3rd step of streamline, the path of combinational logic is long, therefore at first need be optimized on algorithm, to reduce critical path.

By the regulation of the flow process in the agreement, when coding, at first inquire about the CX table, required qe value when coding found in the allocation index of the Qe table that is obtained by CX table again, the updating value of the current C X list item of the branch decision CX table of being walked by encoding again, the selection of the index of the Qe table when therefore CX imports continuously is the key point that restriction arithmetic encoder flowing water is realized.

In cataloged procedure, when the value of register A (16 bit) during less than 0X8000H, need be to the A normalization (Renorme in the agreement, see Figure C-8), A promptly moves to left, greater than 0X8000H,, at first need to detect the figure place that A need move to left up to the A value in single clock therefore for it is finished, as A=16 ' b0001,0100,1000,0001 o'clock, A need move to left three, to determine promptly that A counts from a left side first 1 before 0 number, be defined as the zero-bit testing circuit of A, provide the combinational circuit of this realization at this.

After overcoming the above problems, for making synchronous flowing water arithmetic encoder really practical, need the main critical path in second step and the 3rd step be optimized, to obtain the shortest critical path, target is in the complete realization of arithmetic encoder, under the storehouse of the TSMC of .25, under Synopsys DC comprehensive, can reach 200M.

The present invention is the pipeline synchronization VLSI implementation method of the arithmetic encoder among a kind of JPEG2000, has realized 1 input of 1 clock coding of arithmetic encoder, and has provided the structural design and the Key Circuit that realize.

Description of drawings

Fig. 1 is the figure that underdraws of traditional arithmetic encoder flow process;

Fig. 2 is the key diagram of step3 in the arithmetic coding flow process;

Fig. 3 is that step3 is converted into 3 step pipeline organization figure;

Fig. 4 is the process flow diagram of stage2;

Fig. 5 is the streamline main critical path figure in the 3rd step;

Fig. 6 is that the implementation algorithm level of byteout is optimized process flow diagram.

Embodiment

The present invention is described in further detail below in conjunction with embodiment that accompanying drawing and inventor provide.

The process description of the arithmetic encoder of JPEG2000:

Step1:INITENC: the register that calls during initialization codes

Step2: read in CX (context labe1), D (0,1)

Step3: coding (ENCODE) needs to introduce RENORME in coding.

The CODEMPS condition:

((D＝0)&(MPS(CX)＝0))||((D＝1)&(MPS(CX)＝1))

The CODELPS condition:

((D＝1)&(MpS(CX)＝0))||((D＝0)&(MPS(CX)＝1))

Step4:FLUSH after the end-of-encode exports the data in REGC and the buffer memory.

The flow process of step3 when A＜0X8000H, needs move to left with normalization to A as shown in Figure 2, so that A＞=0X8000H is 0 o'clock at CT simultaneously, encoding code stream exports (byteout) in the buffer memory to.As seen, a complete cataloged procedure needs 4 clock period at least, as need normalization, then need 5,6 clocks in addition,, then will add one to two clock if add byteout, if n group (cx, d) is encoded, because being serial, this realizes, on average need 6*n clock.

The objective of the invention is to overcome the renewal and the RENORME flow process institute interrupt flow waterline of CX table, arithmetic coding can be realized by flowing water in step3.The present invention is described in more detail below in conjunction with drawings and Examples, but Key Circuit of the present invention and method are not limited to this embodiment, can adapt to other arithmetic encoders.

According to technical scheme of the present invention, the inventor has provided embodiments of the invention.What use in the present embodiment is MQ arithmetic encoder flow process in the JPEG2000 standard, three step pipeline organizations have been adopted, arithmetic coding can be realized by flowing water, promptly CX, the D to continuous input imports, can carry out continuous coding to it, thereby obtain continuous output, then only need N+3 clock just can finish the coding that the N group is imported, when the N value is enough big, can finish input of a clock.

Yet, realize that the flowing water of arithmetic coding realizes that following problem becomes the key of realization:

At first be that CX table is not unalterable, it is that result according to a last coding upgrades, like this next group (CX, D) input the time, last more new construction is output also, this moment, computation of table lookup can be made mistakes;

Next is the byteout operation, be not that each coding all will carry out, so CODEMPS and CODELPS coding, normalization even byteout operation in addition sometimes, this all will finish in 2 clocks, need carry out some variations and handle and to realize processing procedure, these problems are discussed respectively below.

1.Qe obtaining of table index:

In the process of arithmetic coding, can the CX table correctly upgrade timely, be the necessary condition of correct coding, by Fig. 3, we as can be seen, the renewal of CX table can only occur in the 3rd clock, so in 3 continuous CX,, upgrade the CX table again at the 3rd clock so and do not influence the inquiry of importing later if CX two neither waits, but if equal situation is arranged, the CX table index value that obtains of tabling look-up when also not upgrading is just incorrect.

In the pipeline organization of arithmetic coding, because the content of CX table is unimportant, participate in the just qe value of computing, as long as can obtain correct index value continuously, and then obtain correct qe value continuously, need not then to consider whether the CX table upgrades.So, when CX table two neither waits, index is the result who tables look-up and obtain, when two continuous CX equate, index is not equal to the index value of CX, but used TYPE (type of coding) directly selects the value of index=nmps, nlps or a last index according to last CX coding the time, if at interval one equate that the 3rd index just directly equals nmps, the nlps or the index that are drawn by first cx so.Describe the value (for convenience of explanation, add n, n+1, the n+2 footmark is represented time sequencing in practice) of index below in detail:

Suppose at CLK _nThe time be input as CX _n(CX ₁～CX _nDo not equate continuously), use CX _N-1_ reg1 represents CX _N-1The value of a clock of time-delay;

At CLK _N+1The time be input as CX _N+1(suppose CX _N+1=CX _n), INDEX1 _nProduce and (be the output valve INDEX0 of inquiry CX table _n); This moment CX _n_ reg1 (CX _nValue time-delay one-level) is not equal to CX _N-1_ reg2 (CX _N-1_ reg1 value time-delay one-level), Ci Shi INDEX then _nThe INDEX1 that draws for tabling look-up _nTherefore can be by INDEX _nInquiry qe table obtains correct output: NMPS _n, NLPS _n, SWITCH _n, Qe _n

CLK _N+2Clock be input as CX _N+2(suppose CX _N+2=CX _N+1And CX _N+2=CX _n), and this is constantly, is input as CX last time _N+1The time, INDEX1 _N+1Output valve INDEX0 for inquiry CX table _N+1, so the time CX table upgrade the INDEX1 of this moment _N+1It is not actual required index value; This moment is because CX _N+1_ reg1 (CX _N+1Value is deposited one-level) equal CX _n_ reg2 (CX _n_ reg1 value is deposited one-level), be that CODEMPS coding or CODELPS coding can be selected input n+1 INDEX constantly then according to the n time type of coding _N+1Value be NMPS _n_ reg1, NLPS _n_ reg1 or INDEX _nAmong _ the reg1 one; Again by INDEX _N+1Inquiry qe table output: NMPS _N+1, NLPS _N+1, SWITCH _N+1, Qe _N+1CLK _N+3Clock be input as CX _N+3Can be that CODEMPS coding or CODELPS coding can be selected input n+2 INDEX constantly equally according to the n+1 time type of coding _N+2Value be NMPS _N+1_ reg1, NLPS _N+1_ reg1 or INDEX _N+1Among _ the reg1 one; Again can be by INDEX _N+2Inquiry qe table output: NMPS _N+2, NLPS _N+2, SWITCH _N+2, Qe _N+2

……

And the like, can handle the input that the CX value of continuous input equates, repeat no more for equal situation at interval, detailed index inquires about that more new logic is as follows:

Situation if (CODEMPS) the begin if that always@ (posedge clk) if (cx==cx_reg2) // CX in the interval equates (index1＜=index_reg1 of a-qe＞=0X8000); Else index1＜=nmps_reg1; End else index1＜=nlps_reg1; Else index1＜=index0; Situation if (CODEMPS) if that always@ (responsive variable is all) if (cx_reg1==cx_reg2) // continuous two CX equate (index=index_reg1 of a-qe＞=0X8000); Else index=nmps_reg1; Else index=nlps_reg1; Else index=index1;

[notes]: index0 looks into the index value that the CX table draws,

Be DFF in the index1 reality, INDEX is WIRE type variable in practice.

2.REGA 0 testing circuit

In stage2 (streamline the 2nd step), after A upgrades, A is moved to left, so that A＞=8000H, needs the figure place shiftbit[3..0 that moves to left of definite REGA for this reason in this stage], move to left again.

Be the false code of its gate level circuit below:

if(A15|A14|…..|A8)＝1

shiftbit[3]＝0；

else shiftbit[3]＝1；

if((A15|A14|A13|A12)＝1)&(shiftbit[3]＝0)

shiftbit[2]＝0

else?if(A7|A6|A5|A4＝1)||(shiftbit[3]＝1)

shiftbit[2]＝0

else shiftbit[2]＝1

Be divided into for four steps, be equivalent to the tree-shaped search of y-bend and determine the figure place that moves to left, the time-delay of the composite door when obtaining shiftbit is shorter relatively like this.

3.C fractionation

28 C is split into C[19:0] and C[27:20], at CLK3: input Qe,, (1 is CODEMPS to TYPE, 0 is CODELPS), output C[19:0], A, here, REGC[19:0] the same computing and the shifting function of all having finished with Qe with A, enter computing next time as correct output.

And low 20 carry digits that obtain with the Qe addition of the most-significant byte of C and C only participate in the byteout computing, can carry out computing at next clock.

4: the main critical path in the 3rd step of streamline

In the 3rd step of the streamline of arithmetic encoder, except will doing CODEMPS (or CODELPS) coding, (normalization) and the byteout operation that also will move to left is because may run into the situation of double byteout.Make like this and must be optimized the critical path lengthening critical path.

Import the most-significant byte of REGC in the 3rd step of streamline, low 20 carry digit CARRY that obtain with the Qe addition with C, CT and SHIFTBIT are earlier relatively with definite figure place that moves to left for the first time, if do not need to carry out the BYTEOUT first time, directly obtain the most-significant byte of the required new C of next step operation, otherwise carry out the BYTEOUT first time, judge quadratic B YTEOUT process again, result according to twice BYTEOUT carries out the shift left operation second time more at last, to obtain the most-significant byte of the required new C of next step operation, while output encoder byte in the BYTEOUT process, as shown in Figure 5.

5. the processing of detailed byteout

In the streamline of arithmetic encoder was realized, that the most complicated had been normalization and byteout, because may run into the situation of twice of continuous byteout.Though byteout can carry out outside streamline, normalization must be finished in a clock, and its process of byteout can change the value of CT, C, will influence the normal operation of streamline.

At type=0 (CODEMPS coding), the agreement regulation does not need to carry out the normalization operation when a-qe＞=0X8000, in fact calculated shiftbit=0 this moment, can regard shiftbit as and be 0 normalization operation, only the value before and after the normalization is constant, therefore is included into the situation unification of shiftbit＜CT and carries out the normalization operation.Operation (appendix 1 is seen in variable declaration) when needing normalization is discussed respectively below:

● at this moment shiftbit＜CT only needs normalization, and need not carry out byteout tempct=ct-shiftbit at this moment

● shiftbit＞=CT, at this moment not only need normalization, and will carry out the byteout operation and carry out the normalization first time earlier, c is moved the ct position earlier, carry out the byteout operation, draw tempc1, the tempct1 (8 or 7) that obtain behind the byteout first time

Normalization this moment is not also finished, and the figure place that also needs to move is (shiftbit-CT)

If ● (shiftbit-CT)＜and tempct1, tempct=tempct1+ct-shiftbit need not to carry out the byteout second time so

If ● (shiftbit-CT)＞tempct1, also need to carry out the second time byteout tempc1 is moved the tempct1 position earlier, obtain tempc2, carry out the byteout operation, draw second

Tempc3 behind the inferior byteout, tempct2 (8 or 7)

Tempct=tempct2+tempct1+ct-shiftbit so

Detailed flow process is seen Fig. 4.

Five optimization work

1. second of the streamline step was optimized, as shown in Figure 4

Have 16 subtractions (A=A-Qe) of serial by former flow process, 16 bit comparators (A, Qe) and 16 additions (C=C+Qe (I (CX))), become the constraint of design in the time after, change the serial flow process into parallel flow process as far as possible.

Amended flow process can be as follows:

1 ^st?op(operation)：A＝A-Qe A1＝A-2Qe C1＝C+Qe

2 ^NdOp: according to coding process selecting A value (A2) and C value (C2)

3 ^RdOp: the figure place that moves to left is determined

4 ^ThOp: A2 and C2 simultaneously move to left

Wherein whether carry out the size comparison of A-Qe and Qe with the high position generation borrow of A1, make A1 and A executed in parallel, critical path greatly shortens like this.

2. Yi Wei operation

Streamline second is in the step, and the operation of execution is many, and in order to improve travelling speed, the output that adds shiftbit is to occur successively by the order of a high position to low level, so when being shifted, can carry out respectively according to each of shiftbit.

Cltemp＝C2<<shiftbit[3]

c2temp＝cltemp<<shiftbit[2]

c3temp＝c2temp<<shiftbit[1]

C3＝c3temp<<shiftbit[0]

Move to left so successively, cltemp wherein, c2temp, c3temp are intermediate variable, "＜＜" realize in this MUX with alternative.

3. the simplification of logic

In fact the value of a only might be for qe or (a-qe), and the arithmetic logic on the agreement is carried out abbreviation, can obtain following code

if((type＝＝0&&a_sub_2qe[16]＝＝0)||(type＝＝1&&a_sub_2qe[16]＝＝1))

a1＝qe；

else a1＝a_sub_qe；

[notes] a_sub_2qe={1 ' b1, a}-2*qe, a_sub_2qe[16] be equivalent to the big or small comparative result of a-qe and qe.

Variable or symbolic significance used in the literary composition illustrate:

The probability interval that A A is current

B B packed data buffer memory output byte

The BYTEOUT arithmetic coding export caching to, detailed process is seen agreement

Will carry out the C value of BYTEOUT for the first time after the BYTEOUTC normalization for the first time

C CT shift counter

CX is that context is that calculate and the context D correspondence

CODEMPS MPS type of coding

CODELPS LPS type of coding

D D D is the data after layered encoded

DFF

E

The end operation of F FLUSH arithmetic coding, detailed process is seen agreement

G

H

The index value of I index probability tables

The initialization operation of INITENC arithmetic coding, detailed process is seen agreement

J

K

L

M MPS is used for the judgement of contextual big probability

MQ

The index value of the next MPS of N NMPS

The index value of the next LPS of NLPS

O

P

Q QE probability

The normalization operation of R RENORME arithmetic coding, detailed process is seen agreement

The end operation of S SETBITS arithmetic coding, detailed process is seen agreement

The sign of SWITCH index value

The figure place that moves to left of SHIFTBIT A

T TYPE presentation code type, 0 is CODEMPS, 1 is CODELPS

TEMPC calculates the intermediate variable of C

The new C value that TEMPC1 draws behind the BYTEOUT for the first time

Will carry out the C value of BYTEOUT for the second time after the TEMPC2 normalization for the first time

The new C value that TEMPC3 draws behind the BYTEOUT for the second time

TEMPCT calculates the intermediate variable of CT

The new CT value that TEMPCT1 draws behind the BYTEOUT for the first time

The new CT value that TEMPCT2 draws behind the BYTEOUT for the second time

Claims (1)

1. the VLSI implementation method of a synchronous flowing water arithmetic encoder comprises structural design and wherein Key Circuit design, carries out according to the following steps:

1) at first the flow process of the arithmetic encoder in the JPEG2000 agreement is converted into three step streamline and supporting processes, the whole flow process of arithmetic encoder is divided into four operations by implementation procedure:

The inquiry of the first step: CX table, the reading of the inquiry of Qe table and qe value;

Second step: low 20 renewals of the renewal of register A, register C and the renewal of CX table;

The 3rd step: the renewal of register C and byte output;

Supporting process: to finish last byte output;

2) second step and the 3rd in the three step streamlines is gone on foot the optimization that proposes algorithm level

Second of streamline mainly comprises 4 sequential operation step by step suddenly:

First is operating as three parallel methods that add deduct: A-Qe, A-2Qe, C+Qe;

Second operation from A-Qe, selected A value according to the coding flow process among the Qe, selection C value from C+Qe and C,

The 3rd operation: utilize 4) the first nonzero digit testing circuit of the register A that proposes in is determined the figure place that moves to left

The 4th operation: utilize this figure place that moves to left that A and C are done to move to left and obtain new A and C,, during arrival, upgrade the value of register A and C with new A and C on a clock edge.

The 3rd of streamline finally turns to following sequential operation step by step suddenly:

The most-significant byte of operation 1:C and the carry digit addition in second step, and the lt figure place is definite arbitrarily for the first time;

Operation 2: for the first time any lt;

Operation 3: byteout for the first time;

Operation 4: byteout for the second time;

Operation 5: for the second time any lt;

The logic of choosing of the Qe table index under 3) CX imports arbitrarily is as follows:

If n, n+1, n+2 represent the time-angle table of the streamline under continuous 3 input CX respectively:

Work as CX _n≠ CX _N+1≠ CX _N+2The time

Index _n, index _N+1, index _N+2Be followed successively by the index as a result that inquiry CX table obtains ₀

As CXn=CXn+1 ≠ CXn+2,

Index _N+1Be not equal to the index that inquiry obtains ₀, but according to TYPE _nBe type of coding and A _n-qe _nValue at nmps (index _n), nips (index _n), index _nOne of middle selection;

When CXn=CXn+1=CXn+2,

Index then _N+2Be not equal to the index that inquiry obtains ₀, but according to TYPE _N+1Be type of coding and A _N+1-qe _N+1Value at nmps (index _N+1), nlps (index _N+1), index _N+1One of middle selection;

As (CXn=CXn+2) ≠ CXn+1,

Index then _N+2Remain according to TYPE _nBe type of coding and A _n-qe _nValue at nmps (index _n), nlps (index _n), index _nOne of middle selection;

4) a kind of first nonzero digit testing circuit that uses the register A of combinational logic realization is proposed, with the realization in second step of accelerating flow waterline;

5) second step and the 3rd step are adopted critical path optimization

The method of its optimization is as follows:

[1] Yi Wei operation

Suppose that shiftbit is the figure place that need move to left, C2 is the number that need move to left, and when the output order of shiftbit, its stable order in combinational circuit inside is C2＞shiftbit[3]＞...＞shiftbit[0], then move to left in the following manner, fastest:

C3＝(((C2＜＜shiftbit[3])＜＜shiftbit[2])＜＜shiftbit[1])＜＜shiftbit[0]

"＜＜" realize in this MUX with alternative;

[2] work as a_sub_2qe={1 ' b1, a}-2*qe uses a_sub_2qe[16] judge the big or small comparative result of a-qe and qe;

[3] C is split into C[19:0] and C[27:20]

Wherein the optimization of design of structural design and Key Circuit and critical path is as a whole, and purpose is in order to guarantee to be implemented in N input of coding in N+3 the clock, and the work clock of the circuit after the concrete optimization under .25um technology is the requirement of 200M.

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