CN1561060A - Threshold setting method of first-in first-out buffer - Google Patents
Threshold setting method of first-in first-out buffer Download PDFInfo
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- CN1561060A CN1561060A CNA2004100061834A CN200410006183A CN1561060A CN 1561060 A CN1561060 A CN 1561060A CN A2004100061834 A CNA2004100061834 A CN A2004100061834A CN 200410006183 A CN200410006183 A CN 200410006183A CN 1561060 A CN1561060 A CN 1561060A
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Abstract
This invention discloses a threshold value set method for a first-in, first-out buffer including: 1, dividing the FIFO into three parts of actual application part, attached buffer part and a forbidden part, 2, when data flow is less, FIFO only uses the actual part to buffer-store data packets, when it is large, it also uses the attached part to store data packets, 3 the state of the actual applied part in FIFO is indicated to an external interface, the state of both the actual applied part and attached buffer part is indicated to an internal interface. This invention solves the problem of data packet loss resulted from non-matched signals between network processor and interface chips.
Description
Technical field
The present invention relates to computer and communication system, relate in particular to the Signal Matching between network processing unit and the interface chip and the method for control.
Background technology
Along with the development of mechanics of communication, the data traffic on the Internet (Internet) becomes geometric growth, develops into present 10Gbps rate interface by original 64Kbps rate interface.Processing for high-speed data-flow, traditional universal communication CPU has too many difficulties to cope with, do not satisfy user's performance requirement, under these circumstances, network processing unit also just becomes the developing inevitable outcome of data communication, and Fig. 1 is exactly network processing unit and an interface chip typical case connection diagram in the data communication system.
In order to adapt to the different demands of complex network environment, present nearly all network of network processor all adopts the achieve a butt joint processing of mouthful state information of the method based on software microcode (microCode), though this method has very big advantage aspect flexibility, also brought the problem of flow matches between network processing unit and the interface chip simultaneously.Because the time ductility of software is difficult to satisfy the requirement of hardware signal, though have only short several microseconds to network processing unit by the time that software sends the operation of corresponding transceive data bag such as the state of network processing unit by software fetch interface chip from it self status register, but well beyond the nanosecond delay requirement of hardware, in other words, the state information of the interface chip that network processing unit is read has not been the current state information of interface chip, but the state information before the interface chip, because the used interface message of network processing unit does not reflect the state that interface chip is current in real time, so the serious consequence that network processing unit sends the transmitting-receiving operation of packet based on the interface status information of reading is exactly losing of packet or mistake, can occur simultaneously when network processing unit when interface chip is sent out packet, perhaps interface is in full load condition at this moment, cause data-bag lost, perhaps when network processing unit when interface is received packet, interface chip does not but have data at this moment, what receive is the situation of invalid data, produces error in data.
In sum, existing based on software fetch interface state information network processing unit and interface chip between have the problem of Signal Matching, be easy to cause losing or mistake of packet between network processing unit and the interface.
Summary of the invention
The objective of the invention is to solve in the prior art the data-bag lost or the Problem-Error that do not match and caused, and then propose the threshold setting method of first in first out in a kind of interface chip (FIFO) buffer based on signal between the network processing unit of software fetch interface state information and the interface chip.
The method of the invention may further comprise the steps:
Step 1: whole FIFO is divided into actual use partial L 1 or L1 ', additional cushion partial L 2 or L2 ', bans use of three parts such as partial L 3 or L3 ' on version;
Step 2: under the less situation of data traffic, FIFO only utilizes actual use partial L 1 or L1 ' to come data cached bag, and when data traffic is big, FIFO can also utilize additional cushion partial L 2 or L2 ' to come data cached bag except that utilizing actual partial L 1 or the L1 ' of using to come the data cached bag;
Step 3: the full state of sky of actual use partial L 1 among the whole FIFO or L1 ' is indicated to external interface;
Step 4: the full state of the actual sky that uses partial L 1 or L1 ', additional cushion partial L 2 or two parts of L2 ' to lump together among the FIFO is indicated to internal interface.
Compared with prior art, the present invention is owing to adopt the method that FIFO is cut apart, reserving the part of FIFO uses to internal interface, realize the circular in advance of interface message, solve between network processing unit and the interface chip because the data-bag lost or the Problem-Error that do not match and caused of signal, make the inventive method realize that cost is low, implementation method is simple, can be applicable in the design of all interface chips that dock with network processing unit.
Description of drawings
Fig. 1 is a connection layout between network processing unit and interface chip in the available data communication system.
Fig. 2 is the flow chart of the method for the invention.
Fig. 3 is a transmitter side FIFO organigram of the present invention.
Fig. 4 is L1 of the present invention transmitter side FIFO schematic diagram when full.
Fig. 5 is L1 of the present invention, L2 transmitter side FIFO schematic diagram when full.
Fig. 6 is a receiver side FIFO organigram of the present invention.
Fig. 7 is L1 ' of the present invention receiver side FIFO schematic diagram when full.
Fig. 8 is L1 ' of the present invention, L2 ' receiver side FIFO schematic diagram when full.
Embodiment
The present invention relates to the design of interface chip in communication or the computer system, and the method for Signal Matching between network processing unit and the interface chip and control.Proposed the method handled by docking port chip FIFO, reached between network processing unit and the interface packet and do not lose purpose.
Basic thought of the present invention is to utilize the memory space of FIFO showing inconsistent characteristics realization to internal interface with to external interface, concrete thinking is as follows: the memory space of transmitter side and receiver side FIFO shows relative smallerly to external interface, shows greatly relatively to internal interface.Network processing unit is after the external interface signals that has obtained transmitter side, even without upgrading, promptly also send data to interface, but owing to report the transmitter side FIFO memory space that interface signal showed of network processing unit is not real transmitter side FIFO memory space, even that is to say that network processing unit writes data in a small amount again toward transmitter side FIFO and also can not lose.In like manner, network processing unit sends the reception order even without having enough time after the external signal that has obtained receiver side, and receiver side FIFO can also continue to hold data in a small amount and not lose.
As described in Figure 2, the method for the invention is summarized as follows:
Step 1: whole FIFO is divided into actual use partial L 1 or L1 ', additional cushion partial L 2 or L2 ', bans use of three parts such as partial L 3 or L3 ', as Fig. 2 and shown in Figure 5 on version;
Step 2: under the less situation of data traffic, FIFO only utilizes actual use partial L 1 or L1 ' to come data cached bag, and when data traffic is big, FIFO comes the data cached bag except utilizing actual use partial L 1 or L1 ', can also utilize additional cushion partial L 2 or L2 ' to come data cached bag;
Step 3: the full state of sky of the actual use partial L 1 among the whole FIFO is indicated to external interface;
Step 4: the full state of the wherein actual sky that uses partial L 1 or L1 ', additional cushion partial L 2 or two parts of L2 ' to lump together is indicated to internal interface.
Specifically, realize that the technical program is as described below:
According to different transmitter side and the receiver side FIFO that determine appropriate depth in concrete application scenario.The Ethernet data bag selects for use above transmitter side of 3000 bytes and receiver side FIFO just can meet the demands less than 1500 bytes in the Ethernet application scenario at present.
Transmitter side FIFO is divided into 3 parts, as shown in Figure 3, be L1, L2, L3, when system powers on, there are not data among the transmitter side FIFO, be that L1, L2, L3 state are sky, external_empty (outside fifo empty signal is given in indication) signal and internal_empty (indication is to the fifo empty signal of internal interface) signal are height.
The full degree of the sky of L1 is given network processing unit by the external_empty signal reporting, when promptly the data of being write in transmitter side FIFO when network processing unit surpass the represented degree of depth of L1, as shown in Figure 4, the external_empty signal changes, when powering on such as system, the L1 state is empty, the external_empty signal is high, the expression network processing unit can send data in transmitter side FIFO, when data are filled up L1, external_empty signal step-down, the current transmitter side FIFO of informing network processor is in full state, can not receive data again.
When data are filled up L1, though the current transmitter side FIFO of external_empty signalisation network processing unit be in full state the time, but because network processing unit is based on software fetch interface state information, the state network processor of current transmitter side FIFO does not upgrade in time, network processing unit also can continue to send data probably in transmitter side FIFO, if at this moment transmitter side FIFO does not have the space, promptly transmitter side FIFO only is made of L1, and the data of transmission will be lost.In order not lose the network processing unit data that continuation sends under the full state of L1, internal interface sampling internal_empty signal, be that internal interface continues to receive the data that network processing unit sends under the full state of L1, and be written among the L2, as shown in Figure 5.
Because most of network processing unit is based on pack mode sampling external_empty signal, it is once sampling external_empty signal, send a complete packet, continue the packet that sends down in order not lose the full state of network processing unit L1, the length of the long data bag that requires promptly that the degree of depth of L2 can hold that next network processing unit sends.Such as in Ethernet is used, the degree of depth that requires L2 is more than or equal to 1500 bytes.
Equally, receiver side FIFO is divided into 3 parts, as shown in Figure 6, be L1 ', L2 ', L3 ', when system powers on, do not have data among the receiver side FIFO, promptly L1 ', L2 ', L3 ' state are empty, and external_full (indication gives outside FIFO full signal) signal and internal_full (indication gives the FIFO of internal interface full signal) signal are low.The full degree of the sky of L1 ' is given network processing unit by the external_full signal reporting, and promptly when data among the receiver side FIFO during above the represented degree of depth of L1 ', the external_full signal changes, as shown in Figure 7.When powering on such as system, L1 ' state is empty, the external_full signal is low, there are not data will give network processing unit among the expression receiver side FIFO, when data are filled up L1 ', the external_full signal uprises, and the current receiver side FIFO of informing network processor is in full state, the order that network processing unit can sending/receiving data.
When data are filled up L1 ', though the current receiver side FIFO of external_full signalisation network processing unit be in full state the time, but because network processing unit is based on software fetch interface state information, the state network processor of current receiver side FIFO does not upgrade in time, the be not able to do in time order of sending/receiving data of network processing unit, if at this moment receiver side FIFO does not have the space, be that receiver side FIFO only is made of L1 ', the data of coming on the physical circuit have just been lost.For overcoming network processing unit also not loss of data that order caused of sending/receiving data under the full state of L1 ', internal interface sampling internal_full signal, be that internal interface continues to receive the data that physical circuit is brought under the full state of L1 ', and be written among the L2 ', as shown in Figure 8.
Claims (5)
1, a kind of threshold setting method of first-in first-out buffer is characterized in that, may further comprise the steps:
Step 1: whole first-in first-out buffer is divided into actual use part, additional cushion part, bans use of three parts such as part on version;
Step 2: under the less situation of data traffic, first-in first-out buffer only utilizes actual use part to come data cached bag, and when data traffic is big, first-in first-out buffer can also utilizes additional cushion partly to come data cached bag the data cached bag except utilizing actual use part;
Step 3: the actual full state of sky of part that uses in the whole first-in first-out buffer is indicated to external interface;
Step 4: the full state of the actual sky that uses part and additional cushion portion to lump together in two sub-sections in the first-in first-out buffer is indicated to internal interface.
2, the threshold setting method of first-in first-out buffer according to claim 1 is characterized in that, under the Ethernet application scenario, selects the above transmitter side of 3000 bytes and the first-in first-out buffer of receiver side for use.
3, the threshold setting method of first-in first-out buffer according to claim 1 is characterized in that, the length of the long data bag that the degree of depth of transmitter side additional cushion part can hold that next network processing unit sends.
4, the threshold setting method of first-in first-out buffer according to claim 1, it is characterized in that, when system powers on, there are not data in the first-in first-out buffer of transmitter side, reality is used part, additional cushion part and is banned use of partial status to be sky, and the indication of transmitter side is height for the first in first out buffering spacing wave of internal interface for the first in first out buffering spacing wave of internal interface and indication.
5, the threshold setting method of first-in first-out buffer according to claim 1, it is characterized in that, when system powers on, there are not data in the first-in first-out buffer of receiver side, actual use part, additional cushion part and ban use of partial status to be sky, the indication of receiver side expires signal for the full signal of first in first out buffering of internal interface and first in first out buffering that internal interface is given in indication to be low.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101034344B (en) * | 2007-04-12 | 2010-09-29 | 华为技术有限公司 | Threshold configuration method of first-in first-out memory, device and first-in first-out memory |
| CN101321038B (en) * | 2008-07-23 | 2010-12-08 | 杭州华三通信技术有限公司 | HDLC controller and HDLC controller report breaking method |
| CN101499245B (en) * | 2008-01-30 | 2011-11-16 | 安凯(广州)微电子技术有限公司 | Asynchronous first-in first-out memory, liquid crystal display controller and its control method |
| CN101520722B (en) * | 2008-02-27 | 2011-12-07 | 奇景光电股份有限公司 | Method for accessing a first-in-first-out (fifo) buffer and a fifo controller therefor |
| CN105518617A (en) * | 2015-08-07 | 2016-04-20 | 深圳市元征科技股份有限公司 | Caching data processing method and device |
-
2004
- 2004-03-05 CN CNA2004100061834A patent/CN1561060A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101034344B (en) * | 2007-04-12 | 2010-09-29 | 华为技术有限公司 | Threshold configuration method of first-in first-out memory, device and first-in first-out memory |
| CN101499245B (en) * | 2008-01-30 | 2011-11-16 | 安凯(广州)微电子技术有限公司 | Asynchronous first-in first-out memory, liquid crystal display controller and its control method |
| CN101520722B (en) * | 2008-02-27 | 2011-12-07 | 奇景光电股份有限公司 | Method for accessing a first-in-first-out (fifo) buffer and a fifo controller therefor |
| CN101321038B (en) * | 2008-07-23 | 2010-12-08 | 杭州华三通信技术有限公司 | HDLC controller and HDLC controller report breaking method |
| CN105518617A (en) * | 2015-08-07 | 2016-04-20 | 深圳市元征科技股份有限公司 | Caching data processing method and device |
| WO2017024430A1 (en) * | 2015-08-07 | 2017-02-16 | 深圳还是威健康科技有限公司 | Cached data processing method and device |
| CN105518617B (en) * | 2015-08-07 | 2019-08-02 | 深圳市元征科技股份有限公司 | Data cached processing method and processing device |
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