CN1558329A - Modular implement method for operating system of single-chip microcomputer - Google Patents
Modular implement method for operating system of single-chip microcomputer Download PDFInfo
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Abstract
The present invention relates to an implement method for operating system of single-chip microcomputer for controlling sub-system in a control system composed of a main control system and a sub-system, comprising steps of arranging system dispatch to achieve dispatch function of task, dispatching application process by message trigger, meantime achieve management operation of EMS memory buffer for storing message; arranging interrupt process to achieve interrupt process function, dispatching periodicity of the interrupt task during interrupt; arranging timing scan to achieve clock managing function to supply timing and timing cancel service for users; arranging message communication to achieve message communication during the process, and supplying communication between processes in sub-system and communication between processes in main system. The invention greatly reduces complex degree of sub-system, and separates completely the operation system and application program, which greatly improves efficiency of single-chip assembler system as multigrade system of sub-system control.
Description
Technical field
The present invention relates to communication automation system and control field, be specifically related to the implementation of operating system and application process in single-chip microcomputer compilation operating system.
Background technology
In the communications field, robotization and control field, the control of system often is divided into Multistage Control, and single-chip microcomputer for example the assemble system of 8031/8051 grade be commonly used for the control of subsystem, be used for handling work such as the single-plate grade subsystem.In 8031/8051 subsystem, whether its operating system and application structure arrangement have rationally play a part important for the security, the reliability that improve subsystem, also can reduce simultaneously the complexity of application programming, make that the realization of application program is simpler and easy, readable.
Existing 8031/8051 assemble system is gone back the ready-made operating system of neither one and is specifically designed to system's control.The control of whole subsystem is all finished by application program, and it will finish the function of all operations system on the one hand, finishes the function of application program on the other hand again, and both combine together fully.Such implementation has increased the complexity of system, also is unfavorable for the expansion and the application of system simultaneously.In the operating system of widespread usage 8031/8051 assemble system, have a plurality of subsystems, and each subsystem must be finished the complete operation system function of a cover as subsystem controls.As adopting in the switch system of 8031/8051 assemble system as subsystem controls at one, its subsystem types is a lot: user subsystem, dual-tone multifrequency subsystem, switching network subsystem, Multiple Frequency Control subsystem, trunk subsystem, test subsystems etc., on the one hand the application function that need finish of these subsystems is very complicated, on the other hand it again in the complete operation system clock control system, internal storage management system, message scheduling system and subsystem and master control system carry out functions such as message communication.If all these functions are finished by application program all, can make application program very complicated, be easy to make mistakes, also pretty troublesome to the expansion of subsystem simultaneously, subsystem of every increase or subsystem function all will adjust system architecture.Be difficult to for safeguarding also in addition, system is too complicated after all, and it is existing from operating system, has from application program again.
Summary of the invention
The object of the present invention is to provide a kind of modular implementation method of single-chip microcomputer operating system, be suitable for the independently operating system of all subsystems, the interface of standard is provided to application program simultaneously, the realization that makes application program only pay close attention to concrete application gets final product.
The object of the present invention is achieved like this:
The invention discloses a kind of modular implementation method of single-chip microcomputer operating system, the subsystem that is used for control system that master control system and subsystem are formed is controlled, and comprising:
The step of system call is set, and the scheduling feature that is used to finish the work is dispatched by the triggering application processes of message, finishes the management work of the core buffer of depositing message simultaneously;
The Interrupt Process step is set, is used to finish the Interrupt Process function, periodically produce interruption, in interrupting, interrupt task is carried out periodic scheduling by internal clocking;
The timing scan step is set, is used to finish the Clock management function, for the user provides regularly and the regularly service of cancellation;
The step of message communication is set, is used to finish the message communication between process, the communication between process and the communication between subsystem and master control system process in the subsystem are provided.
The described step that system call is set comprises: system environments is carried out initial work, and the district handles to clock data, dispatches according to message and process scheduling table application processes;
The described Interrupt Process step that is provided with comprises: preserve and interrupt environment, control table is dispatched task according to the interrupt task periodic scan, withdraws from the environment before recovering when interrupting to interrupt;
The described timing scan step that is provided with comprises: the setting of timer is carried out in control according to process, in each Interrupt Process, puts a scheduling sign simply; Before each scanning timing data district, check earlier whether this sign is put,, then this is indicated clear 0 and the timing data district carried out scan process as putting; Otherwise do not handle.
The described step that the message communication is set comprises: carry out communication between clock level task and main level process, communication is mutually carried out communication between subsystem and master control system process between the main level process;
Need at first during system handles to determine that the communication between process in the subsystem still is communication between subsystem and master control system process.
Described initial work comprises the preliminary examination setting that storehouse start address, interrupt timing system are set, the setting of registers group, the setting of system's control word, set up message scheduling formation, free memory administration queue, prepare packing formation, message bag transmit queue, initialization timing device data field.
The described clock data district is handled comprises: check whether timer regularly arrives, if produce timed message then for the process that timer is set.
Before described timed message is scheduled, check whether the proof test value in timer data district is identical with proof test value in the timer at that time.
Described dispatching process table, periodic scan control table, interrupt task dispatch list are stored in the storage space different with the operating system memory address.
Described system call comprises that also application process is finished, and described message is hung into idle queues, and restart the clock data district and handle.
It is the mode that adopts pop down that environment is interrupted in described preservation, and the registers group that preservation interrupt register, interrupt vector, main level operation are selected for use also need be switched registers group in addition, and reset break period, in order to the generation of interrupting next time.
Described periodic scan control table is made up of a plurality of bytes, a task of representing need to handle of a byte.
Described interrupt task comprises each interrupt scanning, need the task of scheduling in that byte of property dispatching cycle scan control table, the next task of then needing scheduling when interrupting arriving in the scan schedule table in the next byte is carried out round-robin scheduling to the periodic scan control table.
Describedly the timing data district is carried out scan process comprise that timer adds 1 operation, the process number that keeps in completely then according to the data field when timer value produces time exceeded message, and proof test value is brought in the message of generation in order to handling.
Communication between described clock level task and main level process is unidirectional communication modes, comprise: the memory field of a free time of system's application, in the data field, insert the process that to accept this message, the type of message of transmission, the length and the message content of message, and this message hung into the message scheduling formation, wait for that dispatching system sends to corresponding process with this message.
Mutual communication between described main level process is the both-way communication mode, comprise: the memory field of a free time of system's application, length and the message content of inserting the process of need accepting, transmission process, type of message, message in the data field copy in the message area, and apply for the memory field that another is new again, deposit the address of last message in the message content district, the address of current message is preserved as message content, send to the process place that is responsible for packing, unpacks as sending message.
Communication between described subsystem and master control system process is by the mode in serial communication or employing and outside shared drive district.
The mode in described and outside shared drive district comprises two parts:
The process of main level is handled, and is used for the message content that sends master control system is packed so that deposit more message at a packet; Accept the message that master control system is come, the message bag is unpacked, and send a message to the process of acceptance;
To the reading and writing in shared drive district operation, be used to finish and master control system between the message packets reliability transmission.
Described application process can be finished the transmission and the reception of the setting of timer and cancellation, message by the primitive that the call operation system provides.
The present invention has reduced the complexity of described subsystem, on function and structure operating system and application program is separated fully, has improved the efficient of widespread usage 8031/8051 assemble system such as single-chip microcomputer such as grade as the multilevel system of subsystem controls greatly.
Description of drawings
Fig. 1 is each system module synoptic diagram of the present invention;
Fig. 2 is the realization flow of dispatching system module of the present invention;
Fig. 3 is the realization flow of interrupt system module of the present invention;
Fig. 4 is the realization flow of timing system module of the present invention;
Fig. 5 is provided with flow process for timer in the timing system module of the present invention;
Fig. 6 is a timer cancellation flow process in the timing system module of the present invention;
Fig. 7 is the communication flow between clock level task and main level process in the communication system module of the present invention;
Fig. 8 be in the communication system module of the present invention in communication between the main level process and the subsystem with master control system in the communication flow of process;
The flow process that Fig. 9 packs and unpacks message for the present invention among Fig. 8.
Embodiment
At first introduce the realization principle of operating system in 8031/8051 assemble system, introduction offers the interface of application program application and the structure of application program then.
The step that relates among the figure is as follows:
The byte that step 32 finds the need of interrupt task dispatch list to handle prepares to handle the 0th position/task
Step 61 finds the data field of this timer according to timer
Step 62 is clear 0 with the timer value of this timer zone, and the check code of this timer is added 1
The memory field of step 71 free time of application
Step 72 is inserted the process that need accept this message, the type of message of transmission, the length and the message content of message in buffer area
This message of step 73 is hung into the message scheduling formation
Step 81 judges whether it is the interior message of subsystem
Process, transmission process, type of message, message-length will be accepted in the memory field of a free time of step 82 application, message content copy into
This message of step 83 is hung into the message scheduling formation
Free core of step 84 application will be accepted process, transmission process, type of message, message-length and message content and insert
Step 85 is applied for the memory field that another is new again, and the address of current message is preserved as message content, sends to the process place that is responsible for packing, unpacks as sending message
Step 91 is judged current type of message
Step 92 hangs message into preparation packing formation
Step 93 is judged the current packing that whether allows
Step 94 is put and is not allowed packing, and applies for a free core
Step 95 is taken out message from prepare the packing formation, and packs, and gives back core buffer
Step 96 judges whether bag is full
Step 97 judges whether prepare the packing formation is empty
Step 98 judges whether bag can load current message
Step 99 hangs packet into message bag transmit queue
Step 101 is unpacked the message bag, and hangs the message scheduling formation
Step 102 is judged the current packing that whether allows
Step 103 is put and is not allowed packing, and applies for a free core
Step 104 is taken out message from prepare the packing formation, and packs, and gives back core buffer
Step 105 judges whether bag is full
Step 106 judges whether prepare the packing formation is empty
Step 107 judges whether bag can load current message
Step 108 hangs packet into message bag transmit queue
One, the formation of operating system
Operating system is divided into the following aspects, sees Fig. 1: dispatching system 14, interrupt system 11, timing system 13, communication system 12, can introduce the realization principle of each system below in detail.
Difference instruction time that 8031/8051 assemble system is different, generally calculate according to the double-byte instruction execution time, each instruction is carried out needed for two nanoseconds, press ten milliseconds of calculating as Interrupt Process, promptly all interrupt task are handled and must be finished in ten milliseconds, that is to say and can carry out 5,000 instructions at most, must be fast as far as possible so use processing, the processing of operating system is also like this.Therefore, the realization of following each function of plane system need consider that all the efficient, particularly Interrupt Process carried out can not take too many duration.
1, dispatching system:
Processing to all programs in the system is divided into two priority levels: one is the process of processing messages, and its priority level is low, is referred to as the basic process 15 of application process, and it can be by the clock tasks interrupt of high priority; Another one is the program of handling in clock interrupts, and its priority level height is referred to as application process interrupt task 16, sees Fig. 1.
In 8031/8051 assemble system, the work that system is done comprises two aspects: on the one hand hardware is periodically scanned, scanning is obtained content handle and report master control system, accept the message that the master control system transmission is got off on the other hand, transmit the message to the application corresponding process and go to carry out.All data communications are adopted the processing mode of message transmission, and do not adopt the mode of sharing data area.To in the communication between the main level application process or all adopt the mode of message communication with the communication between the master control system process; And in Interrupt Process, the resulting information of the scanning hardware also mode by message sends to corresponding main level process and handles.
System call is at first carried out initial work to environment, this is comprising the setting of the preliminary examination setting that storehouse start address, interrupt timing system are set, registers group, the setting of system's control word, set up message scheduling formation, free memory administration queue, prepare packing formation, message bag transmit queue, initialization timing device data field, step 21.After initial work was finished, the district checked to timer data, and step 22 in order to find whether have timer to be timed to, if having, produces timed message then for the process that timer is set.Whether in message scheduling formation have message exist, if any then dispatching, need according to the corresponding process of process scheduling list scheduling, and this message is handled step 23 to application process by register transfer if checking subsequently.Also comprise judging whether this message is time exceeded message, step 24.After application process is finished, this message is hung into the free memory administration queue, and restart to scan timer data district, step 27.Before timed message dispatched, step 26 need be checked especially, check whether the proof test value of timer in the timer data district is identical with proof test value in the current timer, step 25 is in case the user had cancelled this timer again after message was hung the message scheduling formation during fastening.
In different subsystems, the application process difference of system call, therefore the process scheduling table is placed on operating system not at the program's memory space at same place, thereby make operating system have independence.
2, interrupt system:
In Interrupt Process, at first to preserve the interruption environment, step 31 makes when Interrupt Process finishes to withdraw from interruption, the processing before can proceeding to interrupt.The mode of pop down is adopted in the preservation of environment, the interruption environment of preserving comprises: the registers group that interrupt register, interrupt vector, main level operation are selected for use, also need switch registers group (promptly in Interrupt Process with during dispatching process is handled, adopting different registers group) in addition, and reset break period, in order to the generation of interrupting next time.
After above-mentioned environmental preparation is good, dispatch according to the periodic scan control table.The periodic scan control table is so a kind of table, and it is made up of a plurality of bytes, a task of representing need to handle of a byte, and having eight tasks like this can handle.Interrupt task dispatch list of corresponding existence can be dispatched these 8 tasks.Each interrupt scanning needs the task of scheduling in that byte of a property dispatching cycle scan control table, the next task of then needing scheduling when interrupting arriving in the scan schedule table in the next byte is carried out round-robin scheduling to the periodic scan control table.To each task handling is not all to need to dispatch at every turn, but according to the actual needs, the scheduling identification of each task in the his-and-hers watches, distinguish with " 0 " and " 1 ", a certain bit is " 0 ", then the pairing task of this bit need not scheduling in this interrupts, and is that the pairing task of bit of " 1 " then need be dispatched.Can control the dispatching cycle of different task so as required, as each interrupt schedule once, every an interrupt schedule once, every four interrupt schedule once, inferior every ten interrupt schedule one.
The periodic scan control table that interrupt task is handled can be following structure: the 76543210
| ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??1 | ??1 |
| ??0 | ??0 | ??0 | ??0 | ??0 | ??1 | ??0 | ??1 |
| ??0 | ??0 | ??0 | ??0 | ??1 | ??0 | ??0 | ??1 |
| ??0 | ??0 | ??0 | ??1 | ??0 | ??0 | ??0 | ??1 |
| ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??1 | ??1 |
| ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??1 |
| ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??1 |
| ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??1 |
| ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??1 | ??1 |
| ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??1 |
| ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??1 |
| ??0 | ??0 | ??0 | ??0 | ??0 | ??1 | ??0 | ??1 |
| ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??1 | ??1 |
| ??0 | ??0 | ??0 | ??1 | ??0 | ??0 | ??0 | ??1 |
| ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??1 |
| ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??0 | ??1 |
| ?0 | ?0 | ?0 | ?0 | ?0 | ?0 | ?1 | ?1 |
| ?0 | ?0 | ?0 | ?0 | ?0 | ?0 | ?0 | ?1 |
| ?0 | ?0 | ?0 | ?0 | ?0 | ?0 | ?0 | ?1 |
| ?0 | ?0 | ?0 | ?0 | ?0 | ?0 | ?0 | ?1 |
Be 20 bytes above, each byte has 8, and representative can be handled 8 clock level Interrupt Process tasks.Wherein:
The 0th each interruption of task all need be dispatched once;
The 1st per 4 interrupt schedule of task once;
The 2nd per 20 interrupt schedule of task once;
The 3rd per 10 interrupt schedule of task once;
The 4th per 20 interrupt schedule of task once;
Do not exist task 5 to task 7.
Before withdrawing from interruption, carry out opposite bullet stack according to the sequencing of pop down and handle, successively eject registers group, interrupt vector, interrupt register, switching and return original registers group, step 37.After all interrupt task dispose, need withdraw from interruption, step 38.Detailed process is seen Fig. 3.
Same because the different subsystem of periodic scan control table and interrupt task dispatch list and difference also is placed on different program's memory spaces with operating system, thus making to operate has independence.
3, timing system:
Adopt the mode of timing data district management to control, each timer is corresponding to fixing timing data district, and process need be carried out the setting of which timer and be controlled by process.Each timer data district has arranged following content: the timing setting value reserved area of two bytes, a byte also has a byte to be used for carrying out verification in order to write down the process number of setting timer.
When carrying out timing setting, number find corresponding timer data district according to timer, step 51 is noted the duration that the user sets, and notes current process number simultaneously.Subtract relatively difficulty of an operation because the byte method of operation of 8031 systems, system are carried out, therefore will put into timing setting value reserved area after the timing value negate, step 52 so that when scanning timer data district, is carried out and is added 1 operation and get final product, and sees Fig. 5.
Carrying out timing when operation cancellation, number finding corresponding timer data district according to timer, step 61, with the reserved area zero clearing of timing setting value, the proof test value with this timer data district adds 1 simultaneously, and step 62 is seen Fig. 6.
Should finish in interrupting on the detection principle in timer data district, because the periodicity of interrupting is secure, it is periodically to scan the timer data district, and the timer execution that is provided with is regularly added 1 operation, then produces time exceeded message when timer is full.And the scheduling in timer data district is here dispatched by dispatching system, is equally to dispatch once each interrupt cycle, and Interrupt Process is just at the mid-sign that need are dispatched the timer data district of each interruption.The purpose of doing like this is to carry out the required time in order to reduce interrupt task.Need all timer data districts of scanning, to not handling for the timer of " 0 " in the timing setting value reserved area; To not being that 0 timer adds 1 operation, completely then produce time exceeded message as timer value, and proof test value is brought in the message of generation in order to handling according to the process number that keeps in the data field.See Fig. 4.
4, communication system:
Because the mode of message-driven is adopted in the design of native system, so the communication between process is exactly a very important content.Communication between process is divided into following several: the communication between the communication between clock level task and main level process, the mutual communication between the main level process, subsystem and master control system process.Communication between clock level task and main level process is a kind of unidirectional communication, and clock level task can send message to the main level process, otherwise then not all right.Other two kinds of communications then are two-way.Communication between subsystem and master control system generally has dual mode, and a kind of is mode by serial communication, and another kind is the mode that adopts with outside shared drive district, and promptly subsystem writes data in the shared drive district, and master control system can read these data.And master control system can write data equally in this shared drive district, and subsystem reads.Design to process communication between subsystem and master control system describes with regard to the mode that adopts the shared drive district below.
The management of message area is divided into system region and user data area, and system region is used for the flow process of control messages, it comprise the process number of accepting message, the process number that sends message, transmission type of message, send the length of message.User data area then comprises the information that the user need send.
A kind of independent communication modes has been adopted in communication between clock level task and main level process, and it is brought into by the information that register will send.See Fig. 7, system at first applies for the memory field of a free time, step 71, in data buffer area, insert the process that to accept this message, the type of message of transmission, the length and the message content of message, step 72, and this message hung into the message scheduling formation, step 73 waits for that dispatching system sends to corresponding process with this message.
Another control mode has been adopted in the communication of process in mutual communication between the main level process and subsystem and the master control system.See Fig. 8, need at first during system handles to determine that the communication between process in the subsystem still is communication between subsystem and master control system process, step 81.If the communication in the subsystem, its processing is fairly simple, identical with clock level task with the communication between the main level process, system at first applies for the memory field of a free time, inserts the process number that need accept message, the process number that sends message, the type of message of transmission, the length of message in the data field, and message content is copied in the message area, step 82, and this message hung into the message scheduling formation, step 83 waits for that dispatching system sends to corresponding process with this message.
If the communication between subsystem and master control system, its processing more complicated.Communication modes in shared drive district mode describes.Its processing separated into two parts, a part are that the process of main level is handled, and it is responsible for need are sent to the message content of master control system and packs, so that can deposit more message in a packet; Accept the message that master control system is come, the message bag is unpacked, and send a message to the process of acceptance; On the one hand be reading and writing operation in addition to the shared drive district, it be responsible for finishing and master control system between the message packets reliability transmission, the realization of this part is finished in clock interrupts, and is the task of an interrupt level.
If message mails to master control system, at first free core of user applies is accepted needs process number, type of message, message-length and the message content of this message and is inserted step 84.
Because the process priority of main level is not identical, the length of the process holding time of be responsible for packing, unpacking can not have influence on the processing of consumer process., apply for a new memory field again here, the address of current message is preserved as message content, send to the process place that is responsible for packing, unpacks, step 85 as sending message.
At the process place that is responsible for packing, unpacks, at first check the content of message, step 91 is if send message, the then agreement of basis and master control system, to the message processing of packing, step 92--98 can squeeze into a plurality of message in the packet simultaneously, and hangs message bag transmit queue, step 99 is seen Fig. 9 left-half.If accept message, then packet is broken, the message that is split into is one by one hung into scheduling queue wait scheduling, and step 101--108 sees Fig. 9 right half part.
At the transmission of the clock level place that receives an assignment, adopt the moving window of 1 bit carry out packet transmission, accept control, packet in the message bag transmit queue is write in the shared drive district, read the data in the shared drive district simultaneously, this packet is sent to the process place that is responsible for packing, unpacks as accepting message after reading verification finishing, wait for the message processing of unpacking.
Two, the formation of application system
Because application process is to adopt the mode of message-driven to carry out work, that is to say which type of message has been accepted in which type of processing carries out.To Message Processing the time, can divide according to state of a process, promptly under specific state, only handle specific message, move to next state after Message Processing is intact, wait for the arrival of news again and handle, other message under this state is not handled.
Application process can be finished these function associated by the primitive that the call operation system provides, and these functions comprise the transmission of the setting of timer and cancellation, message and acceptance etc.The calling of these functions that system is provided realized by the address of directly calling relevant primitive.
8031/8051 assemble system provides the program memory space of 64K, by the compiling application program, can know the size of application program.Application program is arranged in different storage spaces, and operating system is directly called the address of storage space, thereby each application program is separated fully, compiles separately and debugs.
The transmission of the clock level place that receives an assignment adopts the moving window communications protocol of 1 bit to carry out the transmission of packet, accept control.Moving window communications protocol for 1 bit does not just describe in detail.Having only a bit needs explanation, after packet sends successfully, needs current permission packing sign is put.
The application processes calling system provides the mode of primitive, is to realize by the address of directly calling relevant primitive.
As shown in giving a definition:
SEND????????????EQU?????0050H
OUTPUT??????????EQU?????0053H
SET?????????????EQU?????0056H
RESET???????????EQU?????0059H
GETBUF??????????EQU?????005CH
Appropriate address place in operating system then does following processing:
ORG???????0050H
LJMP??????SEND
LJMP??????OUTPUT
LJMP??????SET
LJMP??????RESET
LJMP??????GETBUF
So, can compile separately and debug so that each application program is separated fully.
Claims (16)
1. the modular implementation method of a single-chip microcomputer operating system, the subsystem that is used for control system that master control system and subsystem are formed is controlled, and it is characterized in that, comprising:
The step of system call is set, and the scheduling feature that is used to finish the work is dispatched by the triggering application processes of message, finishes the management work of the core buffer of depositing message simultaneously;
The step of Interrupt Process is set, is used to finish the Interrupt Process function, periodically produce interruption, in interrupting, interrupt task is carried out periodic scheduling by internal clocking;
The step of timing scan is set, is used to finish the Clock management function, for the user provides regularly and the regularly service of cancellation;
The step of message communication is set, is used to finish the message communication between process, the communication between process and the communication between subsystem and master control system process in the subsystem are provided.
2. the modular implementation method of single-chip microcomputer operating system as claimed in claim 1 is characterized in that,
The step of described system call comprises: system environments is carried out initial work, and the district handles to clock data, dispatches according to message and process scheduling table application processes;
The step of described Interrupt Process comprises: preserve and interrupt environment, control table is dispatched task according to the interrupt task periodic scan, withdraws from the environment before recovering when interrupting to interrupt;
The step of described timing scan comprises: the setting of timer is carried out in control according to process, in each Interrupt Process, puts a scheduling sign; Before each scanning timing data district, check this sign earlier, and the timing data district is carried out scan process;
The step of described message communication comprises: carry out communication between clock level task and main level process, communication is mutually carried out communication between subsystem and master control system process between the main level process.
3. the modular implementation method of single-chip microcomputer operating system as claimed in claim 2, it is characterized in that, described initial work comprises the preliminary examination setting that storehouse start address, interrupt timing system are set, the setting of registers group, the setting of system's control word, set up message scheduling formation, free memory administration queue, prepare packing formation, message bag transmit queue, initialization timing device data field.
4. the modular implementation method of single-chip microcomputer operating system as claimed in claim 2 is characterized in that, the described clock data district is handled comprises: check whether timer regularly arrives, if produce timed message then for the process that timer is set.
5. the modular implementation method of single-chip microcomputer operating system as claimed in claim 4 is characterized in that, before described timed message is scheduled, checks whether the proof test value in timer data district is identical with proof test value in the timer at that time.
6. the modular implementation method of single-chip microcomputer operating system as claimed in claim 2 is characterized in that, described dispatching process table, periodic scan control table, interrupt task dispatch list are stored in the storage space different with the operating system memory address.
7. the modular implementation method of single-chip microcomputer operating system as claimed in claim 2 is characterized in that, described system call comprises that also application process is finished, and described message is hung into idle queues, and restart the clock data district and handle.
8. the modular implementation method of single-chip microcomputer operating system as claimed in claim 2, it is characterized in that, it is the mode that adopts pop down that environment is interrupted in described preservation, the registers group that preservation interrupt register, interrupt vector, main level operation are selected for use, also need switch registers group in addition, and reset break period, in order to the generation of interrupting next time.
9. as the modular implementation method of claim 2 or 6 described single-chip microcomputer operating systems, it is characterized in that described periodic scan control table is made up of a plurality of bytes, a task of representing need to handle of a byte.
10. as the modular implementation method of claim 2 or 6 described single-chip microcomputer operating systems, it is characterized in that, described interrupt task is meant each interrupt scanning, need the task of scheduling in that byte of property dispatching cycle scan control table, the next task of then needing scheduling when interrupting arriving in the scan schedule table in the next byte is carried out round-robin scheduling to the periodic scan control table.
11. the modular implementation method of single-chip microcomputer operating system as claimed in claim 2, it is characterized in that, described to the timing data district carry out scan process comprise timer add 1 the operation, the process number that keeps in completely then according to the data field when timer value produces time exceeded message, and proof test value is brought in the message of generation in order to handling.
12. the modular implementation method of single-chip microcomputer operating system as claimed in claim 2, it is characterized in that, communication between described clock level task and main level process is unidirectional communication modes, comprise: bring into by the information that register will send, the memory field of a free time of system's application, in the data field, insert the process number that to accept this message, the type of message of transmission, the length and the message content of message, and this message hung into the message scheduling formation, wait for that dispatching system sends to corresponding process with this message.
13. the modular implementation method of single-chip microcomputer operating system as claimed in claim 2, it is characterized in that, mutual communication between described main level process is the both-way communication mode, comprise: need at first during system handles to determine that the communication between process in the subsystem still is communication between subsystem and master control system process, if the communication in the subsystem, system at first applies for the memory field of a free time, in the data field, insert the process number that to accept message, send the process number of message, the type of message that sends, the length of message, and message content copied in the message area, and this message hung into the message scheduling formation, wait for that dispatching system sends to corresponding process with this message; If the communication between subsystem and master control system, the memory field of a free time of system's application then, length and the message content of inserting the process of need accepting, transmission process, type of message, message in the data field copy in the message area, and apply for the memory field that another is new again, deposit the address of last message in the message content district, the address of current message is preserved as message content, send to the process place that is responsible for packing, unpacks as sending message.
14. the modular implementation method of single-chip microcomputer operating system as claimed in claim 2 is characterized in that, the communication between described subsystem and master control system process is by the mode in serial communication mode or employing and outside shared drive district.
15. the modular implementation method of single-chip microcomputer operating system as claimed in claim 14 is characterized in that, the mode in described and outside shared drive district comprises:
The main level process is handled, and is used for the message content that sends master control system is packed so that deposit more message at a packet; Accept the message that master control system is come, the message bag is unpacked, and send a message to the process of acceptance;
To the reading and writing in shared drive district operation, be used to finish and master control system between the message packets reliability transmission.
16. the modular implementation method of single-chip microcomputer operating system as claimed in claim 2 is characterized in that, described application process can be finished the transmission and the reception of the setting of timer and cancellation, message by the primitive that the call operation system provides.
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| CN101276292B (en) * | 2008-05-13 | 2010-04-21 | 杭州华三通信技术有限公司 | Interrupt synthetic method and apparatus as well as modularization host computer system |
| CN101272564B (en) * | 2008-04-17 | 2011-05-11 | 中兴通讯股份有限公司 | Soft real-time timing device module and method for soft real-time timing device scheduling |
| CN101770392B (en) * | 2008-12-30 | 2012-07-25 | 上海贝岭股份有限公司 | High speed communicating method based on mu C/OS-II |
| CN102750149A (en) * | 2012-06-13 | 2012-10-24 | 普华基础软件股份有限公司 | Realization method and system of dispatch list |
| CN101826032B (en) * | 2009-03-06 | 2013-07-31 | 盈威力新能源科技(上海)有限公司 | High-efficiency real-time multi-task operating system kernel |
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| US5012409A (en) * | 1988-03-10 | 1991-04-30 | Fletcher Mitchell S | Operating system for a multi-tasking operating environment |
| GB2273591A (en) * | 1992-12-18 | 1994-06-22 | Network Systems Corp | Microcomputer control systems for interprogram communication and scheduling methods |
| KR100325386B1 (en) * | 1999-06-02 | 2002-03-04 | 서평원 | Signaling Connection Control Part Message Routing Method In No.7 Signaling Network |
| CN1215668C (en) * | 2001-03-30 | 2005-08-17 | 中兴通讯股份有限公司 | Multiple channel demodulation dispatching method |
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