CN1549318A - Semi conductor device packaging method - Google Patents

Semi conductor device packaging method Download PDF

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Publication number
CN1549318A
CN1549318A CNA031313485A CN03131348A CN1549318A CN 1549318 A CN1549318 A CN 1549318A CN A031313485 A CNA031313485 A CN A031313485A CN 03131348 A CN03131348 A CN 03131348A CN 1549318 A CN1549318 A CN 1549318A
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CN
China
Prior art keywords
substrate
semiconductor device
air pressure
packing method
semiconductor
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Granted
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CNA031313485A
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Chinese (zh)
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CN1258808C (en
Inventor
陈凯琪
李巡天
黄淑祯
李宗铭
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Industrial Technology Research Institute ITRI
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Industrial Technology Research Institute ITRI
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Priority to CNB031313485A priority Critical patent/CN1258808C/en
Publication of CN1549318A publication Critical patent/CN1549318A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

The present invention provides a packaging method of semiconductor device, applicable to a sealing process. Said method includes the following steps: providing a base plate with several semiconductor devices, the above-mentioned semiconductor device respectively contains a semiconductor chip respectively electrically-connected into a present sealing region on a surface of the above-mentioned base plate; under the first air pressure lower than one atmosphere using stencil printing process to make an excess sealing material be passed through the above-mentioned preset sealing region on the above-mentioned base plate so as to make the partial package material be filled into the above-mentioned preset sealing region; under the second air pressure greater than the above-mentioned first air pressure using stencil printing process to make the above-mentioned sealing material which is not filled into the above-mentioned base plate be passed through the above-mentioned sealing material filled into the above-mentioned base plate; under the third air pressure greater than one atmosphere hardening the above-mentioned sealing material.

Description

Semiconductor device packing method
Technical field
The present invention relates to a kind of semiconductor device packing method, the manufacturing method thereof of sealing in particularly a kind of semiconductor device packing method.
Background technology
Please refer to Figure 1A, is that demonstration one is covered the semiconductor device that crystalline substance (Flip Chip) encapsulation technology is made with tradition.Wherein substrate (substrate) 100a comprises a plurality of encapsulation unit 112a, can encapsulate a plurality of semiconductor devices.Shown in Figure 1A, so-called chip package is the technology that semiconductor chip 10a is engaged with substrate in active surface mode down.As substrate 100a is under the situation of organic substrate (organic substrate), because the thermal coefficient of expansion (CTE of organic substrate; Coefficient of thermal expansion) be about 14-17ppm/ ℃) for example excessive with semiconductor chip 10a for the CTE of silicon (being about 4ppm/ ℃) gap, when expanding with heat and contract with cold, the do not match stress that caused of CTE is easy to cause the formed contact of conductive projection 12a to damage.Therefore, for considering of reliability, usually need in the gap of substrate 100a and semiconductor chip 10a, insert primer (underfill) 120a, so that stress is dispersed to colloid, use and reduce the suffered stress of conductive projection 12a, so just, can reduce contact and break (crack), the extension that inhibition is broken, and the fatigue life of prolongation contact.In addition, primer 120a is a megohmite insulant, also can prevent to have between contact impurity to cause the transmission of leakage current.Data show, have the high 5-10 of its reliability (reliability) that the structure of wafer be adhered on substrate do not have a wafer be adhered on substrate doubly.Because primer can promote the reliability of joint effectively, therefore in flip chip assembly process, wafer be adhered on substrate is the processing procedure of can not ignore.Yet This is what people generally disapprove of the most for the filler processing procedure in that to produce speed low excessively, and the bottleneck major part that causes assembling production all occurs in the filler processing procedure.
Primer is inserted in liquid adhesive material utilization point glue (dispensing) mode mostly at present, its processing procedure at first will hang down stickiness liquid state colloid point on the semiconductor chip 10a next door that is attached on the substrate 100a, utilize liquid formed capillary pressure of fine pore (capillary pressure) between semiconductor chip 10a and substrate 10a to be permeated and fill up gap between conductive projection 12a as actuating force.The shortcoming of this processing procedure has following columns item: (1) filling is slow, under the driving of capillary pressure, loading time rough with square being directly proportional of distance, and decide filling on the sol temperature and take several minutes to tens minutes; (2) one groups of primer pad devices once can only be made a glue to single semiconductor chip 10a, if simultaneously two (containing) above semiconductor chip 10a is made a glue, certainly will will prepare many groups equipment, increase the burden of cost.
Please refer to Figure 1B, is to show a semiconductor device with the manufacturing of traditional wire bonds (wire bonding) encapsulation technology.Wherein substrate 100b comprises a plurality of encapsulation unit 112b, can encapsulate a plurality of semiconductor devices; Semiconductor chip 10b sticks together at each encapsulation unit 112b, with bonding wire 12b and substrate 100b electrically connect; Semiconductor chip 10b and bonding wire 12b cover with a packing colloid 120b.In addition, also substrate 100b can be replaced into the substrate (not illustrating) that a winding engages (tape automatic bonding) form automatically, replace bonding wire 12b with a lead (not illustrating), with semiconductor chip 10b electrically connect at drawing at drawing.
Except the chip package technology, when the packaged semiconductor devices of conventional package technology such as above-mentioned wire bonds or the automatic joint of winding being carried out sealing (molding) processing procedure with liquid adhesive material, though can make a glue and not have the problem that filling is slow and cost increases in the above-mentioned chip package technology two (containing) above semiconductor device simultaneously, do not have above-mentioned only complete filling primer and may be because of chip and the not good shortcoming of the relatively poor reliability that may cause of glue material interface adhesion in the slit below the chip and between base plate for packaging yet, but in the packing colloid 120b easily the problem of entrapped air pockets still can take place.
In addition, please refer to Fig. 1 C, is multi-chip module (the multi-chip module that shows the encapsulation of a chip stack (stack die) technology; MCM) semiconductor device.Wherein substrate 100c comprises a plurality of encapsulation unit 112c, can encapsulate a plurality of semiconductor devices; Semiconductor chip 10c sticks together at each encapsulation unit 112c, with conductive projection 12c and substrate 100c electrically connect; Semiconductor chip 10d stick together and storehouse on semiconductor chip 10c, with bonding wire 12d and substrate 100d electrically connect; Fill with primer 120c in the space with conductive projection 12c between substrate 100c and the semiconductor chip 10c; Semiconductor chip 10d, bonding wire 12d, cover with a packing colloid 120d with primer 120c.In addition, also substrate 100c can be replaced into a compound winding and engage automatically and the substrate (not illustrating) that covers crystalline form, replace bonding wire 12d with a lead (not illustrating), with semiconductor chip 10d electrically connect at drawing at drawing.
In the MCM semiconductor device shown in Fig. 1 C, cover brilliant and multiple encapsulation technologies such as wire bonds or winding engage automatically because of compound, its process complexity, process rate, and production reliability etc. face more acid test; Except will be simultaneously in the face of primer filling in the above-mentioned flip chip assembly process slowly, equipment cost, semiconductor chip engages with primer and problem such as bubble, the residual air bubble problem of packing colloid also can take place simultaneously in the encapsulation technologies such as the automatic joint of above-mentioned traditional wire bonds or winding; Adding packing colloid 120d and primer 120c also has the interface to exist, and both engagement problems become a factor that influences this semiconductor device process rate and production reliability again more.
The problem of easy entrapped air pockets (void) in the above-mentioned semiconductor device, existing many pieces of documents propose relevant solutions.For example at United States Patent (USP) the 5th, 834, No. 339 and the 6th, 107, in No. 123, disclose a kind of processing procedure (method) that utilizes pressure encapsulating material to be filled to chip and substrate gap: above-mentioned pressure be by etc. produce to gas pressure or by hydrostatic (hydrostatic pressure), and encapsulating material can be the mode of liquid some glue; Yet, above-mentioned processing procedure is a glue mode and can't improve the low shortcoming of throughput rate on package application, and this Technology Need has mould to go to control glue material flowing and cause extra fringe cost when pressurization, adds this technology and only can be used in the processing procedure of wafer be adhered on substrate.United States Patent (USP) the 6th for another example, 000, in No. 924, disclose the mould seal apparatus that encapsulation is filled in a kind of bottom, be that size particular design at the IC chip makes it can contain the whole packaging area of lid just, control again stroke that mould descends and pressure make this mould just capping chip top again simultaneously and possess certain clearance between substrate can be for bleed (with the extraction of the air in chip and the substrate gap), and utilize pressure that liquid state colloid is filled in this gap; Yet the said apparatus liquid mould envelope mode that is particular design and can't reach the general-using type encapsulation and require (need at the structure installing meter mould of different size and the manufacturing cost of mould is relatively costly), and can't utilize single mold simultaneously two (containing) above semiconductor device to be done sealing.And for example United States Patent (USP) the 6th, 187, in No. 613, disclose and a kind ofly utilize metallic film (plastic film) to cover on the chip and then the strength by this of exerting pressure thereon will be put encapsulating material bottom behind the glue and be filled in the processing procedure that covers in brilliant and the substrate gap, wherein above-mentioned metallic film (plastic film) thickness is 0.01mm～0.1mm, can bear the strength of 100psi; The low shortcoming of the speed of producing yet being still a glue encapsulation procedure basically, above-mentioned processing procedure is arranged, and what metallic film cost height and plastic film had deformation may influence the package dimension consistency, adds above-mentioned processing procedure and also can't utilize single mold simultaneously two (containing) above semiconductor device to be done sealing.
In addition, United States Patent (USP) the 6th, 187, in No. 613, disclose a kind of by vacuumize and subsequently more in addition high pressure make encapsulating material bottom behind the glue fill the processing procedure (method) of chip and substrate gap; Yet above-mentioned processing procedure is a glue mode and can't improve and produce the low shortcoming of speed on package application; And the very accurate point gum machine of this Technology Need point glue amount, otherwise the glue material might overflow; Or be need be at each chip design top closure, still manufacturing cost improves thus.For another example, United States Patent (USP) the 6th, 255 in No. 142, discloses and a kind ofly carries out a glue and vacuumize and utilize this pressure differential that sealing is filled to cover processing procedure in the gap of brilliant and substrate in the packaged type seal cavity, and above-mentioned pressure differential is to reach by vacuum environment; Yet above-mentioned processing procedure is still a glue encapsulation procedure basically and the low shortcoming of the speed of producing is arranged, and vacuum pressure reduction is only arranged is can't fully encapsulating material be filled into to cover in the intergranular crack, adds portable seal cavity and extremely is unfavorable for a large amount of continous way productions.And for example, United States Patent (USP) the 6th, 284, in No. 173, disclose and a kind ofly in the packaged type seal cavity, carry out a glue and vacuumize and utilize this pressure differential that sealing is filled to cover processing procedure in the gap of brilliant and substrate, above-mentioned pressure differential is to reach a kind of utilization by vacuum environment to carry out a glue under vacuum environment, this vacuum environment is returned to the processing procedure (method) that forces glue material packing IC assembly under the normal pressure again; Yet, above-mentioned processing procedure is still a glue encapsulation procedure basically and the low shortcoming of the speed of producing is arranged, and above-mentioned product speed and the some glue processing procedure that is applied in simultaneously two (containing) when above semiconductor device carries out sealing is all very slow and complicated, adds to return to the normal pressure way in the above-mentioned processing procedure and can't make the encapsulating material envelope completely cover crystalline substance and substrate gap.
Above-mentioned known techniques, all can't satisfy a kind of not only can be simultaneously to two (containing) above semiconductor device carry out manufacture procedure of adhesive, not only can avoid simultaneously in semiconductor device, producing bubble, also can be especially to the semiconductor device wafer be adhered on substrate of chip package the time but also can while capping entire chip, also be applicable to the demand that comprises the semiconductor device packing method of chip package in all interior encapsulation technologies.
Summary of the invention
In view of this, main purpose of the present invention provides a kind of semiconductor device packing method, can carry out manufacture procedure of adhesive to two (containing) above semiconductor device simultaneously, and can increase the output of above-mentioned semiconductor device, can save the equipment cost of above-mentioned manufacture procedure of adhesive again.
Another object of the present invention provides a kind of semiconductor device packing method, can carry out manufacture procedure of adhesive, can avoid in semiconductor device, producing simultaneously bubble again, two (containing) above semiconductor device simultaneously with encapsulation yield that promotes semiconductor device or reliability and the useful life that promotes the semiconductor device of institute's output.
Another purpose again of the present invention provides a kind of semiconductor device packing method, can be simultaneously to two (containing) above semiconductor device carry out manufacture procedure of adhesive, not only can avoid simultaneously in semiconductor device, producing bubble, also can be especially to the semiconductor device wafer be adhered on substrate of chip package the time but also can while capping entire chip, with the reliability and the useful life of the semiconductor device that promotes institute's output more.
Another purpose again of the present invention provides a kind of semiconductor device packing method, can carry out manufacture procedure of adhesive to two (containing) above semiconductor device simultaneously, simultaneously can avoid in semiconductor device, producing bubble again, also can be especially to the semiconductor device wafer be adhered on substrate of chip package the time entire chip of capping simultaneously again, also be applicable to the demand that comprises the semiconductor device packing method of chip package in all interior encapsulation technologies, more can save the equipment cost of above-mentioned manufacture procedure of adhesive, simplify above-mentioned manufacture procedure of adhesive, and the process rate of lifting semiconductor device, production reliability and useful life.
For reaching above-mentioned purpose of the present invention, the present invention provides a kind of semiconductor device packing method, is applicable to a manufacture procedure of adhesive, comprises the following steps:
One substrate is provided, and it has a plurality of semiconductor devices, and these semiconductor devices comprise the semiconductor chip respectively and are electrically connected at respectively in this substrate one lip-deep one predetermined adhesive area;
Be lower than under atmospheric first air pressure, with stencil methods (stencil printing) with on excessive inswept this substrate of adhesive material should predetermined adhesive area in, make this encapsulating material partly be filled on this substrate should predetermined adhesive area in;
Under second air pressure, will not be filled in this adhesive material on this substrate with stencil methods, on inswept this adhesive material that has been filled on this substrate greater than this first air pressure; And
Under greater than atmospheric the 3rd air pressure, this adhesive material hardens.
Wherein the mode of those semiconductor chips and this substrate electric connection is to electrically connect to cover crystal type and this substrate, and respectively have a space respectively between this semiconductor chip and this substrate, and in this space respectively, have and a plurality ofly electrically connect respectively this semiconductor chip and this substrate with a spaced conductive projection.
This adhesive material that wherein has been filled on this substrate is to cover these semiconductor chips fully.
Wherein this adhesive material more is filled in respectively this chip and the space of this substrate and the interval between these conductive projections.
Wherein be filled in the thickness of this adhesive material on this substrate, be not less than this space height and this semiconductor chip thickness sum.
Wherein this first air pressure is 0.1torr～10torr.
Wherein the 3rd air pressure is for being not more than 30kgf/cm 2
Wherein the 3rd air pressure is 3kgf/cm 2～15kgf/cm 2
The gas that the 3rd air pressure wherein is provided is to select certainly: dry air (dry air), nitrogen (N 2) or inert gas (inert gases).
The present invention also provides a kind of semiconductor device packing method, comprises the following steps:
One substrate and a plurality of semiconductor chip are provided, wherein have a predetermined adhesive area on the surface of this substrate, this predetermined adhesive area comprises a plurality of encapsulation units;
These semiconductor chips are placed respectively in the above-mentioned encapsulation unit, be electrically connected at this substrate respectively;
Be lower than under atmospheric first air pressure, with stencil methods (stencil printing) with on excessive inswept this substrate of adhesive material should predetermined adhesive area in, make this encapsulating material partly be filled on this substrate should predetermined adhesive area in;
Under second air pressure, will not be filled in this adhesive material on this substrate with stencil methods, on inswept this adhesive material that has been filled on this substrate greater than this first air pressure;
Under greater than atmospheric the 3rd air pressure, first section this adhesive material of sclerosis; And
With these encapsulation units is unit, and this substrate is divided into a plurality of semiconductor devices.
Wherein these semiconductor chips are to electrically connect to cover crystal type and this substrate, and respectively have a space respectively between this semiconductor chip and this substrate, and in this space respectively, have and a plurality ofly electrically connect respectively this semiconductor chip and this substrate with a spaced conductive projection.
This adhesive material that wherein has been filled on this substrate is to cover these semiconductor chips fully.
Wherein this adhesive material more is filled in respectively this chip and the space of this substrate and the interval between these conductive projections.
Wherein be filled in the thickness of this adhesive material on this substrate, be not less than this space height and this semiconductor chip thickness sum.
Wherein this first air pressure is 0.1torr～10torr.
Wherein the 3rd air pressure is for being not more than 30kgf/cm 2
Wherein the 3rd air pressure is 3kgf/cm 2～15kgf/cm 2
The gas that the 3rd air pressure wherein is provided is to select certainly: dry air (dry air), nitrogen (N 2) or inert gas (inert gases).
More comprise one second section cure step, guarantee that this adhesive material hardens fully.
More comprise the formation one respectively pin or the spherical binding element of this semiconductor device.
The present invention can effectively realize above-mentioned purpose, save above-mentioned manufacture procedure of adhesive equipment cost, simplify above-mentioned manufacture procedure of adhesive and promote process rate, production reliability and the useful life of semiconductor device.
For above and other objects of the present invention, feature and advantage can be become apparent, the following example cited below particularly is routine with work, and cooperates appended diagram, is described in detail below:
Description of drawings
Figure 1A～Fig. 1 C is a series of profile, in order to the known semiconductor device packages technology and the semiconductor device of manufacturing thereof to be described.
Fig. 2 A～Fig. 2 J is a series of profile, in order to the implementing procedure of explanation first embodiment of the invention.
Fig. 3 A～Fig. 3 K is a series of profile, in order to the implementing procedure of explanation second embodiment of the invention.
Fig. 4 A-Fig. 4 B is a series of photo, in order to the experimental result of example one of explanation work example of the present invention.
Fig. 5 A～Fig. 5 B is a series of photo, in order to the experimental result of example two of explanation work example of the present invention.
Fig. 6 is a series of photo, in order to the experimental result of example three of explanation work example of the present invention.
Execution mode
First embodiment:
In the first embodiment of the present invention, be to cover geode gate array (flip chip ball grid array with one; FCBGA) package semiconductor device is an example, the step of semiconductor device packing method of the present invention and the effect that can reach thereof are described, but do not represent application of the present invention just to be limited to the method for packing of the semiconductor device of above-mentioned FCBGA, the semiconductor device of other packing forms: for example with chip and substrate juncture, for wire bonds, winding engage or the packing forms of alternate manner automatically; With the connected mode of semiconductor device with extraneous (for example printed circuit board (PCB)), the packing forms that other has pin or does not have pin; Any semiconductor device packing method of the present invention that can use per capita of haveing the knack of this skill encapsulates the semiconductor device of above-mentioned other packing forms.
Step 1:
Please refer to Fig. 2 A, a substrate 100 is provided, can be organic or ceramic substrate, on a surface of substrate 100, comprises a predetermined adhesive area 110, and a plurality of encapsulation units 112 are included in predetermined adhesive area 110.Substrate 100 illustrates in Fig. 2 B along the part top view of arrow direction among Fig. 2 A, quantity and the arrangement mode of noting the encapsulation unit 112 of the employed substrate 100 of the first embodiment of the present invention are not limited to the form that Fig. 2 B is illustrated, and visual its of people of haveing the knack of this skill need and be changed.
Please get back to Fig. 2 A, a plurality of semiconductor chips 10 are provided, have a plurality of on its active surface with set spaced conductive projection 12; Semiconductor chip 10 and conductive projection 12 thereof with after each encapsulation unit 112 is aimed at, are sticked together semiconductor chip 10 on substrate 100 in the downward mode of active surface.Also visual its of people of haveing the knack of this skill need change the quantity and the arrangement mode thereof of conductive projection 12, also conductive projection 12 can be pre-formed on substrate 100 and not be formed on the semiconductor chip 10.
Step 2:
Please refer to Fig. 2 C, semiconductor chip 10 is sticked together and be fixed on the substrate 100, the visual process requirement of its mode and different the variation arranged.For example: can be earlier a tin cream (solder paste) (not illustrating at drawing) or scaling powder (flux) (not illustrating at drawing) be formed at ad-hoc location in each encapsulation unit, again with semiconductor chip 10 with after each encapsulation unit 112 is aimed at, semiconductor chip 10 is placed on the substrate 100, at last again via a reflow (reflow) processing procedure, with semiconductor chip 10 seam on substrate 100.This moment, semiconductor chip 10 formed electrically connect by conductive projection 12 with substrate 100.
Step 3:
Please refer to Fig. 2 D, substrate 100 is placed on the platform 52 in the sealing equipment 50, and a printing stencil 70 is placed on platform 52 and the substrate 100, the scope of the mesh 72 of printing stencil 70 is predetermined adhesive areas 110 of align substrates 100 and overlaps with it; The air pressure of setting in the sealing equipment 50 is first air pressure: 0.1torr～10torr, treat sealing equipment 50 air pressure inside arrive the value set and stable after, utilize stencil methods, use scraper (squeeze) 60 will place the adhesive material 120 on the printing stencil 70 to be formed on the substrate 100 via mesh 72 in advance with the A direction.Wherein printing stencil 70 is generally metal material, the size of its thickness and mesh 72, quantity, arrangement mode, but the different of packing colloid thickness that will form on the size of the design of optic placode 100, predetermined adhesive area 110 and quantity and arrangement mode and the substrate 100 change.
Wherein, the main material of adhesive material 120 is any Material formula makeup that is applicable to that the semiconductor packages characteristic requires.
Step 4:
Please refer to Fig. 2 E, scraper 60 and adhesive material 120 partly move to the other end of printing stencil 70, and the inside that has been formed on the adhesive material 120 on the substrate 100 is for example residual in the gap of conductive projection 12 some bubbles 122; Again the air pressure in the sealing equipment 50 is set at second air pressure greater than above-mentioned first air pressure, treat air pressure in the sealing equipment 50 arrive second air pressure that sets and stable after, this moment, bubble 122 was because of being subjected to big pressure, even its volume can dwindle disappearance, and make the adhesive material 120 that is formed on the substrate 100 because of filling up above-mentioned bubble 122 and dwindle or some potholes 124 appear in the space that is carried over that disappears on the surface; Re-use scraper 60 and will remain in adhesive material 120 on the printing stencil 70 has been formed on the adhesive material 120 on the substrate 100 via mesh 72 leveling with the B direction surface.
In addition, the thickness that has been formed on the adhesive material 120 on the substrate 100 can just equal the height sum in space between the thickness of semiconductor chip 10 and semiconductor chip 10 and the substrate 100, and just makes another surface exposure of semiconductor chip 10; The adhesive material 120 that has been formed on the substrate 100 also can cover semiconductor chip 10 fully.
Step 5:
Please refer to Fig. 2 F, remove scraper 60 and printing stencil 70, the surface of the adhesive material 120 on the substrate 100 flattens at this moment, and its inner bubble 122 has disappeared nearly all, still has the bubble 122 that has only a few to remain in the inside of adhesive material 120.
Step 6:
Please refer to Fig. 2 G, can collect the substrate 100 of lot, put into one or a plurality of substrate small suitcase (magazine) (not illustrating) at drawing, above-mentioned magazine being put into a pressurization baking oven (pressure oven) (not illustrating) or pressurization axe (pressure chamber) (not illustrating), be set at air pressure greater than an atmospheric pressure and be not more than 30kgf/cm at drawing at drawing 2The 3rd air pressure, wherein above-mentioned the 3rd air pressure is preferably 3kgf/cm 2～15kgf/cm 2, gas-pressurized can be dry air (dry air), nitrogen (N 2) or inert gas (inert gases) etc., dwindle more or disappear so that may still residue in the bubble 122 of the inside of adhesive material 120.
In pressurization; can carry out glue material sclerosis processing procedure; look the property settings hardening parameter of adhesive material 120; make adhesive material 120 become a tool elasticity; sealing is good; the chemical stability height; and the packing colloid 126 of insulation; can protect semiconductor chip 10 with as the conductive projection 12 of semiconductor chip 10 with substrate 100 contacts; be not subjected to the thermal stress that difference caused of thermal coefficient of expansion between semiconductor chip 10 and the substrate 100; and the invasion of environmental contaminants and being damaged, also protect between each conductive projection 12 due to leakage current (leakage) not and the situation that is short-circuited.
In addition, via the effect of above-mentioned the 3rd air pressure pressurization, the inside of packing colloid 126 has not had above-mentionedly to cause the popcorn effect of semiconductor device that semiconductor device was lost efficacy or concentrate and accelerate the failure and the bubble that lost efficacy in semiconductor device stress when meeting with stresses at follow-up hot processing procedure probably fully.
Step 7:
Please refer to Fig. 2 H, can on substrate 100 another lip-deep ad-hoc locations, form a plurality of spherical binding elements 130 optionally with substrate 100 turn-overs.Its generation type for example is: form a tin cream (solder paste) (not illustrating at drawing) or scaling powder (flux) (not illustrating at drawing) respectively on aforesaid substrate 100 another lip-deep ad-hoc locations, on above-mentioned tin cream or scaling powder, place a tin ball (solder ball) (not illustrating) with certain sphere diameter more respectively at drawing, via another back welding process above-mentioned tin ball bonding is combined on the substrate 100 again, forms a plurality of spherical binding elements 130.
Step 8:
Please refer to Fig. 2 I, is unit with the encapsulation unit shown in Fig. 2 A 112, uses a rotary cutter 80 cutting substrates 100, forms the semiconductor device 150 of a plurality of FCBGA packing forms that illustrated as Fig. 2 J.In addition, substrate 100 also can use the conductive metal frames of no pin form, does not just carry out above-mentioned steps seven when implementing.
Again, after step 6, can additionally add above hardening process of a stage, can harden fully to guarantee packing colloid 126.And above-mentioned extra hardening process can be carried out under air pressure identical with step 7 and gas-pressurized, also can carry out under a general atmospheric pressure, decides on process requirement.
Step 3 according to first embodiment of the invention, semiconductor device packing method of the present invention, can carry out manufacture procedure of adhesive to two (containing) above semiconductor device simultaneously, and can increase the output of above-mentioned semiconductor device, can save the equipment cost of above-mentioned manufacture procedure of adhesive again.
Step 3～step 6 according to first embodiment of the invention, semiconductor device packing method of the present invention, can carry out manufacture procedure of adhesive, can avoid in semiconductor device, producing simultaneously bubble again, two (containing) above semiconductor device simultaneously with encapsulation yield that promotes semiconductor device or reliability and the useful life that promotes the semiconductor device of institute's output.
Step 3～step 6 according to first embodiment of the invention, semiconductor device packing method of the present invention, can be simultaneously to two (containing) above semiconductor device carry out manufacture procedure of adhesive, not only can avoid simultaneously in semiconductor device, producing bubble, also can be especially to the semiconductor device wafer be adhered on substrate of chip package the time but also can while capping entire chip, with the reliability and the useful life of the semiconductor device that promotes institute's output more.
Second embodiment:
In the second embodiment of the present invention, be to be changed to example with the MCM semiconductor device that a chip stack encapsulates, the step of semiconductor device packing method of the present invention and the effect that can reach thereof are described, semiconductor device packing method particularly of the present invention, it is applicable to the demand characteristics that comprises the semiconductor device packing method of chip package in all interior encapsulation technologies, when encapsulating the MCM semiconductor device with the chip stack encapsulation technology, can bring into play: the equipment cost that more can save above-mentioned manufacture procedure of adhesive, simplify above-mentioned manufacture procedure of adhesive, and the process rate of lifting semiconductor device, the effect in production reliability and useful life; Please refer to the following step:
Step 1:
Please refer to Fig. 3 A, a substrate 200 is provided, can be organic or ceramic substrate, on a surface of substrate 200, comprises a predetermined adhesive area 210, and a plurality of encapsulation units 212 are included in predetermined adhesive area 210.Substrate 200 is similar to the substrate 100 that illustrates in Fig. 2 B along the part top view of arrow direction among Fig. 3 A, and the Therefore, omited does not illustrate; Quantity and the arrangement mode of noting the encapsulation unit 212 of the employed substrate 200 of the second embodiment of the present invention are not limited to the form that Fig. 2 B is illustrated, and visual its of people of haveing the knack of this skill need and be changed.
Please get back to Fig. 3 A, a plurality of semiconductor chips 20 are provided, have a plurality of on its active surface with set spaced conductive projection 22; Semiconductor chip 20 and conductive projection 22 thereof with after each encapsulation unit 212 is aimed at, are sticked together semiconductor chip 20 on substrate 200 in the downward mode of active surface.Also visual its of people of haveing the knack of this skill need change the quantity and the arrangement mode thereof of conductive projection 22, also conductive projection 22 can be pre-formed on substrate 200 and not be formed on the semiconductor chip 20.
Step 2:
Please refer to Fig. 3 B, semiconductor chip 20 is sticked together and be fixed on the substrate 200, the visual process requirement of its mode and different the variation arranged.For example: can be earlier a tin cream (solder paste) (not illustrating at drawing) or scaling powder (flux) (not illustrating at drawing) be formed at ad-hoc location in each encapsulation unit, again with semiconductor chip 20 with after each encapsulation unit 212 is aimed at, semiconductor chip 20 is placed on the substrate 200, at last again via a reflow (reflow) processing procedure, with semiconductor chip 20 seam on substrate 200.This moment, semiconductor chip 20 formed electrically connect by conductive projection 22 with substrate 200.
Step 3:
Please refer to Fig. 3 C, a plurality of semiconductor chips 30 are provided again, the semiconductor chip 20 that is different from above-mentioned flip chip type formula sticks together on substrate 200 in the downward mode of active surface; Semiconductor chip 30 is to stick together respectively on each semiconductor chip 20 in the mode that active surface makes progress, and forms electrically connect with bonding wire 32 and substrate 200 respectively again.Wherein the material of bonding wire 32 is gold-base alloy (Au-based alloy), be to be main material with gold, adds the minority alloying element again to adjust its physical property; And under the only a few situation, it is the lead of main material with aluminium that bonding wire 32 also has use.
The people who is familiar with this skill also can optionally increase the number of semiconductor chip storehouse, or/and the mode of above-mentioned wire bonds is changed to winding engage automatically or other form.
Step 4:
Please refer to Fig. 3 D, substrate 200 is placed on the platform 54 in the sealing equipment 50, and a printing stencil 90 is placed on platform 54 and the substrate 100, the scope of the mesh 92 of printing stencil 90 is predetermined adhesive areas 210 of align substrates 200 and overlaps with it; The air pressure of setting in the sealing equipment 50 is first air pressure: 0.1torr～10torr, treat sealing equipment 50 air pressure inside arrive the value set and stable after, utilize stencil methods, use scraper (squeegee) 60 will place the adhesive material 220 on the printing stencil 90 to be formed on the substrate 200 via mesh 92 in advance with the A direction.Wherein printing stencil 90 is generally metal material, the size of its thickness and mesh 92, quantity, arrangement mode, but the different of packing colloid thickness that will form on the size of the design of optic placode 200, predetermined adhesive area 210 and quantity and arrangement mode and the substrate 200 change.
Wherein, the main material of adhesive material 220 is any Material formula makeup that is applicable to that the semiconductor packages characteristic requires.
Step 5:
Please refer to Fig. 3 E, scraper 60 and adhesive material 220 partly move to the other end of printing stencil 90, and the inside that has been formed at the adhesive material 220 on the substrate 200 is for example residual in the gap of conductive projection 22 some bubbles 222; Again the air pressure in the sealing equipment 50 is set at second air pressure greater than above-mentioned first air pressure, treat air pressure in the sealing equipment 50 arrive second air pressure that sets and stable after, this moment, bubble 222 was because of being subjected to big pressure, even its volume can dwindle disappearance, and make the adhesive material 220 that is formed on the substrate 200 because of filling up above-mentioned bubble 222 and dwindle or some potholes 224 appear in the space that is carried over that disappears on the surface; Re-use scraper 60 and will remain in adhesive material 220 on the printing stencil 90 has been formed at the adhesive material 220 on the substrate 200 via mesh 92 leveling with the B direction surface.
In addition, the thickness that has been formed at the adhesive material 220 on the substrate 200 must cover semiconductor chip 30 and bonding wire 32 fully.
Step 6:
Please refer to Fig. 3 F, remove scraper 60 and printing stencil 90, the surface of the adhesive material 220 on the substrate 200 flattens at this moment, and its inner bubble 222 has been forced nearly all, still has the bubble 222 that has only a few to remain in the inside of adhesive material 220.
Step 7:
Please refer to Fig. 3 G, can collect the substrate 200 of lot, put into one or a plurality of substrate small suitcase (magazine) (not illustrating) at drawing, above-mentioned magazine being put into a pressurization baking oven (pressure oven) (not illustrating) or pressurization axe (pressure chamber) (not illustrating), be set at air pressure greater than an atmospheric pressure and be not more than 30kgf/cm at drawing at drawing 2The 3rd air pressure, wherein above-mentioned the 3rd air pressure is preferably 3kgf/cm 2～15kgf/cm 2, gas-pressurized can be dry air (dry air), nitrogen (N 2) or inert gas (inert gases) etc., dwindle more or disappear so that may still residue in the bubble 222 of the inside of adhesive material 220.
In pressurization; can carry out glue material sclerosis processing procedure; look the property settings hardening parameter of adhesive material 220; make adhesive material 220 become a tool elasticity; sealing is good; the chemical stability height; and the packing colloid 226 of insulation; can protect semiconductor chip 20; semiconductor chip 30; as the conductive projection 22 of semiconductor chip 20 with substrate 200 contacts; with the bonding wire 32 that electrically connects semiconductor chip 30 and substrate 200; not can under air pressure identical and gas-pressurized, carry out by semi-conductive hardening process with step 7; can also under a general atmospheric pressure, carry out, decide on process requirement.
And the semiconductor device of so-called MCM is not limited to chip stack technology package semiconductor device 250, also comprises shown in Fig. 3 K, and semiconductor chip is the semiconductor device of the MCM of storehouse not.And be familiar with the people of this skill, and also can be under the situation that does not increase the manufacture procedure of adhesive complexity, bonding semiconductor device 250,260 is equiped with the storehouse and the semiconductor chip of storehouse not in the semiconductor device of same MCM.Step 4 according to second embodiment of the invention, semiconductor device packing method of the present invention, can carry out manufacture procedure of adhesive to two (containing) above semiconductor device simultaneously, and can increase the output of above-mentioned semiconductor device, can save the equipment cost of above-mentioned manufacture procedure of adhesive again.
Step 4～step 7 according to second embodiment of the invention, semiconductor device packing method of the present invention, can carry out manufacture procedure of adhesive, can avoid in semiconductor device, producing simultaneously bubble again, two (containing) above semiconductor device simultaneously with encapsulation yield that promotes semiconductor device or reliability and the useful life that promotes the semiconductor device of institute's output.
Step 4～step 7 according to second embodiment of the invention, semiconductor device packing method of the present invention, can be simultaneously to two (containing) above semiconductor device carry out manufacture procedure of adhesive, not only can avoid simultaneously in semiconductor device, producing bubble, also can be especially to the semiconductor device wafer be adhered on substrate of chip package the time but also can while capping entire chip, with the reliability and the useful life of the semiconductor device that promotes institute's output more.
Step 4～step 7 according to second embodiment of the invention, semiconductor device packing method of the present invention, can carry out manufacture procedure of adhesive to two (containing) above semiconductor device simultaneously, simultaneously can avoid in semiconductor device, producing bubble again, also can be especially to the semiconductor device wafer be adhered on substrate of chip package the time entire chip of capping simultaneously again, also be applicable to the demand that comprises the semiconductor device packing method of chip package in all interior encapsulation technologies, more can save the equipment cost of above-mentioned manufacture procedure of adhesive, simplify above-mentioned manufacture procedure of adhesive, and the process rate of lifting semiconductor device, production reliability and useful life.
Above-mentioned first and second embodiment according to the present invention, semiconductor device packing method of the present invention is to reach all above-mentioned main purpose of the present invention and other purposes.
The work example:
In following work example, be to prove as an example that with three groups of FCBGA semiconductor making method of the present invention can effectively avoid producing at the packing colloid of semiconductor device the effect of bubble really.In above-mentioned known techniques,, the problem of entrapped air pockets is arranged easily between semiconductor chip and substrate with the Flip Chip package semiconductor device.Therefore, in following work example, semiconductor making method of the present invention can effectively be avoided producing bubble with the packing colloid of Flip Chip package semiconductor device, represents that promptly semiconductor making method of the present invention more can effectively avoid engaging automatically with wire bonds, winding or the packing colloid of other encapsulation technology package semiconductor device produces bubble.
In following work example, because be with FCBGA as an example, its fabrication steps is to implement according to above-mentioned first embodiment.Following example one, example two are to be experimental group, in the process of enforcement all according in the first embodiment of the present invention the narration of each step condition and be enforcement; And example three is to be damaged for the thermal stress that difference caused of thermal coefficient of expansion and the invasion of environmental contaminants between chip 20 and the substrate 200, also protects between each conductive projection 22 and each bonding wire 32 due to leakage current (leakage) not and the situation that is short-circuited.In addition, via the effect of above-mentioned the 3rd air pressure pressurization, the inside of packing colloid 226 has not had above-mentionedly to cause the popcorn effect of semiconductor device that semiconductor device was lost efficacy or concentrate and accelerate the failure and the bubble that lost efficacy in semiconductor device stress when meeting with stresses at follow-up hot processing procedure probably fully.
Step 8:
Please refer to Fig. 3 H, can on substrate 200 another lip-deep ad-hoc locations, form a plurality of spherical binding elements 230 optionally with substrate 200 turn-overs.Its generation type for example is: form a tin cream (solder paste) (not illustrating at drawing) or scaling powder (flux) (not illustrating at drawing) respectively on aforesaid substrate 200 another lip-deep ad-hoc locations, on above-mentioned tin cream or scaling powder, place a tin ball (solder ball) (not illustrating) with certain sphere diameter more respectively at drawing, via another back welding process above-mentioned tin ball is welded on the substrate 200 again, forms a plurality of spherical binding elements 230.
Step 9:
Please refer to Fig. 3 I, is unit with the encapsulation unit shown in Fig. 3 A 212, uses a rotary cutter 80 cutting substrates 200, forms the semiconductor device 250 of a plurality of MCM that illustrated as Fig. 3 J.
In addition, substrate 200 also can use the conductive metal frames of no pin form, does not just carry out above-mentioned steps nine when implementing.
Again, after step 7, can additionally add above hardening process of a stage, can harden fully to guarantee packing colloid 226.And above-mentioned extra check group, the condition of its enforcement are then slightly different.And the implementation condition of following example one, example two is one of numerous example, thereby should not limit the implementation condition of method for packaging semiconductor of the present invention thus, the people who is familiar with this skill person according to its product that will encapsulate not, material source, appointed condition etc., do not breaking away from variation to some extent under feature of the present invention and the spirit.
Example one:
One first substrate is provided, and having an area on the surface of above-mentioned first substrate is the predetermined adhesive area of 40mm * 40mm, has 9 encapsulation units in the above-mentioned predetermined adhesive area, with 3 * 3 arranged.Then beginning according to the step 1 of first embodiment of the invention is enforcement in regular turn; When step 3, the mesh size of employed printing stencil is that 40mm * 40mm, printing stencil thickness are about 0.8mm, employed liquid adhesive material (liquid encapsulant) is that viscosity is about 120Pa.S, the CV-5400A product of being produced by Matsushita Electric WorksCo. (MEW), and above-mentioned first substrate sets in sealing equipment under the air pressure of 0.7torr and utilizes the scraper of Teflon material to carry out the mould printing step; Be carried out up to step 7 more in regular turn; Before step 7, the adhesive material inside of observing on above-mentioned first substrate has or not bubble and distribution scenario earlier, and after being noted down, execution in step seven; When step 7, above-mentioned first substrate is moved in the pressure baking oven, setting adding pressure is about 5kgf/cm 2, gas-pressurized is dry air (dry air), heat up simultaneously and carry out first section hardening process: 100 ℃/1hr, treat that after first section sclerosis finishes above-mentioned first substrate being moved to general baking oven carries out the second stage after-hardening again: 150 ℃/3hrs, promptly finish sealing sclerosis processing procedure; Next, the adhesive material inside of observing and noting down on above-mentioned first substrate has or not bubble and distribution scenario.
Example two:
One second substrate is provided, and having an area on the surface of above-mentioned second substrate is the predetermined adhesive area of 40mm * 40mm, has 9 encapsulation units in the above-mentioned predetermined adhesive area, with 3 * 3 arranged.Then beginning according to the step 1 of second embodiment of the invention is enforcement in regular turn; When step 3, the mesh size of employed printing stencil is that 40mm * 40mm, printing stencil thickness are about 0.8mm, employed liquid adhesive material (liquid encapsulant) is that viscosity is about 30Pa.S, the CV-5351A product of being produced by Matsushita Electric WorksCo. (MEW), and above-mentioned second substrate sets in sealing equipment under the air pressure of 0.7torr and utilizes the scraper of Teflon material to carry out the mould printing step; Be carried out up to step 7 more in regular turn; Before step 7, the adhesive material inside of observing on above-mentioned second substrate has or not bubble and distribution scenario earlier, and after being noted down, execution in step seven; When step 7, above-mentioned second substrate is moved in the pressure baking oven, setting adding pressure is 5kgf/cm 2, gas-pressurized is dry air (dry air), heat up simultaneously and carry out first section hardening process: 100 ℃/1hr, treat that after first section sclerosis finishes above-mentioned second substrate being moved to general baking oven carries out the second stage after-hardening again: 150 ℃/3hrs, promptly finish sealing sclerosis processing procedure; Next, the adhesive material inside of observing and noting down on above-mentioned second substrate has or not bubble and distribution scenario.
Example three:
One the 3rd substrate is provided, and having an area on the surface of above-mentioned the 3rd substrate is the predetermined adhesive area of 40mm * 40mm, has 9 encapsulation units in the above-mentioned predetermined adhesive area, with 3 * 3 arranged.Then beginning according to the step 1 of third embodiment of the invention is enforcement in regular turn; When step 3, the mesh size of employed printing stencil is that 40mm * 40mm, printing stencil thickness are about 0.8mm, employed liquid adhesive material (liquid encapsulant) is that viscosity is about 120Pa.S, the CV-5400A product of being produced by Matsushita Electric WorksCo. (MEW), and above-mentioned the 3rd substrate sets in sealing equipment under the air pressure of 0.7torr and utilizes the scraper of Teflon material to carry out the mould printing step; Be carried out up to step 7 more in regular turn; Before step 7, the adhesive material inside of observing on above-mentioned the 3rd substrate has or not bubble and distribution scenario earlier, and after being noted down, execution in step seven; When step 7, above-mentioned the 3rd substrate is moved in the general baking oven, this moment, pressure was about 1atm, heated up and carried out first section hardening process: 100 ℃/1hr, carry out the second stage after-hardening again: 150 ℃/3hrs, promptly finish sealing sclerosis processing procedure; Next, the adhesive material inside of observing and noting down on above-mentioned the 3rd substrate has or not bubble and distribution scenario.
Please refer to Fig. 4 A～Fig. 4 B, is a series of photo, shows the experimental result of the example one of the invention described above work example.Fig. 4 A shows that record is to a bubble before carrying out the first embodiment of the invention step 7; And Fig. 4 B be presented at carry out the first embodiment of the invention step 7 after, the just complete obiteration of above-mentioned bubble is the effect that proof semiconductor making method of the present invention can effectively avoid producing at the packing colloid of semiconductor device bubble really.
Please refer to Fig. 5 A～Fig. 5 B, is a series of photo, shows the experimental result of the example two of the invention described above work example.Wherein above-mentioned example two is 120Pa.S with the difference of example one at example one employed liquid adhesive material viscosity, greater than the liquid adhesive material of example two viscosity that uses as 30Pa.S.Fig. 5 A shows, record is to a bubble before carrying out the first embodiment of the invention step 7, and less because of employed liquid sealing ability viscosity, the bubble in the liquid encapsulating material of the diameter of above-mentioned bubble thereby the example one shown than Fig. 4 A is little; And Fig. 5 B be presented at carry out the first embodiment of the invention step 7 after, the just complete obiteration of above-mentioned bubble is the effect that proof semiconductor making method of the present invention can effectively avoid producing at the packing colloid of semiconductor device bubble really.
Please refer to Fig. 6, is a photo, shows the experimental result of the example three of the invention described above work example.The difference of wherein above-mentioned example three and example one is when step 7, example three is not carried out as the pressurization program of method for packaging semiconductor of the present invention and the adhesive material on above-mentioned the 3rd substrate that directly hardens, therefore there is no at the viewed bubble in the step 7 front and back of first embodiment of the invention and change, after above-mentioned sealing material hardened into packing colloid, this bubble still was present in the above-mentioned packing colloid.
Can prove that by the result of implementation of above-mentioned work example semiconductor making method of the present invention can effectively avoid producing at the packing colloid of semiconductor device the effect of bubble really, it is another purpose of reaching above-mentioned " semiconductor device packing method of the present invention; can be simultaneously two (containing) above semiconductor device is carried out manufacture procedure of adhesive, can be avoided producing simultaneously bubble again in semiconductor device is with the encapsulation yield that promotes semiconductor device or reliability and the useful life that promotes the semiconductor device of institute's output ".
In addition, result of implementation by above-mentioned work example can illustrate, semiconductor device packing method of the present invention produces aspect the effect of bubble at the packing colloid of semiconductor device effectively avoiding, with the above-mentioned first embodiment of the present invention be example step 3～step 7 on the implementation, real is indispensable necessary condition.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to qualification the present invention, any people who has the knack of this skill, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking the claim scope.

Claims (20)

1. a semiconductor device packing method is applicable to a manufacture procedure of adhesive, it is characterized in that comprising the following steps:
One substrate is provided, and it has a plurality of semiconductor devices, and these semiconductor devices comprise the semiconductor chip respectively and are electrically connected at respectively in this substrate one lip-deep one predetermined adhesive area;
Be lower than under atmospheric first air pressure, with stencil methods (stencil printing) with on excessive inswept this substrate of adhesive material should predetermined adhesive area in, make this encapsulating material partly be filled on this substrate should predetermined adhesive area in;
Under second air pressure, will not be filled in this adhesive material on this substrate with stencil methods, on inswept this adhesive material that has been filled on this substrate greater than this first air pressure; And
Under greater than atmospheric the 3rd air pressure, this adhesive material hardens.
2. semiconductor device packing method as claimed in claim 1, it is characterized in that the mode that wherein these semiconductor chips and this substrate electrically connect is to cover the electric connection of crystal type and this substrate, and respectively have a space respectively between this semiconductor chip and this substrate, and in this space respectively, have and a plurality ofly electrically connect respectively this semiconductor chip and this substrate with a spaced conductive projection.
3. semiconductor device packing method as claimed in claim 1, this adhesive material that it is characterized in that wherein being filled on this substrate is to cover these semiconductor chips fully.
4. semiconductor device packing method as claimed in claim 2 is characterized in that wherein this adhesive material more is filled in respectively this chip and the space of this substrate and the interval between those conductive projections.
5. semiconductor device packing method as claimed in claim 2 is characterized in that wherein being filled in the thickness of this adhesive material on this substrate being not less than this space height and this semiconductor chip thickness sum.
6. semiconductor device packing method as claimed in claim 1 is characterized in that wherein this first air pressure is 0.1torr～10torr.
7. semiconductor device packing method as claimed in claim 1 is characterized in that wherein the 3rd air pressure is for being not more than 30kgf/cm 2
8. semiconductor device packing method as claimed in claim 1 is characterized in that wherein the 3rd air pressure is 3kgf/cm 2～15kgf/cm 2
9. semiconductor device packing method as claimed in claim 1 is characterized in that it is to select certainly that the gas of the 3rd air pressure wherein is provided: dry air (dry air), nitrogen (N 2) or inert gas (inert gases).
10. a semiconductor device packing method is characterized in that comprising the following steps:
One substrate and a plurality of semiconductor chip are provided, wherein have a predetermined adhesive area on the surface of this substrate, this predetermined adhesive area comprises a plurality of encapsulation units;
These semiconductor chips are placed respectively in the above-mentioned encapsulation unit, be electrically connected at this substrate respectively;
Be lower than under atmospheric first air pressure, with stencil methods (stencil printing) with on excessive inswept this substrate of adhesive material should predetermined adhesive area in, make this encapsulating material partly be filled on this substrate should predetermined adhesive area in;
Under second air pressure, will not be filled in this adhesive material on this substrate with stencil methods, on inswept this adhesive material that has been filled on this substrate greater than this first air pressure;
Under greater than atmospheric the 3rd air pressure, first section this adhesive material of sclerosis; And
With these encapsulation units is unit, and this substrate is divided into a plurality of semiconductor devices.
11. semiconductor device packing method as claimed in claim 10, it is characterized in that wherein these semiconductor chips are to electrically connect to cover crystal type and this substrate, and respectively have a space respectively between this semiconductor chip and this substrate, and in this space respectively, have and a plurality ofly electrically connect respectively this semiconductor chip and this substrate with a spaced conductive projection.
12. semiconductor device packing method as claimed in claim 10, this adhesive material that it is characterized in that wherein being filled on this substrate is to cover these semiconductor chips fully.
13. semiconductor device packing method as claimed in claim 11 is characterized in that wherein this adhesive material more is filled in respectively this chip and the space of this substrate and the interval between these conductive projections.
14. semiconductor device packing method as claimed in claim 11 is characterized in that wherein being filled in the thickness of this adhesive material on this substrate being not less than this space height and this semiconductor chip thickness sum.
15. semiconductor device packing method as claimed in claim 10 is characterized in that wherein this first air pressure is 0.1torr～10torr.
16. semiconductor device packing method as claimed in claim 10 is characterized in that wherein the 3rd air pressure is for being not more than 30kgf/cm 2
17. semiconductor device packing method as claimed in claim 10 is characterized in that wherein the 3rd air pressure is 3kgf/cm 2～15kgf/cm 2
18. semiconductor device packing method as claimed in claim 10 is characterized in that it is to select certainly that the gas of the 3rd air pressure wherein is provided: dry air (dry air), nitrogen (N 2) or inert gas (inert gases).
19. semiconductor device packing method as claimed in claim 10 is characterized in that more comprising one second section cure step, guarantees that this adhesive material hardens fully.
20. semiconductor device packing method as claimed in claim 10 is characterized in that more comprising the formation one respectively pin or the spherical binding element of this semiconductor device.
CNB031313485A 2003-05-14 2003-05-14 Semi conductor device packaging method Expired - Lifetime CN1258808C (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101937884A (en) * 2010-08-12 2011-01-05 日月光半导体制造股份有限公司 Semiconductor packaging member
CN102403240A (en) * 2011-10-11 2012-04-04 常熟市广大电器有限公司 Sealing method of chip
CN110620051A (en) * 2019-08-29 2019-12-27 深圳赛意法微电子有限公司 Wafer surface coating method, packaging method and vacuum printing machine
CN111826107A (en) * 2020-08-07 2020-10-27 武汉锐奥特科技有限公司 Packaging processing method of optical device optical path structure based on single-fiber bidirectional

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101937884A (en) * 2010-08-12 2011-01-05 日月光半导体制造股份有限公司 Semiconductor packaging member
CN101937884B (en) * 2010-08-12 2012-07-25 日月光半导体制造股份有限公司 Semiconductor packaging member
CN102403240A (en) * 2011-10-11 2012-04-04 常熟市广大电器有限公司 Sealing method of chip
CN110620051A (en) * 2019-08-29 2019-12-27 深圳赛意法微电子有限公司 Wafer surface coating method, packaging method and vacuum printing machine
CN111826107A (en) * 2020-08-07 2020-10-27 武汉锐奥特科技有限公司 Packaging processing method of optical device optical path structure based on single-fiber bidirectional

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