CN1545097A - Output driving strength correcting circuit and method for DRAM - Google Patents
Output driving strength correcting circuit and method for DRAM Download PDFInfo
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- CN1545097A CN1545097A CNA2003101149570A CN200310114957A CN1545097A CN 1545097 A CN1545097 A CN 1545097A CN A2003101149570 A CNA2003101149570 A CN A2003101149570A CN 200310114957 A CN200310114957 A CN 200310114957A CN 1545097 A CN1545097 A CN 1545097A
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- 238000000034 method Methods 0.000 title abstract description 13
- 238000012937 correction Methods 0.000 claims description 15
- 230000001915 proofreading effect Effects 0.000 claims description 3
- 230000008859 change Effects 0.000 description 7
- 238000001514 detection method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000009966 trimming Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
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Abstract
The invention is an output driving strength correcting circuit and method for a dynamic random access memory (DRAM), applied to an automatic driving strength compensating circuit in order to regulate the resistance value of the output generator of a memory control chip into the object value of the driving strength of the DRAM, therefore able to directly apply the input comparer of the memory control chip to read the DRAM so as to generate an output value, and without an additional high-gain comparer, it can accurately correct the output driving strength, and it is easy to make and to correct.
Description
Technical field
The present invention is relevant for a kind of dynamic RAM (Dynamic Random AccessMemory, be called for short DRAM), and particularly relevant for a kind of output driving strength correcting circuit and method of dynamic RAM.
Background technology
Along with the prosperity of science and technology, computing machine has become information products indispensable among the human lives, its in the workplace in addition shared status such as family life management just hurriedly increase with day.
Recently, computer equipment is in the evolution of arithmetic speed and data processing amount, and it is at a tremendous pace to say so, and therefore, the hardware unit that uses in computing machine is also along with changing apace.With regard to the storer that uses with computing machine, just by dynamic RAM, double data rate dynamic RAM (Double Data Rate Dynamic Random Access Memory, be called for short DDR), and advance to operation rate second generation double data rate dynamic RAM (Double Data RateII Dynamic Random Access Memory, be called for short DDRII) faster.Under the two-forty operation (being generally more than the 400MHz) of second generation double data rate dynamic RAM, in order to ensure the integrality of data transmission, must use an aligning gear, proofread and correct the output drive strength of dynamic RAM.
Please refer to shown in Figure 1ly, it is a kind of known dynamic RAM and its output driving strength correcting circuit synoptic diagram.Wherein dynamic RAM 120 comprises that drawing high (pull up) drives output 121, drags down (pull down) and drive output 122, and draw high in order to adjustment and to drive output 121 and to drag down the drive strength that drives output 122 and adjust logic element 123.110 of output driving strength correcting circuit are used terminal (On-Die-Termination on a steering logic element 111, the chip, be called for short ODT) 112 and 113, and proofread and correct the high- gain comparer 114 and 115 of usefulness, come to drive output 121 and drag down driving and export 122 output drive strength and proofread and correct to drawing high.In addition, the input comparator 117 of importing (D-in) as the output generator 116 and the data of data outputs (D-out) in the storer control chip among the figure then uses at timing.
Terminal on the chip (ODT) 112 and 113 resistance value are generally 300 ohm, and dynamic RAM 120 draw high that to drive output 121 be 4 ohm of 18 ohm of plus-minuss with dragging down the probable value that drives output 122, that is scope is at 14 ohm to 22 ohm.Therefore, draw high when driving output 121 when proofreading and correct, consideration will be proofreaied and correct to draw high and be driven 121 to 18 ohm of outputs, so the reference voltage Voh that the corresponding input end with high-gain comparer 114 is received is set at 300/ (300+18) * Vcc, and with high-gain comparer 114 another input point E (draw high drive that terminal (ODT) 113 provides dividing potential drop on output 121 and the chip by correction) relatively after, COUNTP is to steering logic element 111 in the output control information, adjust logic element 123 adjustment corrections via drive strength again and draw high driving output 121, to realize the effect of correction.Be 4 ohm of 18 ohm of plus-minuss owing to drawing high the probable value that drives output 121 in addition, add that terminal on the chip (ODT) 112 and 113 is 300 ohm, so high-gain comparer 114 admissible change detection window (detection window) drop on the scope of-4/ (300+18) to+4/ (300+18).Identical with it, when correction drags down when driving output 122, consideration will be proofreaied and correct to drag down and be driven 122 to 18 ohm of outputs, reference voltage Vol on the input end of corresponding high-gain comparer 115 will be set at 18/ (300+18) * Vcc, and with high-gain comparer 115 another input point E (drag down drive that terminal (ODT) 112 provides dividing potential drop on output 122 and the chip by correction) relatively after, COUNTN is to steering logic element 111 in the output control information, adjust logic element 123 adjustment corrections via drive strength again and drag down driving output 122, to realize the effect of correction.Be 4 ohm of 18 ohm of plus-minuss owing to dragging down the probable value that drives output 122 in addition, add that terminal on the chip (ODT) 112 and 113 is 300 ohm, so high-gain comparer 115 its admissible change detection window also drop on the scope of-4/ (300+18) to+4/ (300+18).
Above-mentioned output driving strength correcting circuit 110, because of terminal (ODT) 112 and 113 on the use chip is proofreaied and correct, under the very big usually situation of resistance value, make that the change detection window is very little, so need very accurate reference voltage Voh and Vol, obtaining about 1% accuracy range, and increase the difficulty of making, in addition must corresponding use can differentiate the expensive especially expenditure of high-gain comparer of 1% voltage difference.
Summary of the invention
In view of this, the invention provides a kind of output driving strength correcting circuit and method of dynamic RAM, the high-gain comparer that it can add, can accurately proofread and correct the output drive strength of dynamic RAM, and circuit is easy to make and be easy to the carrying out of correction work.
For reaching above-mentioned and other purpose, the invention provides a kind of output driving strength correcting circuit, be used for a dynamic RAM, comprising: a drive strength auto compensatng circuit, according to a reference resistance, output one automatic compensating control signal; Logic element is adjusted in one output, receives data output and this automatic compensating control signal one of in the two in order to control, exports; One output generator when receiving this automatic compensating control signal, produces a corresponding correction resistance; An and input comparator, one input end receives a reference voltage, another input end is connected to output terminal and this dynamic RAM of this output driver, compares output valve in order to produce one, proofreaies and correct the output drive strength of this dynamic RAM.
Wherein, reference resistance for example uses the resistance on the motherboard, and output generator and input comparator are positioned on the north bridge control chip.Output generator comprises that drawing high o controller and drags down o controller.And drawing high o controller can be made of a plurality of PMOS transistors, and dragging down o controller can be made of a plurality of nmos pass transistors.Automatically the number of compensating control signal control PMOS transistor or nmos pass transistor conducting produces corresponding resistance.Said structure more can comprise a steering logic element in addition, receives this comparison output valve, produces a control signal, adjusts the output drive strength of dynamic RAM.
The present invention provides the bearing calibration of a kind of output drive strength in addition, make apparatus proofread and correct an output generator and an input comparator of resistance with one, proofread and correct the output drive strength of a dynamic RAM, one input end of this input comparator connects a reference voltage, the other end is connected to this dynamic RAM and this output driver, comprises the following steps: at first to turn-off this output generator; Then read this dynamic RAM, produced an output valve with this input comparator; When this output valve is one first fixed value, proofreaies and correct one of this dynamic RAM and drag down the output drive strength that drives output; And when this output valve is one second fixed value, proofreaies and correct one of this dynamic RAM and draw high the output drive strength that drives output.
Dragging down of above-mentioned this dynamic RAM of correction drives the o controller that draws high that the program of exporting comprises the following steps: this output generator of conducting; Read this dynamic RAM with this input comparator, produced an output valve; When this output valve is this first fixed value, downgrades this output drive strength that drags down driving output and when this output valve is this second fixed value, stop; And when this output valve was this second fixed value, accent increased this output drive strength that drags down driving output and stops when this output valve is this first fixed value.
Drive the o controller that drags down that the program of exporting comprises the following steps: this output generator of conducting and proofread and correct drawing high of this dynamic RAM; Read this dynamic RAM with this input comparator, produced an output valve; When this output valve is this second fixed value, downgrades this output drive strength that draws high driving output and when this output valve is this first fixed value, stop; And when this output valve was this first fixed value, accent increased this output drive strength that draws high driving output and stops when this output valve is this second fixed value.
By in the above-mentioned explanation as can be known, because the output driving strength correcting circuit and the method for a kind of dynamic RAM provided by the present invention, the direct input comparator of application memory control chip, read dynamic RAM, with the output valve that produces, and the high-gain comparer that need not add can accurately be proofreaied and correct the output drive strength of dynamic RAM, so circuit is easy to make and be easy to the carrying out of correction work.
Description of drawings
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, hereinafter special with preferred embodiment, and conjunction with figs., be described in detail as follows:
Fig. 1 is the output driving strength correcting circuit synoptic diagram of a kind of known dynamic RAM of expression;
Fig. 2 is the output driving strength correcting circuit synoptic diagram of a kind of dynamic RAM of expression preferred embodiment according to the present invention; And
Fig. 3 is a kind of output drive strength bearing calibration process flow diagram of expression preferred embodiment according to the present invention.
Accompanying drawing indicates explanation:
110 known output driving strength correcting circuit
111,218 steering logic elements
112, terminal on 113,212,213 chips
114,115 high-gain comparers
116,216 output generators
117,217 input comparators
120,220 dynamic RAM
121,221 draw high driving output
122,222 drag down driving output
123,223 drive strength are adjusted logic element
210 output driving strength correcting circuit
211 drive strength auto compensatng circuits
Logic element is adjusted in 219 outputs
214 draw high o controller
215 drag down o controller
S310～S375 process step
Embodiment
Please refer to shown in Figure 2ly, it is a kind of dynamic RAM and its output driving strength correcting circuit synoptic diagram of the preferred embodiment according to the present invention.Carrying out timing, we directly utilize the input comparator 217 as the data input to replace the high- gain comparer 114 and 115 that original Fig. 1 adds, and use reference voltage Vref to be set at 1/2nd of power source voltage Vcc, read output valve Z, therefore do not need reference voltage Voh and Vol as two kinds of differences of Fig. 1 and accuracy that must be very high, can make correction program be easier to carry out, and omission high-gain comparer 114 and 115 also can significantly reduce cost.
As shown in the figure, this output driving strength correcting circuit 210 comprises: logic element 219 and steering logic element 218 are adjusted in drive strength auto compensatng circuit 211, output, and the output generator 216 and the input comparator 217 of cooperation storer control chip (for example being the north bridge control chip in the chipset), carry out the correction of the output drive strength of dynamic RAM 220.Wherein, dynamic RAM 220 comprises equally drawing high and drives output 221, drags down and drive output 222, and draw high in order to adjustment and to drive output 221 and to drag down the drive strength that drives output 222 and adjust logic element 223, and terminal (ODT) 212 and 213 there is no effect on the chip shown in the figure when correction program carries out, and can cut off with suitable mechanism.
In this embodiment, it is 4 ohm of 18 ohm of plus-minuss with dragging down the probable value that drives output 222 that the drawing high of the dynamic RAM 220 that desire is proofreaied and correct drives output 221, that is scope is 14 ohm to 22 ohm.Therefore, we directly use one 18 ohm reference resistance Rcomp on the motherboard, be connected to drive strength auto compensatng circuit 211, produce the 18 ohm of corresponding down automatic compensating control signal PU* in a plurality of positions and DN* and adjust logic element 219 to output, output generator 216 then output is adjusted logic element 219 is further controlled output generator 216 more respectively with automatic compensating control signal PU* and DN* a plurality of metal oxide semiconductor transistors that draw high o controller 214, and whether the conducting of a plurality of metal oxide semiconductor transistors that drag down o controller 215 of output generator 216 (is represented with a P type and N type metal oxide semiconductor transistor respectively) herein, make and be adjusted into the drawing high o controller 214 and drag down the resistance that o controller 215 is produced respectively of output generator 216 identical with the resistance of reference resistance Rcomp.Therefore, output generator 216 draw high o controller 214 and the resistance that drags down o controller 215, can not be subjected to the influence of manufacturing process, supply voltage and temperature change.
In addition, because of output generator 216 was used by data output D_out originally, adjust logic element 219 controls in this output of serving as reasons and switch to drawing high driving output 221 and dragging down the correction program that drives output 222 of dynamic RAM 220, and use drawing high o controller 214 and dragging down o controller 215 of output generator 216.Wherein adjust logic element 219 as the data output and the output of the switching mechanism of correction program different time, can by with door, Sheffer stroke gate and or simple and easy logic gate such as door form.When switching to correction program, output adjustment logic element 219 does the time spent, the automatic compensating control signal PU* and the DN* that receive come corresponding control to draw high o controller 214 and the conducting that drags down o controller 215 and whether adjust the resistance output generator 216 of output generator 216 and draw high o controller 214 and drag down o controller 215.Otherwise, when if output adjustment logic element 219 switches to data output, then adjust logic element 219 and receive output data D_out with output, control drawing high o controller 214 and dragging down o controller 215 of output generator 216, and further affact input comparator 217, produce input data (D-in) as Fig. 1.
Input comparator 217 (is adjusted logic element 219 when output and is switched to data output except that doing data input use, output generator 216 receives makes data output D_out), be transformed under the correction program again, one input end of input comparator 217 then is connected to reference voltage Vref (be set at power source voltage Vcc 1/2nd), another input end is drawing high o controller 214 or dragging down o controller 215 and drive output 221 combinations dividing potential drop is provided with dragging down to drive output 222 or draw high by conducting then, make input comparator 217 produce an output Z to steering logic element 218, further the drive strength of control dynamic RAM 220 is adjusted logic element 223 again, output generator 216 draws high o controller 214 and drags down o controller 215 and proofread and correct drawing high of dynamic RAM 220 and drive output 221 or drag down the output drive strength that drives output 222.Because drawing high driving output 221 or dragging down the probable value that drives output 222 is 4 ohm of 18 ohm of plus-minuss, add that drawing high o controller 214 comes with the reference resistance Rcomp of the resistance that drags down o controller 215 according to 18 ohm, therefore make input comparator 217 admissible change detection window also for the scope of-4/ (18+18), significantly improved the noise permission to+4/ (18+18).
Please refer to a kind of output drive strength bearing calibration process flow diagram that Figure 3 shows that preferred embodiment according to the present invention.Certainly, before correction program carries out, output generator 216 draw high o controller 214 and the resistance that drags down o controller 215, can be, and be adjusted into 18 ohm by 18 ohm of reference resistance Rcomp of drive strength auto compensatng circuit 211 outsides.
In the S310 step, at first logic element 219 is adjusted in control output, to turn-off drawing high o controller 214 and dragging down o controller 215 of output generator 216, enter the S315 step then, to read drawing high driving output 221 and dragging down driving output 222 dividing potential drops of dynamic RAM 220 via input comparator 217, relatively more following with reference voltage Vref, produce output valve Z.
When output valve Z was 0, for example representative will begin to proofread and correct the output drive strength that drives output 222 that drags down of dynamic RAM 220.Then enter into the S320 step, conducting output generator 216 draw high o controller 214, drive output 222 effects with dragging down, enter the S325 step then, make input comparator 217 produce output valve Z.
When output valve Z is 0, the output drive strength of representing dragging down of dynamic RAM 220 to drive output 222 may be too high, so when entering the S330 step, adjust logic element 223 effects through steering logic element 218 and drive strength, to adjust the output drive strength that drives output 222 that drags down that reduces dynamic RAM 220.Then enter the S340 step,,, then repeat the step of S330 at 0 o'clock, just become 1 to stop trimming process up to output valve Z if output valve Z still is again to read output valve Z.At last, the output drive strength that drags down driving output 222 of dynamic RAM 220 will be adjusted to 18 ohm of desired desired values.
If at step S325, the output valve Z that reads is 1 o'clock, then representing dragging down of dynamic RAM 220 to drive the output drive strength of output 222 may be low excessively, so when entering the S335 step, adjust logic element 223 effects through steering logic element 218 and drive strength, to adjust the output drive strength that drives output 222 that drags down that increases dynamic RAM 220.Then, enter the S345 step, again read output valve Z,, then repeat the S335 step at 1 o'clock, transfer at 0 o'clock up to output valve Z and stop trimming process if output valve Z still is.At this moment, the output drive strength that drags down driving output 222 of dynamic RAM 220 will be adjusted to 18 ohm of desired desired values.
Otherwise when reading output valve Z in aforementioned S315 step and be 1, for example representative will begin to proofread and correct the output drive strength that drives output 221 that draws high of dynamic RAM 220.Then enter into the S350 step, conducting output generator 216 drag down o controller 215, enter the S355 step then, produce output valve Z with input comparator 117.When reading output valve Z and be 1, the output drive strength of representing drawing high of dynamic RAM 220 to drive output 221 may be too high, so when entering the S360 step, adjust the output drive strength that drives output 221 that draws high that reduces dynamic RAM 220.Then enter the S370 step again, again read output valve Z,, then repeat the S360 step at 1 o'clock, change 0 into up to the output valve Z that reads and stop trimming process if the output valve Z that reads still is.At this moment, the output drive strength that draws high driving output 221 of dynamic RAM 220 will be adjusted to 18 ohm of desired desired values.
If when step S355, output valve Z is 0 o'clock, then representing drawing high of dynamic RAM 220 to drive the output drive strength of output 221 may be low excessively, so enter the S365 step, adjusts the output drive strength that drives output 221 that draws high that increases dynamic RAM 220.Then, program enters the S375 step, again to read output valve Z, if the output valve Z that reads still is, then repeats the step of S365 at 0 o'clock, transfers 1 to up to output valve Z and stops trimming process.At this moment, the output drive strength that draws high driving output 221 of dynamic RAM 220 will be adjusted to 18 ohm of desired desired values.
By in the above-mentioned explanation as can be known, the present invention has following advantage at least:
1. the direct input comparator of application memory control chip reads the output valve of dynamic RAM, and the high-gain comparer that need not add, so circuit is easy to make.
2. because the application of drive strength auto compensatng circuit, so drawing high o controller and dragging down the resistance of o controller of output generator can not be subjected to the influence of manufacturing process, supply voltage and temperature change, and can accurately carry out correction.
3. the mobility scale of detection window rises to the scope of-4/ (18+18) to+4/ (18+18), makes the noise permission also improve.
In sum, though the present invention with preferred embodiment openly as above, right its is not in order to limit the present invention, any those skilled in the art, under the situation that does not break away from the spirit and scope of the present invention, can carry out various changes and modification, therefore scope of the present invention is as the criterion with the claim restricted portion that is proposed.
Claims (11)
1. an output driving strength correcting circuit is used for a dynamic RAM, comprising:
One drive strength auto compensatng circuit, according to a reference resistance, output one automatic compensating control signal;
Logic element is adjusted in one output, receives data output and this automatic compensating control signal one of in the two in order to control, exports;
One output generator when receiving this automatic compensating control signal, produces a corresponding correction resistance; And
One input comparator, an input end receives a reference voltage, and another input end is connected to output terminal and this dynamic RAM of this output generator, compares output valve in order to produce one, proofreaies and correct the output drive strength of this dynamic RAM.
2. output driving strength correcting circuit as claimed in claim 1, wherein this reference resistance is for using the resistance on the motherboard.
3. output driving strength correcting circuit as claimed in claim 1, wherein this output generator and input comparator are positioned on the north bridge control chip.
4. output driving strength correcting circuit as claimed in claim 1, wherein this output generator comprises that drawing high o controller and drags down o controller.
5. output driving strength correcting circuit as claimed in claim 4, wherein this draws high o controller and is made of a plurality of PMOS transistors, and this drags down o controller and is made of a plurality of nmos pass transistors.
6. output driving strength correcting circuit as claimed in claim 5, wherein this output generator is according to this automatic compensating control signal, produce corresponding correction resistance, the number that this automatic compensating control signal is controlled this PMOS transistor or nmos pass transistor conducting produces.
7. output driving strength correcting circuit as claimed in claim 1 also comprises a steering logic element, receives this comparison output valve, produces a control signal, adjusts the output drive strength of dynamic RAM.
8. output drive strength bearing calibration, use has one and proofreaies and correct an output generator and an input comparator of resistance, proofread and correct the output drive strength of a dynamic RAM, one input end of this input comparator connects a reference voltage, the other end is connected to this dynamic RAM and this output driver, comprises the following steps:
Turn-off this output generator;
Read this dynamic RAM with this input comparator, produced an output valve;
When this output valve is one first fixed value, proofreaies and correct one of this dynamic RAM and drag down the output drive strength that drives output; And
When this output valve is one second fixed value, proofreaies and correct one of this dynamic RAM and draw high the output drive strength that drives output.
9. output drive strength as claimed in claim 8 bearing calibration, wherein this first fixed value is a logic element 0, this second fixed value is a logic element 1.
10. output drive strength as claimed in claim 8 bearing calibration, the program that drives output that drags down of wherein proofreading and correct this dynamic RAM comprises the following steps:
This output generator of conducting draw high o controller;
Read this dynamic RAM with this input comparator, produced an output valve;
When this output valve is this first fixed value, downgrades this output drive strength that drags down driving output and when this output valve is this second fixed value, stop; And
When this output valve was this second fixed value, accent increased this output drive strength that drags down driving output and stops when this output valve is this first fixed value.
11. output drive strength as claimed in claim 8 bearing calibration, the program that drives output that draws high of wherein proofreading and correct this dynamic RAM comprises the following steps:
This output generator of conducting drag down o controller;
Read this dynamic RAM with this input comparator, produced an output valve;
When this output valve is this second fixed value, downgrades this output drive strength that draws high driving output and when this output valve is this first fixed value, stop; And
When this output valve was this first fixed value, accent increased this output drive strength that draws high driving output and stops when this output valve is this second fixed value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101149570A CN100454435C (en) | 2003-11-13 | 2003-11-13 | Output driving strength correcting circuit and method for DRAM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101149570A CN100454435C (en) | 2003-11-13 | 2003-11-13 | Output driving strength correcting circuit and method for DRAM |
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| Publication Number | Publication Date |
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| CN1545097A true CN1545097A (en) | 2004-11-10 |
| CN100454435C CN100454435C (en) | 2009-01-21 |
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| CNB2003101149570A Expired - Lifetime CN100454435C (en) | 2003-11-13 | 2003-11-13 | Output driving strength correcting circuit and method for DRAM |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100403290C (en) * | 2005-08-19 | 2008-07-16 | 威盛电子股份有限公司 | Adjustable termination resistor for integrated circuit chip |
| CN107888180A (en) * | 2016-09-30 | 2018-04-06 | 扬智科技股份有限公司 | The bearing calibration of System on Chip/SoC and its terminal impedance element |
| CN112543976A (en) * | 2018-08-21 | 2021-03-23 | 美光科技公司 | Drive strength calibration for multi-level signaling |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6445316B1 (en) * | 2000-09-29 | 2002-09-03 | Intel Corporation | Universal impedance control for wide range loaded signals |
| TW569534B (en) * | 2001-05-15 | 2004-01-01 | Via Tech Inc | Data transmission system using differential signals as edge alignment triggering signals and input/output buffers thereof |
-
2003
- 2003-11-13 CN CNB2003101149570A patent/CN100454435C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100403290C (en) * | 2005-08-19 | 2008-07-16 | 威盛电子股份有限公司 | Adjustable termination resistor for integrated circuit chip |
| CN107888180A (en) * | 2016-09-30 | 2018-04-06 | 扬智科技股份有限公司 | The bearing calibration of System on Chip/SoC and its terminal impedance element |
| CN107888180B (en) * | 2016-09-30 | 2021-06-01 | 扬智科技股份有限公司 | System chip and method for correcting terminal impedance element thereof |
| CN112543976A (en) * | 2018-08-21 | 2021-03-23 | 美光科技公司 | Drive strength calibration for multi-level signaling |
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| Publication number | Publication date |
|---|---|
| CN100454435C (en) | 2009-01-21 |
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Granted publication date: 20090121 |