CN1543089A - Power equalization implementing method for dedicated down channel and reference power calculating circuit - Google Patents
Power equalization implementing method for dedicated down channel and reference power calculating circuit Download PDFInfo
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Abstract
A realization method for balancing down special channel power includes computing a reference power, computing the modulus of CFN to the power balance regulation period. When the modulus is zero, it is determined to be the starting frame of the said period, in which, CFN is got from computing the formula CFN=(SFN-frame offset)mod 256 and SFN is a system frame number, frame offset is the frame offset downward from the upper layer signaling. In the effect period of the entire power balance regulation, the regulation values are summed to be compared with that of the reference power in each time slot so as to decide if the power regulation is continued which makes sure if the present frame is the starting one of a power balancing regulation period to realize accurate positioning.
Description
Technical field
The present invention relates to radio link power control, refer to method and reference power counting circuit that a kind of downlink dedicated channels power equalization is adjusted especially.
Background technology
Realize downlink dedicated channels power equalization adjustment function, at first will determine start frame.Power equalization enables to mean the startup of power equalization, the mould value that the startup of power equalization must be satisfied Connection Frame Number CFN (CFN:Connection Frame Number) and adjustment cycle equals zero, it is this condition of CFN modadjustment period=0, and CFN is relatively more difficult to the delivery calculating of power equalization adjustment cycle, present implementation SFN (System Frame Number, System Frame Number) low 8 bits come replaced C FN, so just need not high-rise configuration vertical shift parameter, simplified the calculating of CFN.And the starting point of power equalization has also been done the simplification processing, promptly after setting up, channel link just starts frame counter and time slot counter, come the cycle and the step-length of power controlling equilibrium with these two counters, acquiescence power equalization starting point is set up back first frame at channel link.Because reference power ∑ P in the power equalization
BalCalculating need use the power of last last time slot of adjustment cycle, so do not do equilibrium treatment in first power equalization adjustment cycle, power equalization works since second adjustment cycle.
The realization of power equalization circuit as shown in Figure 1.(balanced step-length is unit with the time slot during a power equalization step-length, this parameter value scope is 1-10, balanced step-length is equivalent to a minor cycle of a balanced cycle inside), adjustment amount summation to each time slot, the adjustment amount summation and the 1dB that obtain are compared, when with the time, continue during this step-length to adjust, otherwise just no longer power is adjusted less than 1dB; (the balanced cycle is unit with the frame, and this parameter value scope is 1-256, and a frame has 15 time slots) sues for peace sue for peace and reference power [(1-r) (P equally to the adjustment amount of each time slot during a power equalization cycle
Ref+ P
P-CPICH-P
Init)] relatively, when with less than [(1-r) (P
Ref+ P
P-
CPICH-P
Init)] time, in this cycle, continue to adjust, otherwise just no longer power is adjusted.
In processing procedure, need to finish two sum operation, first summation is that the balanced adjustment amount of each time slot in the preceding power equalization adjustment step-length scope of current time slots is sued for peace, be 1～10 time slot because power equalization is adjusted the step-length scope again, so, we can store the power equalization value of maximum ten time slots of 64 code channels successively with RAM, each address can be regarded a shift register as, then, selecting corresponding value according to power equalization adjustment step-length sums up, according to SFN power equalization adjustment cycle (1～256 frame) is carried out the result of delivery, when the delivery result is 0, the address ram unit is carried out zero clearing.Second summation is to all the power equalization adjusted values summations in the power adjustment cycle, when summation greater than [(1-r) (P
Ref+ P
P-CPICH-P
Init)] time, then in the time slot of this adjustment cycle back, do not carry out the power equalization adjustment owing to be that 64 code channels are multiplexing, during realization we deposit with 1 RAM 64 code channels the power equalization adjusted value with.The address assignment of the RAM of two sum operation and realization are as shown in Figures 2 and 3.
Owing to adopt low 8 bits of SFN to simplify the calculating of CFN, and the acquiescence power equalization is since the 0th frame, so CFN is that 8 bits that hang down with SFN carry out modulo operation to balanced adjustment cycle (1～256 frame) to the adjustment cycle delivery.During specific implementation, realize modulo operation with the 8bit counter.When receiving power equalization commencing signal and power adjustment cycle, begin counting, when count results equaled low 8 bit values of SFN, counter was again since 0 counting.When counting down to an adjustment cycle end, counter also will be again since 0 counting.
Summary of the invention
In view of replacing CFN with the SFN least-significant byte in the prior art, can bring the deviation of power equalization starting point, there is not accurately to realize the startup of power equalization, the present invention calculates CFN according to SFN and vertical shift (Frame offset), utilization flowing water divider calculates the mould value of CFN to the delivery of adjustment cycle, realizes the accurate control to the power equalization starting point.
The implementation method of a kind of downlink dedicated channels power equalization of the present invention comprises:
Calculate reference power;
Calculate the mould value of Connection Frame Number, when this mould value equals zero, be defined as the start frame of this power equalization adjustment cycle the power equalization adjustment cycle; Described Connection Frame Number CFN is calculated by formula CFN=(SFN-frameoffset) mod 256, and wherein SFN is a System Frame Number, and frame offset is vertical shift, is issued by top signaling;
During a power equalization step-length of this power equalization adjustment cycle, adjustment amount summation to each time slot, the total adjustment amount and the 1dB that obtain are compared, when with the time less than 1dB, in during this step-length follow-up time slot is continued to adjust, otherwise no longer follow-up time slot interior during this step-length is carried out the power adjustment;
In this power equalization adjustment cycle, power equalization adjustment amount to each time slot sums up, and relatively adjust the numerical values recited of total amount and reference power at each time slot, decide in this power equalization adjustment cycle whether follow-up time slot is carried out the power adjustment with this.
Described reference power ∑ P
BalComputing formula be: ∑ P
Bal=[(1-r) (P
Ref+ P
P-CPICH-P
Init)], parameter r in the formula, P
Ref+ P
P-CPICHBe to be issued by top signaling, wherein r is the decimal between 0～1, P
InitIt is last last time slot power of power equalization adjustment cycle.
According to said method, during a power equalization was adjusted step-length, total amount was adjusted in the equilibrium of only writing down in this adjustment step-length, adopts the register-stored of 64 * 4bits.
If adjust total amount less than reference power, and reference power is greater than zero, and then the power equalization amount is heightened power; If adjust total amount less than reference power, and reference power is less than zero, and then the power equalization adjustment amount is realized power is turned down.
The invention provides a kind of reference power counting circuit, in order to calculate the reference power of downlink dedicated channels, include two subtracters, a multiplier and a divider, these two subtracters are finished (100-r) and (P respectively
Ref+ P
P-CPICH-P
Init) calculating; Described two subtracters output result of calculation is given described multiplier, finishes (100-r) (P
Ref+ P
P-CPICH-P
Init) calculating; The result of calculation that described divider is finished multiplier is divided by 100 calculating, output reference power value.
Described divider adopts the shifter-adder circuit to realize the calculating of (1/128+1/512+1/4096), this shifter-adder circuit comprises shift register and adder, wherein shift register moves to right 7 and realizes 1/128 calculating, move to right 9 and realize 1/512 calculating, move to right 12 and realize 1/4096 calculating, realize addition by adder then.
The present invention provides a kind of flowing water divider circuit in addition, be used for calculating the mould value of the Connection Frame Number of downlink dedicated channels power equalization to the power equalization adjustment cycle, it is characterized in that: this flowing water divider circuit is provided with the intermediate object program that 9 cover registers are stored divider, and every cover register time division multiplexing.
The inventive method is by the accurate modulo operation of CFN to adjustment cycle, and whether judge present frame is the start frame of a power equalization adjustment cycle, compares with the fixing shortcut calculation of low 8 bits of SFN that uses, and has realized accurate location.
For the processing in the power equalization adjustment step-length, use registers group, only the RAM resource is effectively saved in the method meeting of storage adjustment total amount, optimizes sequential.
Because DSCH Downlink Shared Channel adopts the modulation power of the dedicated channel that accompanies, therefore utilize the circuit of the power equalization of downlink dedicated channels to realize, simplify the realization of the control function of power of DSCH Downlink Shared Channel equally, be easy to realize the power control process of DSCH Downlink Shared Channel.
Description of drawings
Fig. 1 is power equalization implementation structure figure in the prior art.
Fig. 2 is that the ram cell of adjusting summation in the step-length in the prior art distributes schematic diagram.
Fig. 3 is a ram cell control principle schematic diagram of adjusting summation in the step-length in the prior art.
Fig. 4 is embodiment of the invention reference power counting circuit figure.
Fig. 5 is an embodiment of the invention flowing water divider circuit schematic diagram.
Fig. 6 is an embodiment of the invention flowing water divider sequential chart.
Embodiment
The power equalization adjustment of downlink dedicated channels is to draw close to reference power for the power of balance Radio Link, obtains a correction value according to the descending power control procedure.In the design of WCDMA base station node B baseband modulation chip, power equalization is a very important function.It will be implemented in simultaneously in power equalization adjustment cycle (adjustment period) and the power equalization adjustment step-length (adjustment step) power is adjusted.Wherein the value of power equalization adjustment cycle is a unit with radio frames (radio frame), and the value that power equalization is adjusted step-length is a unit with time slot (slot).
After power equalization started, each time slot all can carry out a power adjustment, and unit of adjustment is 0.25dB, and the rule of adjustment is: the total adjustment amount in the whole power equalization adjustment cycle is no more than reference power ∑ P
Bal, a power equalization is adjusted the interior total adjustment amount of step-length and is no more than 1dB simultaneously, wherein ∑ P
Bal=[(1-r) (P
Ref+ P
P-CPICH-P
Init)].Parameter r, P
Ref+ P
P-CPICHBe to issue by top signaling, P
RefBe descending reference power (DL Reference Power), P
P-CPICHBe the power of Primary Common Pilot Channel (P-CPICH:Primary Common Pilot Channel), P
RefBe relative value, it is that power with Primary Common Pilot Channel is benchmark, so need be with P
RefAdd P
P-CPICHObtain absolute descending reference power.P
Ref+ P
P-CPICHValue between 0-176, in design, P
Ref+ P
P-CPICHBe to calculate then by software to deliver to chip internal as a configuration parameter.It is as follows that it calculates principle: [cell power (dBm)-(P
Ref+ PCPICH power)]/0.25, following formula is Configuration Values behind round, the amplitude limit as a result.P
InitIt is last last time slot power of power equalization adjustment cycle.
The moment that power equalization starts might not be the moment that power equalization enables, and concrete starting point must satisfy following rule: CFN mod adjustment period=0 that is to say that CFN can divide exactly the power equalization adjustment cycle.CFN is calculated by formula CFN=(SFN-frame offset) mod 256, and wherein SFN is System Frame Number (System Frame Number), and frame offset is vertical shift, is issued by top signaling equally.
Therefore, be no more than reference power at total adjustment amount of whole adjustment cycle, the total adjustment amount in whole adjustment step-length is no more than 1dB, and these two conditions must satisfy simultaneously, could adjust power.
According to above-mentioned, at first calculate reference power [(1-r) (P
Ref+ P
P-CPICH-P
Init)], because the resize ratio r of power equalization is a decimal between (0～1), considering the requirement of precision and the possibility that circuit is realized, we are with 101 the integer representatives (0.00～1.00) between (0～100), and are corresponding, in the end will be again divided by 100.Like this, we just can realize the operation of (1-r) with a simple subtraction circuit and division circuit.Consider the length of flowing water and the complexity of computing during realization, we have used a kind of shortcut calculation, promptly use (1/128+1/512+1/4096) to replace 1/100.So just can use shift register and adder to realize division function.The specific implementation circuit diagram of reference power as shown in Figure 4.Provided reference power ∑ P among the figure
BalAsk for ∑ P
Bal=[(1-r) (P
Ref+ P
P-CPICH-P
Init)], wherein r is as resize ratio, and value is between 0～1.
The calculating of CFN is fairly simple, as long as System Frame Number and vertical shift are done subtraction, it is just passable to get low 8 bits then.Because the vertical shift value is between 0 to 255, so CFN is a variable value, its delivery to adjustment cycle is the division of two variablees, realizes by simple count the prior art so can not resemble, and must use divider circuit.The modulation chip of whole downlink dedicated channels has adopted time-multiplexed processing method, handles 64 dedicated channels in 64 clock cycle respectively.So adopt the method for simply each channel all being used divider, will consume ample resources, and will bring sequence problem.Therefore design one 9 flowing water divider, after the each subtraction of this divider is finished, adopt a new cover register to store operation result.Original register continues the data of next channel of reception to be handled.The essence of flowing water divider is exactly that the intermediate object program that 9 cover registers are stored divider is set, and every cover register is 64 channel time division multiplexinges.
In hardware, divider is realized by subtraction, by the value in two registers is done subtraction, according to the positive and negative value that decides the merchant of difference.Because CFN is 8 bits, adding 1 bit symbol position is 9 bits, needs to do the value that all needs to upgrade after 10 subtractions and the each subtraction in the register so, promptly adopts new register to store new value.Therefore carrying out under the situation of power equalization simultaneously to 64 channels, each channel all has a cover divider so, (just have 64 cover dividers) and every cover divider all must 10 subtractions of promising storage renewal result's register, like this, the wasting of resources is just greatly.As can be seen from Figure 5 the resource of a cover divider comprises shifter0, shifter1 ..., shifter9, totally 10 shift registers, (145 bit) subor0, subor1 ..., subor9 is totally 10 registers (90 bit).64 covers just have 64 * (145+90)=15040 bits.It obviously is insufferable using so many register resources.(in Fig. 5, latch at every turn and all use register, thus shifter0, subor0, shifter1, these signals of subor1 all are registers.)
And the thought of flowing water divider is, a cover divider is set, and this cover divider is 64 channel sharings.Because 64 dedicated channels are wanted a shared cover divider, so for fear of conflict, just must adopt time division multiplexing mode.So-called time division multiplexing, the processing of 64 channels is carried out in 64 clock cycle successively exactly.The 1st clock cycle, divider receives the 0th channel, and (64 channels are since 0 counting, to 63) CFN and the value of adjustment cycle, begin to calculate both moulds, the 2nd clock cycle, divider receives the value of the CFN and the adjustment cycle of the 1st channel, begin to calculate both moulds, receive the CFN and the adjustment cycle of the 2nd channel at the 3rd clock cycle divider, begin to calculate both moulds ..., the 64th clock cycle, divider receives the CFN and the adjustment cycle of the 63rd channel, begins to calculate both moulds.Thereby realized 64 same set of dividers of channel time division multiplexing, only needed the register resources of 145+90 bit.
Can the intermediate object program of 64 channels required buffer memory when doing subtraction process be lost so? can not.This is because the 2nd clock cycle, when divider begins to receive the value of the CFN of the 1st channel and adjustment cycle, for 0 channel for, divider has calculated the poor of CFN and adjustment cycle, and the result has been preserved.If from Fig. 5, that is exactly, and when the 1st channel occupancy shifter0 and these two register resources of subor0, the 0th channel has been finished subtraction, special-purpose shifter1 and these two register resources of subor1.Therefore the intermediate object program of adjacent channel all can store, and can not lose, and be present in equally in the same set of divider, rather than 64 cover dividers.We can analyze equally, the 3rd clock cycle, divider begins the value of the CFN and the adjustment cycle of receive channel 2, the CFN of channel 2 and adjustment cycle take shifter0 and these two registers of subor0, channel 1 is then finished subtraction and taken shifter1 and these two registers of subor1 this moment, and channel then finishes for the second time that subtraction has taken shifter2 and these two registers of subor2 0 this moment.We can analyze any time, the operating position of each register resources according to this.Can find that therefrom each channel uses all registers in the divider successively, finish division arithmetic, why this just claims this reason that cover divider is the flowing water divider.
Fig. 5 has provided 64 channel flowing water dividers, and each channel sharing 9 cover register is finished 9 divide operations.The input of this 9 cover registers group is CFN and adjust period (adjustment cycle), and output is CFN modadjust period, and just CFN is divided by the remainder of adjustment cycle.
Fig. 6 has provided the sequential chart of 64 channel flowing water dividers, as we know from the figure, supposes in T0 moment dedicated channel 0 to obtain CFN and adjustment cycle; Then clap dedicated channel 1 at D1 and obtain CFN and adjustment cycle, the CFN and the adjustment cycle of dedicated channel 0 latch into register shifter0 and subor0 simultaneously, and finish subtraction and obtain result0; Clap dedicated channel 2 at D2 and obtain CFN and adjustment cycle, this moment, dedicated channel 1 latched CFN and adjustment cycle into register shiter0, and subor0, and finish subtraction and obtain result0, dedicated channel 0 is also finished computing, to be worth and deposit register shifter1 respectively in, subor1 and result1 Clap the mould value that just can calculate 0 liang of parameter of dedicated channel at D11.
After obtaining the value of CNF to the adjustment cycle delivery, just can judge the initial frame number of power equalization in conjunction with CNF itself, accurately locate beginning and end that power equalization is adjusted each adjustment cycle.In whole power equalization adjustment cycle scope, the power equalization adjustment amount is summed up, will adjust total amount and deposit RAM in.Judge that at each time slot of power equalization valid period whether this adjustment total amount is less than [(1-r) (P
Ref+ P
P-CPICH-P
Init)], if less than and [(1-r) (P
Ref+ P
P-CPICH-P
Init)] greater than zero, then the power equalization amount is heightened 0.25dB with power; If less than and [(1-r) (P
Ref+ P
P-CPICH-P
Init)] less than zero, then the power equalization adjustment amount is realized power is turned down 0.25dB.If adjusting total amount equals greater than [(1-r) (P
Ref+ P
P-CPICH-P
Init)], the power equalization adjustment amount then is zero, does not mean power is adjusted.
And for the equilibrium of adjusting in the step-length, if the adjustment amount of each time slot in the record step-length so just needs the RAM resource of 64 * 10bits, be 10 because adjust the step-length maximum occurrences.But adopt the balanced method of adjusting total amount in the whole adjustment step-length of record, just needn't store the adjustment amount of adjusting each time slot in the step-length, and only need use the register resources of 64 * 4bits.Do accumulation process at each time slot of the initial back of equilibrium to adjusting total amount, and will adjust equilibrium in the step-length and adjust total amount and make comparisons,, no longer carry out the equilibrium adjustment in during this step-length when adjustment total amount during more than or equal to 1dB with 1dB.Design only needs the interior total amount of adjusting of adjustment step-length of 64 dedicated channels of storage like this.Therefore compare with existing implementation, can effectively save resource.
In sum, the present invention is calculating reference power [(1-r) (P
Ref+ P
P-CPICH-P
Init)] time, suitably adopt shortcut calculation to guarantee the complexity that reduces resource and computing under the required precision satisfying, and introduce vertical shift (Frame offset), use divider to finish the computing of delivery, obtain accurate remainder, and satisfying 64 channel water operations simultaneously, multiplexing same set of register resources realizes time division multiplexing.Obtain the starting point of power equalization adjustment cycle by the remainder of divider output.
Claims (7)
1, a kind of implementation method of downlink dedicated channels power equalization is characterized in that comprising:
Calculate reference power;
Calculate the mould value of Connection Frame Number, when this mould value equals zero, be defined as the start frame of this power equalization adjustment cycle the power equalization adjustment cycle; Described Connection Frame Number CFN is calculated by formula CFN=(SFN-frameoffset) mod 256, and wherein SFN is a System Frame Number, and frame offset is vertical shift, is issued by top signaling;
During a power equalization step-length of this power equalization adjustment cycle, adjustment amount summation to each time slot, the total adjustment amount and the 1dB that obtain are compared, when with the time less than 1dB, in during this step-length follow-up time slot is continued to adjust, otherwise no longer follow-up time slot interior during this step-length is carried out the power adjustment;
In this power equalization adjustment cycle, power equalization adjustment amount to each time slot sums up, and relatively adjust the numerical values recited of total amount and reference power at each time slot, decide in this power equalization adjustment cycle whether follow-up time slot is carried out the power adjustment with this.
2, the implementation method of a kind of downlink dedicated channels power equalization as claimed in claim 1 is characterized in that: described reference power ∑ P
Ba1Computing formula be: ∑ P
Ba1=[(1-r) (P
Ref+ P
P-CPICH-P
Init)], parameter r in the formula, P
Ref+ P
P-CPICHBe to be issued by top signaling, wherein r is the decimal between 0～1, P
InitIt is last last time slot power of power equalization adjustment cycle.
3, the implementation method of a kind of downlink dedicated channels power equalization as claimed in claim 1 is characterized in that: during a power equalization was adjusted step-length, total amount was adjusted in the equilibrium of only writing down in this adjustment step-length, adopts the register-stored of 64 * 4bits.
4, as the implementation method of claim 1,2 or 3 described a kind of downlink dedicated channels power equalizations, it is characterized in that: if adjust total amount less than reference power, and reference power is greater than zero, and then the power equalization amount is heightened power; If adjust total amount less than reference power, and reference power is less than zero, and then the power equalization adjustment amount is realized power is turned down.
5, a kind of reference power counting circuit in order to calculate the reference power of downlink dedicated channels, includes two subtracters, a multiplier and a divider, and these two subtracters are finished (100-r) and (P respectively
Ref+ P
P-CPICH-P
Init) calculating; Described two subtracters output result of calculation is given described multiplier, finishes (100-r) (P
Ref+ P
P-CPICH-P
Init) calculating; The result of calculation that described divider is finished multiplier is divided by 100 calculating, output reference power value.
6, reference power counting circuit as claimed in claim 5, it is characterized in that: described divider adopts the shifter-adder circuit to realize the calculating of (1/128+1/512+1/4096), this shifter-adder circuit comprises shift register and adder, wherein shift register moves to right 7 and realizes 1/128 calculating, move to right 9 and realize 1/512 calculating, move to right 12 and realize 1/4096 calculating, realize addition by adder then.
7, a kind of flowing water divider circuit, be used for calculating the mould value of the Connection Frame Number of downlink dedicated channels power equalization to the power equalization adjustment cycle, it is characterized in that: this flowing water divider circuit is provided with the intermediate object program that 9 cover registers are stored divider, and every cover register time division multiplexing.
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|---|---|---|---|
| CNB031286755A CN100372405C (en) | 2003-04-29 | 2003-04-29 | Power equalization implementing method for dedicated down channel and reference power calculating circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031286755A CN100372405C (en) | 2003-04-29 | 2003-04-29 | Power equalization implementing method for dedicated down channel and reference power calculating circuit |
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| Publication Number | Publication Date |
|---|---|
| CN1543089A true CN1543089A (en) | 2004-11-03 |
| CN100372405C CN100372405C (en) | 2008-02-27 |
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|---|---|---|---|
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009012690A1 (en) * | 2007-07-26 | 2009-01-29 | Huawei Technologies Co., Ltd. | Method, communication system and device for obtaining connection frame number |
| CN103327634A (en) * | 2013-06-07 | 2013-09-25 | 大唐移动通信设备有限公司 | Method and device for scheduling time slot |
| CN104009801A (en) * | 2013-02-27 | 2014-08-27 | 中兴通讯股份有限公司 | Optical signal processing method and apparatus for optical network |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6628957B1 (en) * | 1999-07-16 | 2003-09-30 | Lucent Technologies Inc. | Synchronization of transmit power level settings for soft-handoff in wireless systems by the use of level constraints |
| JP3473555B2 (en) * | 2000-06-30 | 2003-12-08 | 日本電気株式会社 | Transmission power control system, control method, base station, control station, and recording medium |
| US6594499B1 (en) * | 2000-09-25 | 2003-07-15 | Telefonaktiebolaget Lm Ericsson (Publ) | Downlink power control in a cellular telecommunications network |
| CN1150704C (en) * | 2001-05-16 | 2004-05-19 | 华为技术有限公司 | Method and device for obtaining and maintaining system frame number and linking between frame numbers |
| CN1275404C (en) * | 2001-07-12 | 2006-09-13 | 中兴通讯股份有限公司 | Method for setting up initial down transmitting power according to circuit switch service |
-
2003
- 2003-04-29 CN CNB031286755A patent/CN100372405C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009012690A1 (en) * | 2007-07-26 | 2009-01-29 | Huawei Technologies Co., Ltd. | Method, communication system and device for obtaining connection frame number |
| CN104009801A (en) * | 2013-02-27 | 2014-08-27 | 中兴通讯股份有限公司 | Optical signal processing method and apparatus for optical network |
| CN104009801B (en) * | 2013-02-27 | 2016-09-07 | 中兴通讯股份有限公司 | The optical signal processing method of a kind of optical-fiber network and device |
| CN103327634A (en) * | 2013-06-07 | 2013-09-25 | 大唐移动通信设备有限公司 | Method and device for scheduling time slot |
| CN103327634B (en) * | 2013-06-07 | 2016-11-16 | 大唐移动通信设备有限公司 | Timeslot scheduling method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100372405C (en) | 2008-02-27 |
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