CN1531783A - Partitioned radio-frequency apparatus and associated methods - Google Patents
Partitioned radio-frequency apparatus and associated methods Download PDFInfo
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- CN1531783A CN1531783A CNA028048555A CN02804855A CN1531783A CN 1531783 A CN1531783 A CN 1531783A CN A028048555 A CNA028048555 A CN A028048555A CN 02804855 A CN02804855 A CN 02804855A CN 1531783 A CN1531783 A CN 1531783A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/26—Circuits for superheterodyne receivers
- H04B1/28—Circuits for superheterodyne receivers the receiver comprising at least one semiconductor device having three or more electrodes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/403—Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency
- H04B1/406—Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency with more than one transmission mode, e.g. analog and digital modes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B15/00—Suppression or limitation of noise or interference
- H04B15/02—Reducing interference from electric apparatus by means located at or near the interfering apparatus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B15/00—Suppression or limitation of noise or interference
- H04B15/02—Reducing interference from electric apparatus by means located at or near the interfering apparatus
- H04B15/04—Reducing interference from electric apparatus by means located at or near the interfering apparatus the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2215/00—Reducing interference at the transmission system level
- H04B2215/064—Reduction of clock or synthesizer reference frequency harmonics
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- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Noise Elimination (AREA)
- Transceivers (AREA)
- Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
Abstract
Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced.
Description
Technical field
The present invention relates to radio frequency (RF) receiver and transceiver.More particularly, the present invention relates to (i) high-performance RF receiver or transceiver circuit are divided into circuit part (circuitpartition) so that reduce the method for the disturbing effect in the circuit part, and circuit and the agreement of (ii) being convenient to the interface between circuit part.
Background technology
The surge of mobile radio and phone application and the universal market demand that has caused communication system with low cost, low-power and form factor radio frequency (RF) transceiver.Therefore, nearest research has concentrated on and has used low-cost complementary metal oxide semiconductors (CMOS) (CMOS) technology that single-chip transceiver is provided.Present research has concentrated in single integrated circuit (IC) RF is provided transceiver.About around the integrated project of RF transceiver and the discussion of problem, referring to Jacques C.Rudell etc., Recent Developemnts inHigh Integration Multi-Standard CMOS Transceivers for PersonalCommunication System, INVITED PAPER AT THE 1998INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS, MONTERERY, CALIFORNIA; Asad A.Abidi, CMOS WirelessTransceivers:The New Wave, IEEE COMMUNICATION MAG., Aug.1999, at 119; Jan Crol ﹠amp; Michael S.J.Steyaert, 45 IEEETRANSACTIONS ON CIRCUITS AND SYSTEM-II:ANALOG ANDDIGITAL SIGNAL PROCESSING 269 (1998); And Jacques C.Rudell etc., A1.9-GHz Wide-Band IF Double Conversion CMOS Receiver forCordless Telephone Applications, 32 IEEE J.OF SOLID-STATECIRCUITS 2071 (1997), all the elements are incorporated herein by reference.
The integrated of transceiver circuit is not insignificant problem, because it must consider the requirement of transceiver circuit and the communication standard of control transceiver operation.From the viewpoint of transceiver circuit, the RF transceiver generally includes and is easy to each other and the noise between external source and disturb responsive sensitive compressible members.Transceiver circuit is integrated into an integrated circuit will increases the weight of interference in each piece of transceiver circuit.In addition, the communication standard of control RF transceiver operation has outline a cover requirement of noise, intermodulation, blocking performance, power output and spectral emission to transceiver.Unfortunately, also do not develop and to satisfy high-performance RF receiver or transceiver, for example, be used in the method for all the problems referred to above in the RF transceiver in honeycomb or the phone application.Therefore, exist in the needs of the technology of separation that low-cost, low form factor RF transceiver is provided in the performance application of cellular handset for example and integrated RF receiver or transceiver.
Summary of the invention
The invention provides and be used to separate radio frequency (RF) device, for example, the technology of receiver or transceiver.In one embodiment, the RF device comprises first circuit part, and this first circuit part comprises the receiver analog circuit that is configured to generate from analog radio-frequency signal the digital received signal.This RF device also comprises the second circuit part, and this second circuit partly comprises the digital receiver circuit that is configured to accept this digital received signal.Separate first and second circuit parts to be convenient to reduce the disturbing effect between first circuit part and second circuit part.
In another embodiment, RF transceiver according to the present invention comprises first circuit part, and this first circuit part comprises the receiver analog circuit, and it is configured to the RF signal of accepting to receive and at least one digital output signal is provided.This first circuit part also comprises transmitter circuitry, and it is configured to receive at least one and sends input signal and transmission RF is provided signal.The RF transceiver also comprises the second circuit part, and this second circuit partly comprises local oscillator circuit, and it is configured to accept reference signal.This local oscillator circuit further is configured to provide radio frequency (RF) signal to the receiver analog circuit.Separate first circuit part and second circuit part to be convenient to reduce the disturbing effect between first circuit part and second circuit part.
Another aspect of the present invention also relates to separates RF device, for example method of receiver and transceiver.In one embodiment, this method comprises provides first circuit part that comprises the receiver analog circuit, and utilizes the receiver analog circuit to come to produce the digital received signal from analog rf signal.This method also comprises provides the second circuit that comprises digital receiver circuit part, and utilizes this digital receiver circuit to accept the digital received signal.At last, this method comprises that separation first and second circuit parts are to be convenient to reduce the disturbing effect between first circuit part and second circuit part.
In another embodiment, the method for separation RF transceiver comprises provides first circuit part that comprises receiver analog circuit and transmitter circuitry.This method further comprises to be utilized this receiver analog circuit to accept the RF signal that is received and at least one digital output signal is provided, and utilizes this transmitter circuitry to receive at least one emission input signal and the transmitting RF signal is provided.This method also comprises provides the second circuit that comprises local oscillator circuit part, and utilizes this local oscillator circuit to accept reference signal, and radio frequency (RF) signal is offered the receiver analog circuit.At last, this method comprises separates first circuit part and second circuit part, to be convenient to reduce the disturbing effect between first circuit part and second circuit part.
Description of drawings
Accompanying drawing only example illustrates exemplary embodiment of the present invention, does not therefore limit its scope.The invention disclosed principle makes them itself produce other equivalent embodiment.In the drawings, the same numbers that is used among several figure is represented identical, similar or equivalent function, element or piece.
The explanation of Fig. 1 example comprises the block diagram in conjunction with the RF transceiver of the radio circuit of baseband processor circuit operation.
Fig. 2 A represents the RF transceiver circuit of the separation according to the present invention.
Fig. 2 B describes another embodiment of the RF transceiver circuit of separating according to the present invention, and wherein the standard signal generator circuit is present in the identical circuit part or circuit block with the digital receiver circuit.
Another embodiment of the RF transceiver circuit that the explanation of Fig. 2 C example is separated according to the present invention, wherein the standard signal generator circuit is present in the baseband processor circuit.
Fig. 2 D represents another embodiment of the R transceiver circuit of separation according to the present invention, and wherein the digital receiver circuit is present in the baseband processor circuit.
Interference mechanism in each piece of Fig. 3 example explanation RF transceiver, this interference mechanism is attempted to overcome, reduces or minimized to the embodiments of the invention among Fig. 2 A-2D of the RF transceiver that description is separated according to the present invention.
Fig. 4 represents the more detailed block diagram of the RF transceiver circuit of separation according to the present invention.
The explanation of Fig. 5 example is used to separate the another kind of technology of RF transceiver circuit.
Fig. 6 represents to be used to separate the another kind of technology of RF transceiver circuit.
Fig. 7 describes the more detailed block diagram of the RF transceiver circuit of separating according to the present invention, and wherein the digital receiver circuit is present in this baseband processor circuit.
The more detailed block diagram of the multi-band RF transceiver circuit that the explanation of Fig. 8 example is separated according to the present invention.
Fig. 9 A is illustrated in the block diagram according to the embodiment of digital receiver circuit in the RF transceiver of the present invention and the interface between the receiver analog circuit.
Fig. 9 B is described in the block diagram according to another embodiment of baseband processor circuit in the RF transceiver of the present invention and the interface between the receiver analog circuit.
Figure 10 example explanation has the receiver analog circuit that is configured to serial line interface and the more detailed block diagram of the interface between the digital receiver circuit.
Figure 11 A represents to have the more detailed block diagram of the embodiment of the receiver analog circuit of interface of data of being configured to and interface clock signal and the interface between the digital receiver circuit.
Figure 11 B example explanation comprises the block diagram of embodiment of the delay element circuit of the clock driver that is connected in series with the clock receiver circuit.
Figure 12 describes the schematic diagram be used for connecting according to the embodiment of the signal drive circuit of receiver analog circuit of the present invention and digital receiver circuit.
The explanation of Figure 13 example is used for connecting the schematic diagram according to the signal receiver embodiment of circuit of receiver analog circuit of the present invention and digital receiver circuit.
Figure 14 represents to can be used to connect the schematic diagram according to another signal drive circuit of receiver analog circuit of the present invention and digital receiver circuit.
Embodiment
The present invention attempts to separate the RF device so that high integrated, high-performance, low cost and low form factor RF solution are provided.RF device according to the present invention can be used in the high performance communication system.More particularly, the present invention partly relates to the method that minimizes, reduces or overcome the disturbing effect in each piece of RF receiver or transceiver and separates RF receiver or transceiver circuit, satisfies the standard-required of control RF receiver or transceiver performance simultaneously.These standards comprise enhanced data (EDGE) and the GPRS (GPRS) that gsm (GSM), Personal Communications Services (PCS), Digital Cellular System (DCS), GSM develop.Therefore, RF receiver or the transceiver circuit separated according to the present invention overcome the disturbing effect that will be present in high integrated RF receiver or the transceiver, satisfy control criterion with low-cost and low form factor simultaneously.Description of the invention relates to circuit part and circuit block convertibly.
Fig. 1 represents the general block diagram according to RF transceiver circuit 100 of the present invention.RF transceiver circuit 100 comprises the radio circuit 110 that is coupled to antenna 130 through two-way signaling path 160.When transceiver was in sending mode, radio circuit 110 provided RF to send signal through two-way signaling path 160 to antenna 130.When being in receiving mode, radio circuit 110 receives the RF signal through two-way signaling path 160 from antenna 130.
Radio circuit 110 also is coupled to baseband processor circuit 120.This baseband processor circuit 120 comprises digital signal processor (DSP).In addition, or except that DSP, baseband processor circuit 120 can comprise the signal processor of the other types that those skilled in the art understands.Radio circuit 110 is handled from the RF signal of antenna 130 receptions and with received signal 140 and is offered baseband processor circuit 120.In addition, radio circuit 110 is accepted to send input signal 150 and this RF is sent signal from baseband processor 120 and offers antenna 130.
Fig. 2 A-2D represents each embodiment of the RF transceiver circuit of separation according to the present invention.Fig. 3 and following additional description thereof will make that the consideration of the separation that produces the RF transceiver circuit shown in Fig. 2 A-2D is clearer.The embodiment 200A of the RF transceiver circuit that the explanation of Fig. 2 A example is separated according to the present invention.Except that in conjunction with the described element of Fig. 1, RF transceiver 200A comprises antenna interface circuit 202, receiver circuit 210, transmitter circuitry 216, standard signal generator circuit 218 and local oscillator circuit 222.
Standard signal generator circuit 218 produces reference signal 220 and this signal is offered local oscillator circuit 222 and digital receiver circuit 212.Reference signal 220 preferably includes clock signal, yet as required, it also can comprise other signals.Local oscillator circuit 222 produces RF local oscillator signal 224, provides it to receiver analog circuit 208 and transmitter circuitry 216.Local oscillator circuit 222 also produces transmitter intermediate frequency (IF) local oscillator signal 226 and this signal is offered transmitter circuitry 216.Note, in RF transceiver according to the present invention, receiver analog circuit 208 mainly comprises the analog circuit except that some numerals or mixed mode circuit usually, for example, these numerals or mixed mode circuit comprise analog to digital converter (ADC) circuit and the receiver analog circuit is provided and the digital receiver circuit between the circuit of interface, as described below.
In sending mode, baseband processor circuit 120 will send input signal 150 and offer transmitter circuitry 216.Transmitter circuitry 216 uses RF local oscillator signal 224 and transmitter IF local oscillator signal 226 to handle this transmission input signal 150 and this result is sent RF signal 206 and offers antenna interface circuit 202.As required, antenna interface circuit 202 can further be handled this transmission RF signal, and this consequential signal is offered antenna 130, is used for propagating into transmission medium.
Fig. 2 B represents the embodiment 200B of the RF transceiver circuit of separation according to the present invention.Embodiment 200B has the circuit layout identical with the embodiment 200A of Fig. 2 A.Yet the separation of embodiment 200B is different from the separation of embodiment 200A.Similar with embodiment 200A, embodiment 200B has three circuit parts (or circuit block).In embodiment 200B first with tertiary circuit part and embodiment 200A in first similar with the tertiary circuit part.Yet the second circuit part 230 among the embodiment 200B also comprises standard signal generator 218 except that digital receiver circuit 212.As among the embodiment 200A, embodiment 200B is separated to be convenient to reduce by three disturbing effects in the circuit part.
The explanation of Fig. 2 C example is by the embodiment 200C of the deformation construction of the embodiment 200A among Fig. 2 A.Embodiment 200C represents as required, standard signal generator 218 can be placed in the baseband processor circuit 120.Standard signal generator 218 is placed on avoids discrete standard signal generator 218 in the baseband processor circuit 120 or comprise the other integrated circuit of this standard signal generator 218 or the needs of module.Embodiment 200C has the separation identical with embodiment 200A, and operation in a similar manner.
Notice that Fig. 2 A-2C represents as the receiver circuit 210 of piece so that describe embodiment among those figure.In other words, comprise the describe, in general terms of the piece formation of the receiver circuit 210 among Fig. 2 A-2C to the receiver circuit in the RF transceiver shown in Fig. 2 A-2C, rather than circuit part or circuit block.
Fig. 2 D represents the embodiment 200D of the RF transceiver of separation according to the present invention.RF transceiver operation among Fig. 2 D and the transceiver-like shown in Fig. 2 A are seemingly.Yet embodiment 200D realizes the economy of adding by digital receiver circuit 212 is included in the baseband processor circuit 120.As an alternative, whole digital receiver circuit 212 can be integrated on the identical integrated circuit (IC) apparatus that comprises baseband processor circuit 120.Notes, can use software (or firmware), hardware, or the combination of software (or firmware) and hardware realizes the function of the digital receiver circuit 212 in the baseband processor circuit 120 that arrives as skilled in the art will appreciate is such.Notice also that simultaneously similar with the embodiment 200C shown in Fig. 2 C, the baseband processor circuit 120 among the embodiment 200D also can comprise standard signal generator 218 as required.
The separation of embodiment 200D comprises two circuit parts (or circuit block).First circuit part 214 comprises receiver analog circuit 208 and transmitter circuitry 216.Second circuit partly comprises local oscillator circuit 222.Separate first and second circuit parts to be convenient to reduce the disturbing effect between them.
Fig. 3 represents to cause typical R F transceiver, for example, and each piece in the transceiver shown in Fig. 2 A or the mechanism of the interference in the element.Notice that the path of representing with the arrow among Fig. 3 is represented interference mechanism rather than the required path in each interior piece of transceiver.An interference mechanism is to be caused by the reference signal 220 that preferably includes clock signal (seeing Fig. 2 A-2D).In a preferred embodiment, the standard signal generator circuit produces the clock signal of the frequency that can have 13MHz (GSM clock frequency) or 26MHz.If standard signal generator produces the clock signal of 26MHz, then according to RF transceiver of the present invention preferably with this signal divided by 2 to produce the main system clocks of 13MHz.This clock signal generally includes the potential pulse with many Fourier (Fourier) progression harmonic wave.This Fourier progression harmonic wave expands to many levels of clock signal frequency.But these harmonic wave interference receiver analog circuits 208 (for example, low noise amplifier, or LNA), local oscillator circuit 222 (for example, condensating synthesizering circuit), and transmitter circuitry 216 (for example, transmitter voltage controlled oscillator, or VCO).Fig. 3 represents these interference sources as interference mechanism 360,350 or 340.
The sending mode in the GSM specification and the timing of receiving mode help to alleviate the potential interference between receiver reception path circuitry and its transmission path circuit.The GSM specification is used time division duplex (TDD).According to the TDD agreement, the inactive transmission path circuit of transceiver is in the receiving mode of operation simultaneously, and vice versa.Therefore, Fig. 3 does not demonstrate the interference mechanism of 208 of transmitter circuitry 216 and digital receiver circuit 212 or receiver analog circuits.
As the explanation of Fig. 3 example, there is interference mechanism at other pieces of local oscillator circuit 222 and RF transceiver or each of parts.Therefore, for reducing disturbing effect, preferably local oscillator circuit 222 and other transceiver block shown in Fig. 3 are separated according to RF transceiver of the present invention.Yet, note in some cases, as required, part or all of local oscillator circuit can be included in the identical circuit part (for example, the circuit part 214 among Fig. 2 A-2D) that comprises receiver analog circuit and transmitter circuitry.Usually, the voltage controlled oscillator in the local oscillator circuit (VCO) causes the interference with other sensitive circuit elements pieces (for example, receiver analog circuit) by undesirable coupling mechanism.If those coupling mechanisms can be relieved to the performance characteristic of RF transceiver in specifying application is acceptable degree, so, local oscillator circuit can be included in the circuit part identical with transmitter circuitry with the receiver analog circuit.Perhaps,, other parts of local oscillator circuit can be included in the circuit part that comprises receiver analog circuit and transmitter circuitry, but the VCO circuit is got rid of outside this circuit part if the VCO circuit produces unacceptable interference level.
For reducing the influence of interference mechanism 310, RF transceiver according to the present invention is separated receiver analog circuit 208 and digital receiver circuit 212.Because according to the transmitter circuitry 216 of GSM specification and the mutually exclusive operation of receiver analog circuit 208, transmitter circuitry 216 can be present in the identical circuit part (or circuit block) with receiver analog circuit 208.The transmitter circuitry 216 and the receiver analog circuit 208 that are placed in the identical circuit part produce generally more integrated RF transceiver.RF transceiver shown in Fig. 2 A-2D adopts the isolation technique of the benefit of the interference mechanism in each transceiver elements of utilizing above-mentioned analysis.For further reducing the disturbing effect in each circuit part or the circuit block, also can use differential signal to make each circuit part or circuit block coupled to each other according to RF transceiver of the present invention.
Fig. 4 represents the more detailed block diagram of the embodiment 400 of the RF transceiver of separation according to the present invention.Transceiver comprises receiver analog circuit 408, digital receiver circuit 426, and transmitter circuitry 465.In receiving mode, antenna interface circuit 202 offers filter circuit 403 with RF signal 401.Filter circuit 403 will offer receiver analog circuit 408 through the RF of filtering signal 406.Receiver analog circuit 408 comprises low-converter (being frequency mixer) circuit 409 and analog to digital converter (ADC) circuit 418.Down-converter circuit 409 will be mixed with the RF local oscillator signal 454 that receives from local oscillator circuit 222 through the RF of filtering signal 406.Down-converter circuit 409 offers adc circuit 418 with homophase analog down signal 412 (that is I channel signal) and orthogonal simulation down-conversion signal 415 (that is Q channel signal).
When transmitter circuitry 465 was calibrated and adjusted its each parts, the analog circuits in the transmitter circuitry 465 powered up and begin and regulate.When transmitter circuitry 465 had been finished the calibration its internal circuit, digital receiver circuit 426 was opened switch 492, thereby forbids reference signal 220 is offered transmitter circuitry 465.At this point, transmitter circuitry can make the power amplifier circuit 487 in the transmitter circuitry 465 power up.The RF transceiver enters the sending mode of operation subsequently and begins and sends.
Notice that be overall, schematic purpose, Fig. 4 is described as simple switch with switch 492.Can use various devices to realize the function of controlled switch 492, for example, semiconductor switch, gate or the like, as understood by those skilled in the art.Note, be present in the digital receiver circuit 426, as required, can make switch be positioned at other positions although Fig. 4 is shown switch 492.Switch 492 is placed on the harmonic wave that helps in the digital receiver circuit 426 to be generated by switching circuit is only limited to digital receiver circuit 426.
Notice that the embodiment 400 shown in Fig. 4 uses analog to digital-analog signal channel in its receiver section.In other words, adc circuit 418 becomes digital signal with analog signal conversion, so that further handle, and changes back analog signal by DAC circuit 445 afterwards.Use this signal specific path according to RF transceiver of the present invention owing to following reason.At first, adc circuit 418 is avoided and need on the analog interface with high relatively dynamic range signal be propagated into digital receiver circuit 426 from receiver analog circuit 408.The analog interface of the digital interface that comprises an in-phase digital received signal 421 and an orthogonal digital received signal 424 relative high dynamic range than having more is not subject to the influence of noise or interference.
The second, the RF transceiver among Fig. 4 uses DAC circuit 445 to keep and the interface compatibility that is commonly used to communicate by letter with the baseband processor circuit in the RF transceiver.According to these interfaces, baseband processor receives simulation rather than digital signal from the reception path circuitry in the RF transceiver.In the RF of the specification that satisfies those interfaces transceiver, digital receiver circuit 426 offers baseband processor circuit 120 with analog signal.Digital receiver circuit 426 uses DAC circuit 445 that analog signal (that is, homophase analog receiving signal 448 and orthogonal simulation received signal 451) is offered baseband processor circuit 120.DAC circuit 445 allows programming same-phase level and full scale voltage, and it can change in different baseband processor circuit.
The 3rd, to compare with the simulation solution, analog to digital-analog signal channel can cause the circuit size and the area (for example, the area that takies) that reduce in integrated circuit (IC) apparatus, thereby reduces cost.The 4th, digital circuit provides better repeatability, is easy to test relatively, and has stronger operability than its analog counterpart.The 5th, digital circuit and comparable analog circuit compare power supply voltage variation, variations in temperature or the like and have littler dependence.
The 6th, baseband processor circuit 120 generally includes the programmable digital circuit, and if necessary, the function of digital circuit can be included in the digital receiver circuit 426.The 7th, digital circuit allows more accurate signal processing in receiving path, for example, and filtering signals.The 8th, digital circuit allows more efficient signal processing.At last, digital circuit allows the easier use of user to provide the DAC circuit more able to programme and the PGA circuit of signal processing in receiving path.For benefiting from analog to digital-analog signal channel, RF transceiver according to the present invention (for example will hang down the IF signal, be used for the 100KHz that GSM uses) be used in their reception path circuitry, because use higher IF frequency can cause more high performance demands to ADC in this path and DAC circuit.Low IF architecture also alleviates pix carrier controls consumption, and this allows integrated digital filter circuits 436 on the chip.In addition, use digital down converter circuit 427 and digital filter circuit 436 in the received signal path, to realize digital IF path according to RF transceiver of the present invention.Numeral IF architecture is convenient to realize the digital interface between digital receiver circuit 426 and the receiver analog circuit 408.
If digital receiver circuit 426 does not need the general-purpose simulation interface compatibility with baseband processor, then can remove DAC circuit 445, and if necessary, can use digital interface with baseband processor circuit 120.In fact, with RF transceiver-like shown in Fig. 2 D seemingly, can use hardware, software, or the combination of hardware and software comes the function of realization digital receiver circuit 426 baseband processor circuit 120 in.Under this kind situation, the RF transceiver will comprise two circuit parts (or circuit block).First circuit part (or circuit block) 407 will comprise receiver analog circuit 408 and transmitter circuitry 465.Second circuit part (or circuit block) will comprise local oscillator circuit 222.Note, with the RF transceiver-like shown in Fig. 2 C seemingly, if necessary, the function of standard signal generator 218 can be included in the baseband processor circuit 120.
Available other modes are separated RF transceiver shown in Figure 4.The other separation of the RF transceiver of Fig. 5 and 6 example key diagrams 4.Fig. 5 represents to comprise the embodiment 500 of the RF transceiver of three circuit parts (or circuit block).First circuit part comprises receiver analog circuit 408.Second circuit part 505 comprises digital receiver circuit 426 and transmitter circuitry 465.As above mentioned, the GSM specification provides alternative RF transceiver operation with transmission and receiving mode.Separation shown in Figure 5 utilizes the GSM specification by digital receiver circuit 426 and transmitter circuitry 465 are included in the second circuit part 505.Tertiary circuit partly comprises local oscillator circuit 222.Best, first, second and tertiary circuit part are present in respectively in the integrated circuit (IC) apparatus.Similar with the embodiment 400 of Fig. 4, the embodiment 500 among Fig. 5 uses differential signal in the case of any possible so that further reduce disturbing effect in each circuit part.
Fig. 6 represents that the another kind of RF transceiver substitutes separation.Fig. 6 represents to comprise the embodiment 600 of the RF transceiver of three circuit parts (or circuit block).First circuit part 610 comprises the receiver analog circuit, that is, and and down-converter circuit 409, and transmitter circuitry 465.Second circuit part 620 comprises adc circuit 418, and the digital receiver circuit, that is, and and digital down converter circuit 427, and digital filter circuit 436 and DAC circuit 445.Tertiary circuit partly comprises local oscillator circuit 222.Best, first, second and tertiary circuit part are present in respectively in the integrated circuit (IC) apparatus.Similar with the embodiment 400 of Fig. 4, the embodiment 600 of Fig. 6 uses differential signal in the case of any possible so that further reduce disturbing effect in each circuit part.
Fig. 7 represents the modification of RF transceiver shown in Figure 4.The embodiment 700 of the RF transceiver that the explanation of Fig. 7 example is separated according to the present invention.Notice that for for purpose of brevity, Fig. 7 does not clearly represent receiver analog circuit 408, transmitter circuitry 465, and the details of digital receiver circuit 426.Receiver analog circuit 408, transmitter circuitry 465 and digital receiver circuit 426 comprise with Fig. 4 in their corresponding counterparts shown in the similar circuit of circuit.With the RF transceiver-like shown in Fig. 2 D seemingly, the embodiment 700 of Fig. 7 represents that baseband processor 120 wherein comprises the RF transceiver of the function of digital receiver circuit 426.Baseband processor circuit 120 can use the combination of hardware, software or hardware and software to realize the function of digital receiver circuit 426.
Because embodiment 700 is included in the function of digital receiver circuit 426 in the baseband processor circuit 120, so its two circuit part (or circuit block).First circuit part 710 comprises receiver analog circuit 408 and transmitter circuitry 465.Second circuit partly comprises local oscillator circuit 222.Note, with the RF transceiver-like shown in Fig. 2 C seemingly, if necessary, also the function of standard signal generator 218 can be included in the baseband processor circuit 120.
Fig. 8 represents the embodiment 800 of the multi-band RF transceiver of separation according to the present invention.Best, the RF transceiver among Fig. 8 is operated in GSM (925 to 960MHz), PCS (1930 to 1990MHz) and DCS (1805 to 1880MHz) frequency band.The same with the RF transceiver among Fig. 4, the RF transceiver among Fig. 8 uses low IF architecture.Embodiment 800 comprises receiver analog circuit 839, digital receiver circuit 851, transmitter circuitry 877, local oscillator circuit 222 and standard signal generator circuit 218.Local oscillator circuit 222 comprises RF phase-locked loop (PLL) circuit 840 and intermediate frequency (IF) PLL circuit 843.RF PLL circuit 840 produces the RF local oscillator, or RF LO signal 454, and IF PLL circuit 843 produces IF local oscillator or IF LO signal 457.
Following table 1 is illustrated in during the receiving mode, is used for the optimized frequency of RF local oscillator signal 454:
Table 1
| Frequency band | RF local oscillator frequency (MHz) |
| ????GSM | ????1849.8-1919.8 |
| ????DCS | ????1804.9-1879.9 |
| ????PCS | ????1929.9-1989.9 |
| All frequency bands | ????1804.9-1989.9 |
Following table 2 has been listed during emission mode, is used for the optimized frequency of RF local oscillator signal 454:
Table 2
| Frequency band | RF local oscillator frequency (MHz) |
| ????GSM | ????1279-1314 |
| ????DCS | ????1327-1402 |
| ????PCS | ????1423-1483 |
| All frequency bands | ????1279-1483 |
During receiving mode, IF local oscillator signal 457 preferably has the frequency of 100kHz.In a preferred embodiment, during sending mode, IF local oscillator signal 457 preferably has the frequency between 383MHz and the 427MHz.Yet, it should be noted that if necessary, can use other frequencies that are used for RF and IF local oscillator signal 454 and 457.
Although as understood by those skilled in the art, but other signals used, but standard signal generator 218 provides the reference signal 220 that preferably includes clock signal.In addition, transmitter circuitry 877 preferably is used for the high-end injection (high-sideinjection) of GSM frequency band and is used for DCS and the injection of the low side of PCS frequency band.
It is as follows to receive the path circuitry operation.Filter circuit 812 is accepted GSM RF signal 803, DCS RF signal 806 and PCS RF signal 809 from antenna interface circuit 202.Although if necessary, but the filter of other types and quantity used, but filter circuit 812 preferably comprises each surface acoustic wave (SAW) filter that is used for three frequency bands.Filter circuit 812 will be through the GSM of filtering RF signal 815, offer low noise amplifier (LNA) circuit 824 through the DCS of filtering RF signal 818 and through the PCS of filtering RF signal 821.LNA circuit 824 preferably has programmable-gain, and partly provides programmable-gain for receiving path circuitry.
LNA circuit 824 offers down-converter circuit 409 with the RF signal 827 that amplifies.Note, remove to use and have the LNA circuit of real-valued output (real output), also can use the have compound output LNA circuit and the multiphase filter circuit of (homophase and quadrature are exported).The combination of compound LNA circuit and multiphase filter circuit provides better pix carrier to suppress, though loss is high slightly.Therefore, select to use compound LNA circuit and multiphase filter circuit to depend on trading off between the loss that pix carrier suppresses and multiphase filter circuit is interior.
Down-converter circuit 409 is mixed the RF signal 827 that amplifies with the RF local oscillator signal 454 that receives from RF PLL circuit 840.Down-converter circuit 409 produces homophase analog down converter signal 412 and quadrature homophase analog down converter signal 415.Down-converter circuit 409 offers a pair of programmable gain amplifier (PGA) 833A and 833B with homophase analog down converter signal 412 and quadrature homophase analog down converter signal 415.
PGA 833A and PGA 833B partly allow to programme and receive the gain of path.PGA 833A and PGA 833B offer compound adc circuit 836 (that is, I and Q import both will influence I and Q exports both) with analog in-phase amplifying signal 841 and simulation quadrature amplifying signal 842.Adc circuit 836 converts analog in-phase amplifying signal 841 to an in-phase digital received signal 421.Similarly, adc circuit 836 will be simulated quadrature amplifier signal 842 and be converted an orthogonal digital received signal 424 to.
Note, preferably use the one-bit digital interface according to RF transceiver of the present invention and receiver.Yet, also can use various other interfaces as reading skilled person understands that of this specification of the present invention.For example, can use multidigit interface or parallel interface.In addition, as described below, the digital interface that receiver analog circuit 839 and digital receiver circuit are 851 can send various other signals, rather than following situation, or except that following situation, this situation is that a homophase and orthogonal digital received signal are offered digital receiver circuit 851.For instance, those signals can comprise reference signal (for example, clock signal), control signal, logical signal, handshake, data-signal, status signal, information signal, marking signal and/or configuration signal.In addition, as required, these signals can constitute single-ended or differential signal.Therefore, this interface provides between receiver analog circuit and digital receiver circuit communication mechanism flexibly.
Digital receiver circuit 851 is accepted an in-phase digital received signal 421 and an orthogonal digital received signal 424, and they are offered digital down converter circuit 427.Digital down converter circuit 427 becomes the conversion of signals that receives down-conversion in-phase signal 430 and down-conversion orthogonal signalling 433 and these signals is offered digital filter circuit 436.Digital filter circuit 436 preferably includes the IIR channel selection filter of carrying out filtering operation on its input signal.Yet, note, as required, can use the filter of other types, for example the FIR filter.
Note, mainly describe allomeric function and signal flow at the digital circuit block diagram shown in the digital receiver circuit 851.Actual digital circuit realizes can comprising or not comprising the independent discernible hardware that is used for each functional block.For example, as required, can reuse (in time, for example, multiplexed) identical digital circuit and realize digital PGA863A and digital PGA 863B by using.
Also note simultaneously, with RF transceiver-like among Fig. 4 seemingly, the RF transceiver among Fig. 8 is characterised in that digital IF architecture.Numeral IF architecture is convenient to realize the one-bit digital interface of 408 of digital receiver circuit 426 and receiver analog circuits.In addition, digital IF architecture allows numeral (rather than simulation) IF filtering, thereby all advantages of digital filtering are provided.
Transmitter circuitry 877 comprises base band up-converter circuits 466, sends VCO circuit 481, a pair of transmitter output buffer 892A and 892B, and compensation PLL circuit 897.Compensation PLL circuit 897 comprises skew mixer 891, phase detector circuit 882 and loop filter circuit 886.Base band up-converter circuits 466 accepts that analog in-phase sends input signal 460 and the simulation quadrature sends input signal 463, these signals is mixed with IF local oscillator signal 457, and will send IF signal 880 and offer compensation PLL circuit 897.Compensation PLL circuit 897 uses and sends IF signal 880 as reference signal.Send IF signal 880 and preferably include the single sideband IF signal of modulation, but as skilled in the art will appreciate, as required, can use the signal and the modulation of other types.
Skew mixer 891 in compensation PLL circuit 897 will send VCO input signal 478 to be mixed with RF local oscillator signal 454, and mixed signal 890 is offered phase detector circuit 882.Phase detector circuit 882 compares mixed signal 890 and transmission IF signal 880 and compensation PLL error signal 884 is offered loop filter circuit 886.Loop filter circuit 886 offers transmission VCO circuit 481 with the compensation PLL signal 888 of filtering successively.Therefore, compensation PLL circuit 897 and transmission VCO circuit 481 are operated in feedback control loop.Best, the output frequency of transmission VCO circuit 481 occupy the center between DCS and the PCS frequency band, and it is exported divided by 2 for use in the GSM frequency band.
Transmitter output buffer 892A and 892B receive the transmission signal 894 and 895 that sends VCO output signal 478 and will cushion and offer a pair of power amplifier 896A and 896B.Power amplifier 896A and 896B provide the RF signal 899 and 898 of amplification respectively, are used for sending by antenna interface circuit 202 and antenna 130.Power amplifier 896A is provided for the RF signal 899 of GSM frequency band, and power amplifier 896B is provided for the RF signal 898 of DCS and PCS frequency band.Yet, it should be appreciated by those skilled in the art that other configurations that can use power amplifier and frequency band.In addition, as required, the RF filter circuit can be used in the output channel of transmitter circuitry 877.
Embodiment 800 comprises three circuit parts (or circuit block).First circuit part 801 comprises receiver analog circuit 839 and transmitter circuitry 877.Second circuit part 854 comprises digital receiver circuit 851 and standard signal generator circuit 218.At last, tertiary circuit partly comprises local oscillator circuit 222.Make first circuit part 801, second circuit part 854 and tertiary circuit part separated from one another to be convenient to reduce the disturbing effect in each circuit part.Because in above-mentioned analysis in conjunction with the disturbing effect that Fig. 3 provided, this kind configuration is easy to reduce the disturbing effect in each circuit part.Best, each in first, second and the tertiary circuit part is present in the integrated circuit (IC) apparatus.For further reducing the disturbing effect in each circuit part, the embodiment 800 of Fig. 8 uses differential signal in the case of any possible.Among Fig. 8, use differential lines to propagate by the signal of note with holding wire or reference numerals adjacent symbol " (diff.) " expression.
Note, with as shown in Figure 4 RF transceiver-like seemingly, as mentioned above, embodiment 800 shown in Figure 8 is used in analog to digital-analog signal channel in its receiver section.Owing to combine the described similar reason of transceiver shown in Figure 4, embodiment 800 uses this special signal path.
Identical with the transceiver among Fig. 4, if digital receiver circuit 851 does not need the general-purpose simulation interface compatibility with baseband processor, then can remove DAC circuit 875A and 875B, and as required, use digital interface with baseband processor circuit.In fact, with the RF transceiver-like shown in Fig. 2 D seemingly, can use the functions that realize digital receiver circuit 851 in the baseband processor circuit 120 that are combined in of hardware, software or hardware and software.Under this kind situation, the RF transceiver will comprise two circuit parts (or circuit block).First circuit part 801 will comprise receiver analog circuit 839 and transmitter circuitry 877.The second circuit part will comprise local oscillator circuit 222.Also it should be noted that simultaneously with the RF transceiver-like shown in Fig. 2 C seemingly, in embodiment 800, as required, the function of standard signal generator circuit 218 can be included in the baseband processor circuit 120.
Another aspect of the present invention comprises the configurable interface between digital receiver circuit and receiver analog circuit.Usually, the numeral of attempting to minimize in the receiver analog circuit exchanges activity.Numeral exchange activity in the receiver analog circuit may be disturbed sensitive analog RF circuit, for example, and LNA or frequency mixer.As mentioned above, the receiver analog circuit comprises modulus circuit (ADC), and it preferably includes sigma-delta type ADC.Sigma-delta type ADC uses clock signal in their output stage usually, and its output stage has impulse waveform usually, and therefore comprises high frequency Fourier progression harmonic wave.In addition, adc circuit itself produces the numeral output that the digital receiver circuit uses.The numeral exchange that occurs in the output of adc circuit is also with the sensitive analog circuit in the interference receiver analog circuit.
The invention is intended to provide according to RF device of the present invention, for example, receiver and transceiver, it comprises interface circuit so that minimize or reduce disturbing effect from the digital circuit in the RF device.Fig. 9 A represents the embodiment 900A of the interface of 910 of digital receiver circuit 905 and receiver analog circuits.This interface comprises configurable interface holding wire 945.Baseband processor circuit 120 in the transceiver of Fig. 9 A sends to digital receiver circuit 905 and receiver analog circuit 910 with configuration, state and signalization.In the preferred embodiment of RF transceiver according to the present invention, by configuration data being sent to the read-write register that is included in digital receiver circuit 905 and the receiver analog circuit 910, baseband processor circuit 120 can be communicated by letter with receiver analog circuit 910 with digital receiver circuit 905.
In lowering power consumption or serial interface mode (that is, and control signal 915 (for example, PDNB) being in logic low state), interface signal line 950 provides serial clock (SCLK) and interface signal line 955 that serial line interface enable signal (SENB) is provided.In addition.Interface signal line 960 provides input serial data signal (SDI), and interface signal line 965 provides serial data output (SDO) signal.In the operating period of this pattern, as required, but transceiver also executive circuit calibration and adjustment process.For example, the value of different transceiver component can change in time or by the different transceivers of producing in batches.Transceiver can change and adjust its circuit so that consider this variation and more high-performance is provided.
In the normal receiving mode (that is, control signal, PDNB is in logic high state) of operation, interface signal line 950 provides negative clock signal (CKN) and interface signal line 955 that positive clock signal (CKP) is provided.In addition, interface signal line 960 provides negative data signal (ION), and interface signal line 965 provides positive data signal (IOP).
In a preferred embodiment of the invention, CKN and CKP signal form the differential clock signal that is offered receiver analog circuit 910 by digital receiver circuit 905 together.Receiver analog circuit 910 can offer this clock signal transmitter circuitry in the RF transceiver so that the calibration of circuit and adjustment, as mentioned above.During receiving mode, receiver analog circuit 910 offers digital receiver circuit 905 with ION and IOP signal.ION and IOP signal are preferably formed as differential data signals.As above mentioned, during the receiving mode of operation, transceiver disable transmitter circuit.
In a preferred embodiment according to the present invention, when transmitter circuitry sends signal, cut off clock signal C KN and CKP.During sending mode, interface signal line 960 and 965 preferably will offer receiver analog circuit 910 from two logical signals of digital receiver circuit 905.As required, holding wire can provide input/output signal so that send data, state, information, mark and configuration signal at digital receiver circuit 905 and 910 of receiver analog circuits.Best, logical signal control sends the output buffer of VCO circuit.Note, except that interface signal line 960 and 965 is configured to the logical signal line, as required, and can be otherwise, for example, analog signal line, difference analogue or digital signal line or the like dispose them.In addition, as required, interface signal line 960 and 965 can offer the signal from digital receiver circuit 905 receiver analog circuit 910, or vice versa.
Except that using differential signal, RF transceiver according to the present invention preferably adopts other measures to reduce disturbing effect in each transceiver circuit.As required, signal CKN, CKP, ION and IOP can constitute voltage signal.According to application, signal CKN, CKP, ION and IOP (or the logical signal in the sending mode) can have low voltage swing (for example, voltage swing is less than supply power voltage) so that reduce because the size and the effect of the interference that the voltage exchange on these signals causes.
In a preferred embodiment according to the present invention, signal CKN, CKP, ION and IOP constitute electric current, rather than voltage signal.In addition, reduce disturbing effect for further helping, RF transceiver according to the present invention preferably uses band-limited signal.RF transceiver according to the present invention preferably uses filtering to remove some higher frequency harmonics so that produce the finite bandwidth current signal from those signals.
Below table 3 with the preferred function of configurable interface holding wire 950,955,960 and 965 reduce control signal 915 (for example, the function of state PDNB):
Table 3
| Holding wire | Control=0 | Control=1 (reception period) | Control=1 (during the transmission) |
| ????950 | ????SCLK | ??CKN | (CKN disconnection) |
| ????955 | ????SENB | ??CKP | CKP disconnects |
| ????960 | ????SDI | ??ION | Logical signal |
| ????965 | ????SDO | ??IOP | Logical signal |
In the interface of 910 of digital receiver circuit 905 and receiver analog circuits, use configurable interface holding wire 945 to allow to use identical physical connection (for example, pin on the integrated circuit (IC) apparatus or the electric power connector on the module) to realize difference in functionality.Therefore, the configurable interface of digital receiver circuit 905 and 910 of receiver analog circuits makes physical electronic be connected to can be used for other uses, for example, near the analog signal pin of sensitivity or connector, provide ground pin or connector so that help to shield those signals that disturb from RF.In addition, the configurable interface of 910 of digital receiver circuit 905 and receiver analog circuits has reduced size, cost and the complexity of encapsulation.
Fig. 9 B represents to comprise the embodiment 900B according to configurable interface of the present invention.Here, baseband processor circuit 120 comprises the functional of digital receiver circuit 905.As required, baseband processor circuit 120 uses hardware, software or the two to realize the functional of digital receiver circuit 905.Because baseband processor circuit 120 has comprised digital receiver circuit 905, so baseband processor circuit 120 can be used configurable interface holding wire 945, (for example, the PDNB signal) state is communicated by letter with receiver analog circuit 910 according to control signal 915.According to the state of control signal 915, configurable interface holding wire 945 is carried out as above in conjunction with the described identical function of Fig. 9 A.As mentioned above, during sending mode, reconfigurable interface signal line 960 and 965 is so that realize required function, for example, and logical signal.
Figure 10 is illustrated in the interior The general frame according to the embodiment 1000 of configurable interface of the present invention of the RF transceiver that lowers in power consumption or the serial interface mode (that is, logical signal 915 be a logic low state).Logic low state enable driver circuit 1012A, 1012B and 1012C on the control signal 915, thus configurable serial interface holding wire 950,955 and 960 is offered receiver analog circuit 910.Similarly, the logic low state on the control signal 915 makes AND door 1030A, 1030B and 1030C that configurable interface holding wire 950,955 and 960 is offered other circuit in the receiver analog circuit 910.The output of AND door 1030A, 1030B and 1030C comprises the SCLK signal 1032 of gating, the SENB signal 1034 of gating and the sdi signal 1036 of gating respectively.
Three-state driver circuit 1012A, 1012B and 1012C are with the enable signal of anti-phase control signal 915 as them.Therefore, the logic-high value of control signal 915 forbidding drive circuit 1012A, 1012B and 1012C, thereby the serial line interface of 910 of forbidding digital receiver circuit 905 and receiver analog circuits.Similarly, AND door 1030A, 1030B and 1030C use anti-phase control signal 915 to come gating interface signal line 950,955 and 960.In other words, the logic-high value of control signal 915 logic of forbidding manufacture in the output of AND door 1030A, 1030B on receiver analog circuit 910 and 1030C is switched.
Figure 11 A is illustrated in the RF transceiver by conventional receiving mode (that is, control signal 915 the is in logic high state) work of operation, according to the The general frame of the embodiment 1100A of configurable interface of the present invention.As mentioned above, in this pattern, digital receiver circuit 905 offers receiver analog circuit 910 by configurable interface holding wire 950 and 955 with clock signal.Configurable interface holding wire 950 provides CKN signal, and configurable interface holding wire 955 provides CKP signal.Equally, in this pattern, receiver analog circuit 910 offers digital receiver circuit 905 by configurable interface holding wire 960 and 965 with data-signal.
As required, clock signal 1132A is an adc circuit 1144, or other circuit (for example, calibration circuit) or the two timing.Note, except that using clock signal 1132, can use complementary clock signal 1132B by as the technical staff will understand, circuit being improved.Adc circuit 1144 divides quadrature digital signal 1146B to offer multiplexer circuit 1150 a potential difference branch in-phase digital signal 1146A and a potential difference.Multiplexer circuit 1150 divides digital output signal 1152 to offer digit driver circuit 1154 potential difference.Therefore, output signal 1152 forms multiplexed I channel data and Q channel data.Use configurable interface holding wire 960 and 965 respectively, data driving circuit 1154 will comprise that the differential data signals of ION and IOP offers digital receiver circuit 905.
Clock signal 1132A also serves as the selection signal of multiplexer circuit 1150.On the alternation edge of clock signal 1132A, multiplexer circuit 1150 selects a potential difference branch in-phase digital signal 1146A (being the I channel data) and a potential difference to divide quadrature digital signal 1146B (that is Q channel data) and provide it to data driving circuit 1154.Interface controller circuit 1140 offers data driving circuit 1154 with enable signal 1156, and this data driving circuit 1154 offers digital receiver circuit 905 through configurable interface holding wire 960 and 965 controls with configurable interface signal 960 and configurable interface signal 965.
The output signal of delay unit circuit 1119 helps its I channel data and Q channel data that receives from receiver analog circuit 910 of digital receiver circuit 905 samplings.Digital receiver circuit 905 receives multiplexed I channel data and Q channel data by ION signal 960 and IOP signal 965.Therefore, d type flip flop circuit 1123A and 1123B carry out the multichannel decomposition function on multiplexed I channel data and Q channel data.
In the reception or sending mode of routine, (that is, control signal 915 is in logic high state), interface signal line 950 provides negative clock signal (CKN), and interface signal line 955 provides positive clock signal (CKP).In a preferred embodiment of the invention, CKN and CKP signal form the differential clock signal that digital receiver circuit 905 offers receiver analog circuit 910 together.
During receiving mode, interface signal line 960 provides negative data signal (ION), and interface signal line 965 provides positive data signal (IOP).ION and IOP signal are preferably formed as differential data signals.
In sending mode, data-signal can serve as input/output signal so that send data, state, information, mark and/or configuration signal at digital receiver circuit 905 and 910 of receiver analog circuits.Best, interface signal line 960 and 965 is served as two logical signal lines in the sending mode.As mentioned above, during the sending mode of operation, transceiver forbidding receiver circuit.In the RF transceiver of separating according to the present invention (referring to for example, Fig. 2 A-2D, 4 and 8), as mentioned above, clock receiver circuit 1130 can be with clock signal 1132A, complementary clock signal 1132B, or the two offers transmitter circuitry (being separated in conjunction with receiver analog circuit 910), is used for the circuit calibration, circuit is adjusted or the like.
Yet in sending mode, as long as finish circuit calibration and adjustment, clock driver circuit 1114 uses enable signals 1118 to forbid CKN and CKP clock signal are propagated into receiver analog circuit 910.In this way, clock driver circuit 1114 is carried out the function of switch 492 in Fig. 4 and 8.Notice that during the conventional sending mode of operation, adc circuit 1144 provides any data without ION and IOP signal to digital receiver circuit 905, because according to the TDD agreement, during the conventional sending mode of operation, the receiver path circuitry is invalid.Yet digital receiver circuit 905 offers receiver analog circuit 910 with control signal through interface signal line 960 and 965.
During sending mode, interface controller circuit 1116 offers interface signal line 960 and 965 through holding wire 1160 with control signal.Interface controller circuit 1140 receives control signals and as required through holding wire 1165, and they are offered each piece in the receiver analog circuit.During receiving mode, interface controller circuit 1116 is forbidden (for example, high-impedance state) holding wire 1160.Similarly, interface controller circuit 1140 inhibit signal line 1165 during receiving mode.
Be overall example purpose, Figure 11 A represents that as the interface controller circuit 1116 of two circuit blocks and interface controller circuit 1140 these two circuit blocks are distinguished mutually with interface controller circuit 1010 and the interface controller circuit 1040 of Figure 10 respectively.As required, the function of interface controller circuit 1116 can be combined with the function of interface controller circuit 1010.Equally, as required, the function of interface controller circuit 1140 can be combined with the function of interface controller circuit 1040.In addition, the function of signal processing circuit 1110 can be combined with the function of interface controller circuit 1116 and interface controller circuit 1140 respectively.As skilled in the art will appreciate, depend on the selection of various designs and realization in conjunction with the function of these circuit.
The explanation of Figure 11 B example is according to the block diagram of the preferred embodiment 1100B of delay unit circuit 1119 of the present invention.Delay unit circuit 1119 comprises the duplicate of the duplicate series connection clock driver circuit 1114A of Data Receiving machine circuit 1120A.(notice that delay unit circuit 1119 alternately comprises the duplicate of the duplicate tandem data drive circuit 1154 of clock receiver circuit 1130.) duplicate of clock driver circuit 1114A accepts clock signal 1112A and complementary clock signal 1112B.The duplicate of clock driver circuit 1114A offers its output the duplicate of Data Receiving machine circuit 1120A.The duplicate of Data Receiving machine circuit 1120A provides clock signal 1121A and complementary clock signal 1121B.Clock signal 1121A and complementary clock signal 1121B constitute the output signal of delay unit circuit 1119.Delay unit circuit 1119 also is received as enable signal 1118 and 1124 input (note, for clarity sake, not shown those input signals of Figure 11 A).Enable signal 1118 is coupled to the duplicate of clock driver circuit 1114A, and enable signal 1124 is coupled to the duplicate of Data Receiving machine circuit 1120A.
Notice that Figure 11 B constitutes the The general frame of delay unit circuit 1119.Except that using different masses 1114A and 1120A, as required, alternately use single in conjunction with the function of these two pieces.In addition, as required, can use provides adjustable, rather than the circuit of fixed delay.Note the delay in the clock driver circuit 1114 among the best compensation image 11A of the embodiment 1100B of delay unit circuit 1119 simultaneously.In other words, delay unit circuit 1119 preferably is enough to compensate from digital receiver circuit 905 and sends to receiver analog circuit 910 and the round trip that turns back in the signal of digital receiver circuit 905 postpones, so that allow in the digital receiver circuit accurately sampled I channel data and Q channel data.
Yet, if necessary, but the also signal delay of compensating clock receiver circuit 1130, data driving circuit 1154 and Data Receiving machine circuit 1120 of delay unit circuit 1119.Therefore, under the situation of the technological parameter that closely mates digital receiver circuit 905 and receiver analog circuit 910 relatively (for example, by using film assembly, silicon-on-insulator or the like), delay unit circuit 1119 also can compensate the delay of other circuit blocks.As another replacement scheme, as skilled in the art will appreciate, can use provides scalable to postpone, postpone (the digital receiver circuit 905 and the receiver analog circuit 910 of one group of coupling for example, is provided) based on this scalable of late programming in digital receiver circuit 905 and the receiver analog circuit 910 then.In addition, outside loop device, as required, can use the closed loop feedback circuit to realize that (for example, by using phase-locked loop circuit) control and the delay of 905 in compensated receiver analog circuit 910 and digital receiver circuit.
Notice that the digital circuit block shown in Figure 11 A and 11B are interior is mainly described general function and signal flow.Side circuit realizes can comprising or not comprising the independent hardware discerned that is used for each functional block.For example, as required, the function of each circuit block can be attached in the circuit block.
Figure 12 represents the schematic diagram according to the preferred embodiment 1200 of signal drive circuit of the present invention.Can be with signal drive circuit as clock driver circuit 1114 and data driving circuit 1154.Under one situation of back, in Figure 11 A, the input signal of signal drive circuit constitutes output signal 1152 and enable signal 1156, and the output signal of signal receiver circuit constitutes ION signal 960 and IOP signal 965 respectively
Signal drive circuit among Figure 12 comprises two circuit branch.Circuit branch comprises MOSFET device 1218 and 1227 and resistor 1230.Second branch road comprises MOSFET device 1242 and 1248 and resistor 1251.Input clock signal control MOSFET device 1218 and 1242.Current source 1206, MOSFET device 1209 and 1215 and resistor 1212 be provided for the biasing of two circuit branch.
MOSFET device 1227 and 1248 drives CKN and CKP output by resistor 1230 and 1251 respectively.According to the state of clock signal, a branch road of signal drive circuit conducts more electric current than another branch road.By another kind of method, response clock signal, signal drive circuit is introduced other branch roads with electric current from a branch road.Therefore, signal drive circuit provides the differential clock signal that comprises current signal CKN and CKP.
If enable signal is high, therefore MOSFET device 1203 does not influence the operation of remaining circuit for disconnecting.In this case, electric current I
0Flow through current source 1206 and the MOSFET device 1209 that connects into diode.The grid formation voltage that is flowing in MOSFET device 1209 of electric current.MOSFET device 1227 and 1248 is shared identical grid with MOSFET device 1209 and is connected.Therefore, when the MOSFET device that is fit to was in conducting state, MOSFET device 1227 and 1248 had the gate source voltage V identical with MOSFET device 1209
Gs
MOSFET device 1218 and 1242 causes the electric current of guiding between first and second circuit branch.During circuit operation, only there is a MOSFET device 1218 and 1242 to be in conducting state.Which MOSFET device to be in conducting state according to, image current (mirroring current) I
0Flow through the current branch that comprises the device that is in conducting state.
Resistor 1221 and 1239 offers the circuit branch that comprises the MOSFET device (that is, MOSFET device 1218 or MOSFET device 1242) that is in off state with little trickle electric current (strickle current).This little trickle electric current prevents that the MOSFET device (seeing Figure 13) that connects into diode in the signal receiver circuit from disconnecting fully.Transition in the response input clock signal, this trickle electric current help to reduce the delay that changes in the current status.This trickle electric current also helps to help to reduce the transient signal of CKP and CKN end, thereby reduces disturbing effect.
When capacitor 1224 and 1245 provided filtering with convenient MOSFET device 1218 and MOSFET device 1242 switching states, the electric current that flows through first and second circuit branch (CKN and CKP circuit branch) can not change fast.Therefore, capacitor 1224 and 1245 reduces the high frequency content from the electric current of each circuit branch inflow CKN and CKP end.As mentioned above, high frequency (that is, the limited frequency band) content of reduction that flows through the electric current of CKN and CKP end helps to reduce to other circuit parts, for example, and the disturbing effect of LNA circuit.Capacitor 1233 and 1236 and resistor 1230 and 1251 help further to reduce the high frequency content of the electric current that flows through CKN and CKP end.Therefore, the circuit among Figure 12 is provided between two circuit branch and guides electric current smoothly, thus the disturbing effect of reduction and other circuit.
When enable signal entered low level state, 1203 conductings of MOSFET device also disconnected MOSFET device 1209.MOSFET device 1227 and 1248 also disconnects, and this circuit becomes and forbids.Note, can derive enable signal from lowering power consumption PDNB signal.
Figure 13 represents the schematic diagram according to the preferred embodiment 1300 of signal receiver circuit of the present invention.Can be with the signal receiver circuit as clock receiver circuit 1130 and Data Receiving machine circuit 1120 among Figure 11 A.Under latter event, in Figure 11 A, the input signal of signal receiver circuit constitutes ION signal 960 and IOP signal 965 and enable signal 1124, and output signal constitutes the signal at output 1122A and 1122B place respectively.
Signal receiver circuit among Figure 13 helps to convert the difference input current to the CMOS logical signal.Signal receiver circuit among Figure 13 is by comprising two circuit branch.First circuit branch comprises MOSFET device 1303,1342 and 1345.Second branch road comprises MOSFET device 1309,1324 and 1327.Note, best, MOSFET device 1303 and 1309 be targeted at 1: 2 current gain be provided between them.Similarly, MOSFET device 1330 and 1327 be targeted at 1: 2 current gain be provided between them.Current gain helps to reduce the phase noise in the signal receiver circuit.
The current reflection of flowing through CKN and CKP end is to MOSFET device 1327 and 1309.The electric current that actual flow is crossed the second circuit branch road depends on the electric current of being attempted to conduct by MOSFET device 1327 and MOSFET device 1309.The actual current of second circuit branch road is flow through in junior's decision in two electric currents.
Difference between the electric current that MOSFET device 1327 and MOSFET device 1309 are attempted to conduct flows through the parasitic capacitance at node 1360 places.At node 1360, the current charges or this electric capacity that discharges, thus make any one drain source voltage (V in the MOSFET equipment 1327 and 1309 of attempting to transport higher electric current
Ds) less.Finally, the decision of the reduced-current of MOSFET device 1327 and 1309 electric current attempting to conduct is by the electric current of second branch road of circuit.
Pair of phase inverters 1312 and 1315 provides actual and complementary output signal 1351 and 1348 respectively.Therefore, the signal receiver circuit converts the difference input current to the CMOS logic output signal.
Figure 14 represents the embodiment 1400 according to alternative signal drive circuit of the present invention.Signal drive circuit among Figure 14 comprises two circuit branch.First circuit branch comprises MOSFET device 1406 and resistor 1415A.The second circuit branch road comprises MOSFET device 1409 and resistor 1415B.Current source 1403 offers two circuit branch with electric current.
Input clock signal control MOSFET device 1406 and 1409. MOSFET device 1406 and 1409 drives CKP and CKN output respectively.According to the state of clock signal, a branch road conduction current of signal drive circuit.In other words, response clock signal, signal drive circuit is guided into another branch road with electric current from a branch road.Therefore, signal drive circuit provides the differential clock signal that comprises signal CKN and CKP.Capacitor 1412 filters output signal CKN and CKP.In other words, capacitor 1412 provides the frequency band limits of output signal CKN and CKP.Notice that current source 1403 provides electric current that limitation signal is provided by capacitor 1415A and 1415B.
Note, preferably provide current signal CKN and CKP according to signal drive circuit of the present invention (clock driver and data driving circuit).Similarly, according to the best received current signal of signal receiver circuit of the present invention (clock receiver and Data Receiving machine circuit).As a kind of replacement scheme, as required, can use provides signal drive circuit as their output with voltage signal.Also can realize receiving the signal receiver circuit of voltage signal rather than current signal.As mentioned above, according to application, as required, for example, can limit the frequency of those voltage signals by filtering and form.
Usually, exist and be used for limit noise, for example, several technology of the numeral exchange noise in the interface between receiver analog circuit according to the present invention and digital receiver circuit.These technology comprise to be used differential signal, use band-limited signal and uses limitation signal.As required, RF device according to the present invention can use any or whole of these technology.In addition, will understand, can or all be applied in the interface circuit that adopts voltage or current signal any one of those technology as those of ordinary skill in the art of reading specification of the present invention.
Note, as skilled in the art will appreciate, support the various selections of circuit realization according to each embodiment of RF transceiver of the present invention.For example, as above mentioned, preferably be present in the integrated circuit (IC) apparatus according to each circuit part (or circuit block) of RF transceiver of the present invention.Yet, those skilled in the art will recognize, circuit part (or circuit block) alternately is present in other substrates, carrier or the packaging system.By example, as required, other separating devices can use insulated part on assembly, film assembly, thick film assembly, the single substrate, circuit board section or the like, and are consistent with embodiments of the invention described here.
One aspect of the present invention attempts to separate the RF transceiver that is designed to operation in several communication channels (for example, GSM, PCS and DCS).Yet, those skilled in the art will recognize, as required, can separate according to the present invention and be designed to the RF transceiver in one or more other channels, frequency or frequency band, operated.
In addition, the separation according to RF transceiver of the present invention preferably be applied to have low IF, the RF device of digital IF architecture (for example, receiver or transceiver).Yet, note, will appreciate that as those of ordinary skill in the art, separation according to the present invention and interface principle can be applied to other RF receivers or transceiver architectures and configuration.By example, separation according to the present invention and interface principle can be used in the RF device, this RF device comprises:
● low IF receiver circuit;
● low IF receiver circuit and compensation PLL transmitter circuitry;
● low IF receiver circuit and direct upconversion transmitter circuit;
● directly change receiver circuit;
● directly change receiver circuit and compensation PLL transmitter circuitry; Or
● directly change receiver circuit and direct upconversion transmitter circuit
An example as the flexibility of separation principle according to the present invention is described, can comprise the LO circuit in a part, comprises the digital receiver circuit in second portion, and comprise receiver up-converter circuit and receiver analog circuit in third part.Described as another exemplary alternative according to noise and interference characteristic and the specification that is used for specific implementation, LO circuit and transmitter up-converter circuit can be included in the circuit part.
Notice that in typical Direct Conversion RF receiver or transmitter realization, the digital receiver circuit will not comprise Digital Down Convert circuit (yet the receiver analog circuit will be similar with the above embodiments).In addition, in typical directly upconversion transmitter circuit, can from transmitter circuitry, remove compensation PLL circuit and send the VCO circuit.The LO circuit offers the up-converter circuit of transmitter circuitry rather than compensation PLL circuit with RF LO signal.Equally, in directly up-conversion realized, the LO circuit did not provide IF LO signal usually.
In addition, as above mentioned, separation according to the present invention and interface principle not only can be used in the RF transceiver, and be used in the RF receiver that is used for performance application.In this RF receiver, can be shown in Fig. 2 A-2D and 4-8 spaced receiver (as mentioned above).In other words, the RF receiver can have first circuit part that comprises the receiver analog circuit, and the second circuit part that comprises the digital receiver circuit.
As required, the RF receiver also can use digital interface between receiver analog circuit and digital receiver circuit.Because use aforesaid receiver analog circuit and digital receiver circuit, the RF receiver has the feature of low IF, digital IF architecture.In addition, as mentioning,, as required, can all or a part of local oscillator circuit will be comprised in the circuit part that comprises the receiver analog circuit according to specification and design object with respect to RF transceiver according to the present invention.Separate the RF receiver according to the present invention and be easy to reduce disturbing effect between each circuit part.
As mentioned above, although RF device according to the present invention uses serial line interface between receiver analog circuit and digital receiver circuit, but as required, for example also can use the holding wire that comprises varying number, dissimilar and big or small signal, or the interface of the other types such as parallel interface of the two.In addition, according to the present invention, clock driver circuit and data driving circuit constitute signal drive circuit usually, this signal drive circuit can be used in the various digital interfaces between receiver analog circuit and digital receiver circuit.
Equally, according to the present invention, clock receiver circuit and Data Receiving machine circuit constitute the signal receiver circuit usually, this signal receiver circuit can be used in the various digital interfaces between receiver analog circuit and digital receiver circuit.In other words, will understand, and can use signal drive circuit and the signal receiver circuit to realize more kinds of digital interfaces as the those of ordinary skill of reading specification of the present invention.
Other further improvement and additional embodiments of the present invention are conspicuous to the those skilled in the art who considers specification of the present invention.Therefore, this specification instruction those skilled in the art realizes method of the present invention and only is interpreted as being the example purpose.
Shown in and the form of the invention described should be understood to current preferred embodiment.Those skilled in the art will make various changes aspect shape, size and the configuration of each parts, and not break away from the scope of the present invention described in this document.For example, the element of those skilled in the art's available equivalents replaces the element in this example and description.In addition, the those skilled in the art who is benefited from this specification of the present invention can irrespectively use some feature of the present invention with other features, and does not depart from the scope of the present invention.
Claims (54)
1, a kind of radio frequency (RF) device comprises:
First circuit part, it comprises and is configured to be used for produce from analog radio-frequency signal the receiver analog circuit of digital received signal; And
The second circuit part, it comprises the digital receiver circuit that is configured to be used for accepting described digital received signal, wherein separates described first and second circuit parts to be convenient to reduce the disturbing effect between described first circuit part and described second circuit part.
2, RF device as claimed in claim 1, wherein said first circuit part comprise that being configured to be used for receiving at least one sends input signal and the transmitter circuitry that sends the RF signal is provided.
3, RF device as claimed in claim 2, wherein said transmitter circuitry comprise transmission voltage controlled oscillator (VCO) circuit.
4, RF device as claimed in claim 3, wherein said first circuit part is arranged in first integrated circuit (IC) apparatus, and described second circuit partly is arranged in second integrated circuit (IC) apparatus.
5, RF device as claimed in claim 3, comprise the tertiary circuit part, described tertiary circuit partly comprises and is configured to be used for provide to described receiver analog circuit and described transmitter circuitry the local oscillator circuit of radio frequency (RF) signal, described local oscillator circuit further is configured to be used for intermediate frequency (IF) signal is offered described transmitter circuitry, wherein separates described first, second and tertiary circuit part to be convenient to reduce the disturbing effect in described first, second and the tertiary circuit part.
6, RF device as claimed in claim 5, wherein said first circuit part is arranged in first integrated circuit (IC) apparatus, and described second circuit partly is arranged in second integrated circuit (IC) apparatus, and described tertiary circuit partly is arranged in the 3rd integrated circuit (IC) apparatus.
7, RF device as claimed in claim 5, wherein said digital receiver circuit comprise digital to analog converter (DAC) circuit that is configured to be used for producing analog receiving signal.
8, RF device as claimed in claim 7, wherein said first circuit part is arranged in first integrated circuit (IC) apparatus, and described second circuit partly is arranged in second integrated circuit (IC) apparatus, and described tertiary circuit partly is arranged in the 3rd integrated circuit (IC) apparatus.
9, a kind of radio frequency (RF) transceiver comprises:
First circuit part, it comprises:
The receiver analog circuit, it is configured to be used for to accept the RF signal that received
And provide at least one digital output signal; And
Transmitter circuitry, it is configured to be used for receiving at least one and sends input signal
And provide transmission RF signal;
The second circuit part, it comprises the local oscillator circuit that is configured to be used for accepting reference signal, described local oscillator circuit further is configured to be used for radio frequency (RF) signal is offered receiver analog circuit and transmitter circuitry, wherein separates described first circuit part and described second circuit part to be convenient to reduce the disturbing effect between described first circuit part and described second circuit part.
10, transceiver as claimed in claim 9, wherein the described transmitter circuitry in described first circuit part comprises transmission voltage controlled oscillator (VCO) circuit.
11, transceiver as claimed in claim 10, wherein said receiver analog circuit offers described at least one digital output signal in described first and second circuit parts baseband processor circuit in addition.
12, transceiver as claimed in claim 11, wherein said receiver analog circuit comprises:
The analog down converter circuit, it is configured to be used for to accept the RF signal that received, and described down-converter circuit further is configured to be used to provide the analog down signal; And
Analog to digital converter (ADC) circuit, it is configured to be coupled to described baseband processor circuit, described analog-digital converter circuit is configured to be used for receiving the analog down signal, and described modulus circuit further is configured to be used to provide at least one digital output signal of described receiver analog circuit.
13, transceiver as claimed in claim 12, wherein said transmitter circuitry comprises the base band up-converter circuits, this up-converter circuits is configured to be used for accepting described at least one transmission input signal, and described base band up-converter circuits further is configured to be used for intermediate frequency (IF) signal is offered compensation phase-locked loop (PLL) circuit that is coupled to the transmission voltage-controlled oscillator circuit.
14, transceiver as claimed in claim 13 is included in the standard signal generator circuit outside described first and second circuit parts, and this standard signal generator circuit is configured to be used for described reference signal is offered described second circuit part.
15, transceiver as claimed in claim 14, wherein said standard signal generator circuit is positioned at described baseband processor circuit.
16, transceiver as claimed in claim 14, wherein said base band generator circuit receives at least one digital output signal of described receiver analog circuit, and wherein said base band generator circuit offers described base band up-converter circuits with described at least one transmission input signal.
17, transceiver as claimed in claim 16, wherein said first circuit part is arranged in first integrated circuit (IC) apparatus, and described second circuit partly is arranged in second integrated circuit (IC) apparatus.
18, transceiver as claimed in claim 10, comprise the tertiary circuit part, described tertiary circuit partly comprises the digital receiver circuit, this circuit is configured to be used for receiving at least one digital output signal of described receiver analog circuit, wherein separates described first, second and tertiary circuit part to be convenient to reduce the disturbing effect in described first, second and the tertiary circuit part.
19, transceiver as claimed in claim 18, wherein said receiver analog circuit comprises:
The analog down converter circuit, it is configured to be used for to accept the RF signal that received, and described down-converter circuit further is configured to be used to provide the analog down signal; And
Analog to digital converter (ADC) circuit, it is configured to be used for receiving described analog down signal, and described analog-digital converter circuit further is configured to be used to provide at least one digital output signal of described receiver analog circuit.
20, transceiver as claimed in claim 19, wherein said digital receiver circuit comprises:
The digital down converter circuit, it is configured to be used for accepting at least one digital output signal of described receiver analog circuit, and described digital down converter circuit further is configured to be used to provide at least one Digital Down Convert signal; And
Digital filter circuit, it is configured to be used for receiving described at least one Digital Down Convert digital signal, and described digital filter further is configured to be used to provide at least one digital filtered signal.
21, transceiver as claimed in claim 20, wherein said transmitter circuitry comprises the base band up-converter circuits, it is configured to be used for accepting described at least one transmission input signal, and described base band up-converter circuits further is configured to be used for intermediate frequency (IF) signal is offered compensation phase-locked loop (PLL) circuit that is coupled to the transmission voltage-controlled oscillator circuit.
22, transceiver as claimed in claim 21, be included in the standard signal generator circuit outside described first, second and the tertiary circuit part, described standard signal generator circuit is configured to be used for described reference signal is offered described second and the tertiary circuit part.
23, transceiver as claimed in claim 22, wherein outside baseband processor circuit receives at least one filtered digital signal of described digital filter circuit, and wherein said baseband processor circuit offers described base band up-converter circuits with described at least one transmission input signal.
24, transceiver as claimed in claim 23, wherein said standard signal generator circuit is positioned at described baseband processor circuit.
25, transceiver as claimed in claim 24, wherein said first circuit part is arranged in first integrated circuit (IC) apparatus, and described second circuit partly is arranged in second integrated circuit (IC) apparatus, and described tertiary circuit partly is arranged in the 3rd integrated circuit (IC) apparatus.
26, transceiver as claimed in claim 22, wherein said digital receiver circuit comprises digital to analog converter (DAC) circuit, it is configured to be used for accept at least one filtered digital signal from described digital filter circuit, and described d convertor circuit is configured to be used to provide at least one analog receiving signal.
27, transceiver as claimed in claim 26, wherein said first circuit part is arranged in first integrated circuit (IC) apparatus, and described second circuit partly is arranged in second integrated circuit (IC) apparatus, and described tertiary circuit partly is arranged in the 3rd integrated circuit (IC) apparatus.
28, a kind of method that is used to separate radio frequency (RF) device comprises:
First circuit part that comprises the receiver analog circuit is provided;
Utilize described receiver analog circuit to come to produce the digital received signal from analog radio-frequency signal;
The second circuit that comprises digital receiver circuit part is provided;
Utilize described digital receiver circuit to accept described digital received signal; And
Separate described first and second circuit parts to be convenient to reduce the disturbing effect between described first circuit part and described second circuit part.
29, method as claimed in claim 28 further comprises:
In described first circuit part, provide transmitter circuitry; And
Utilizing described transmitter circuitry to receive at least one sends input signal and transmission RF is provided signal.
30, method as claimed in claim 29 further comprises: voltage controlled oscillator (VCO) circuit is included in the described transmitter circuitry.
31, method as claimed in claim 30 further comprises:
Described first circuit part is integrated in first integrated circuit (IC) apparatus; And
Described second circuit is partially integrated in second integrated circuit (IC) apparatus.
32, method as claimed in claim 30 further comprises:
The tertiary circuit that comprises local oscillator circuit part is provided;
Utilize described local oscillator circuit that radio frequency (RF) signal is offered described receiver analog circuit and described transmitter circuitry;
Further utilize described local oscillator circuit that intermediate frequency (IF) signal is offered described transmitter circuitry; And
Separate described first, second and tertiary circuit part to be convenient to reduce the disturbing effect in described first, second and the tertiary circuit part.
33, method as claimed in claim 32 further comprises:
Described first circuit part is integrated in first integrated circuit (IC) apparatus;
Described second circuit is partially integrated in second integrated circuit (IC) apparatus; And
Described tertiary circuit is partially integrated in the 3rd integrated circuit (IC) apparatus.
34, method as claimed in claim 32 further comprises:
Digital to analog converter (DAC) circuit is included in the described digital receiver circuit; And
By utilizing digital-to-analog circuit, described digital received conversion of signals is become analog receiving signal.
35, method as claimed in claim 34 further comprises:
Described first circuit part is integrated in first integrated circuit (IC) apparatus;
Described second circuit is partially integrated in second integrated circuit (IC) apparatus; And
Described tertiary circuit is partially integrated in the 3rd integrated circuit (IC) apparatus.
36, a kind of method that is used to separate radio frequency (RF) transceiver circuit comprises:
First circuit part that comprises receiver analog circuit and transmitter circuitry is provided;
Utilize described receiver analog circuit to accept the RF signal that is received and at least one digital output signal is provided;
Utilizing described transmitter circuitry to receive at least one sends input signal and transmission RF is provided signal;
The second circuit that comprises local oscillator circuit part is provided;
Utilize described local oscillator circuit to accept reference signal, and radio frequency (RF) signal is offered described receiver analog circuit and described transmitter circuitry; And
Separate described first circuit part and described second circuit part to be convenient to reduce the disturbing effect between described first circuit part and described second circuit part.
37, method as claimed in claim 36 further comprises transmission voltage controlled oscillator (VCO) circuit is included in the described transmitter circuitry.
38, method as claimed in claim 37 further comprises and utilizes described receiver analog circuit that described at least one digital output signal is offered baseband processor circuit outside described first and second circuit parts.
39, method as claimed in claim 38 further comprises:
The analog down converter circuit is included in the described receiver analog circuit;
Utilize described analog down converter circuit to accept the RF signal that is received and the analog down signal is provided;
Analog to digital converter (ADC) circuit is provided in described receiver analog circuit;
Described analog-digital converter circuit is coupled to described baseband processor circuit; And
Utilize described analog-digital converter circuit to receive the analog down signal and at least one digital output signal of described receiver analog circuit is provided.
40, method as claimed in claim 39 further comprises:
The formula that affords redress phase-locked loop (PLL) circuit;
Described compensation phase-locked loop circuit is coupled to the transmission voltage-controlled oscillator circuit;
The base band up-converter circuits is included in the described transmitter circuitry; And
Utilize described base band up-converter circuits accept described at least one send input signal and intermediate frequency (IF) signal offered described compensation phase-locked loop circuit.
41, the method for stating as claim 40 further comprises:
Be provided at the standard signal generator circuit outside described first and second circuit parts; And
Utilize described standard signal generator circuit that described reference signal is offered described second circuit part.
42, method as claimed in claim 41 further comprises described standard signal generator circuit is included in the described baseband processor circuit.
43, method as claimed in claim 41, further comprise at least one digital output signal of utilizing described baseband processor circuit to receive described receiver analog circuit and with described at least one send input signal and offer described base band up-converter circuits.
44, method as claimed in claim 43 further comprises:
Described first circuit part is integrated in first integrated circuit (IC) apparatus; And
Described second circuit is partially integrated in second integrated circuit (IC) apparatus.
45, method as claimed in claim 37 further comprises:
The tertiary circuit that comprises digital receiver circuit part is provided;
Utilize described digital receiver circuit to receive at least one digital output signal of described receiver analog circuit; And
Separate described first, second and tertiary circuit part to be convenient to reduce the disturbing effect in described first, second and the tertiary circuit part.
46, method as claimed in claim 45 further comprises:
In described receiver analog circuit, provide the analog down converter circuit;
Utilize described analog down converter circuit to accept the RF signal that is received and the analog down signal is provided;
Analog to digital converter (ADC) circuit is provided in described receiver analog circuit; And
By using analog-digital converter circuit, described analog down conversion of signals is become at least one digital output signal of described receiver analog circuit.
47, method as claimed in claim 46 further comprises:
In described digital receiver circuit, provide the digital down converter circuit;
Utilize described digital down converter circuit to receive at least one digital output signal of described receiver analog circuit and at least one Digital Down Convert signal is provided;
In described digital receiver circuit, provide digital filter circuit; And
By using described digital filter circuit to filter described at least one down-conversion digital signal so that produce at least one digital filtered signal.
48, method as claimed in claim 47 further comprises:
The formula that affords redress phase-locked loop (PLL) circuit;
Described compensation phase-locked loop circuit is coupled to the transmission voltage-controlled oscillator circuit;
The base band up-converter circuits is included in the transmitter circuitry; And
Utilizing described base band up-converter circuits to accept at least one sends input signal and intermediate frequency (IF) signal is offered described compensation phase-locked loop circuit.
49, method as claimed in claim 48 further comprises:
Be provided at the standard signal generator circuit outside described first, second and the tertiary circuit; And
Utilize described standard signal generator circuit that described reference signal is offered described second and the tertiary circuit part.
50, method as claimed in claim 49 further comprises:
Outside baseband processor circuit is provided; And
At least one filtered digital signal of utilizing described outside baseband processor circuit to receive described digital filter circuit also offers described base band up-converter circuits with described at least one transmission input signal.
51, method as claimed in claim 50 further is included in described standard signal generator circuit is provided in the described baseband processor circuit.
52, method as claimed in claim 51 further comprises:
Described first circuit part is integrated in first integrated circuit (IC) apparatus;
Described second circuit is partially integrated in second integrated circuit (IC) apparatus; And
Described tertiary circuit is partially integrated in the 3rd integrated circuit (IC) apparatus.
53, method as claimed in claim 49 further comprises:
Digital to analog converter (DAC) circuit is provided in described digital receiver circuit; And
Utilize described d convertor circuit to come to accept described at least one filtered digital signal and at least one analog receiving signal is provided from described digital filter circuit.
54, method as claimed in claim 53 further comprises:
Described first circuit part is integrated in first integrated circuit (IC) apparatus;
Described second circuit is partially integrated in second integrated circuit (IC) apparatus; And
Described tertiary circuit is partially integrated in the 3rd integrated circuit (IC) apparatus.
Applications Claiming Priority (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US26150601P | 2001-01-12 | 2001-01-12 | |
| US60/261,506 | 2001-01-12 | ||
| US27311901P | 2001-03-02 | 2001-03-02 | |
| US60/273,119 | 2001-03-02 | ||
| US09/821,342 | 2001-03-29 | ||
| US09/821,342 US6804497B2 (en) | 2001-01-12 | 2001-03-29 | Partitioned radio-frequency apparatus and associated methods |
| US09/821,340 | 2001-03-29 | ||
| US09/821,340 US7158574B2 (en) | 2001-01-12 | 2001-03-29 | Digital interface in radio-frequency apparatus and associated methods |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1531783A true CN1531783A (en) | 2004-09-22 |
| CN100449952C CN100449952C (en) | 2009-01-07 |
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Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA028048547A Pending CN1507698A (en) | 2001-01-12 | 2002-01-10 | Digital interface in radio-frequency apparatus and associated methods |
| CNB028048555A Expired - Fee Related CN100449952C (en) | 2001-01-12 | 2002-01-10 | Partitioned radio-frequency apparatus and associated methods |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA028048547A Pending CN1507698A (en) | 2001-01-12 | 2002-01-10 | Digital interface in radio-frequency apparatus and associated methods |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP1350331A2 (en) |
| CN (2) | CN1507698A (en) |
| AU (2) | AU2002241865A1 (en) |
| WO (2) | WO2002056488A2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102111142A (en) * | 2009-12-29 | 2011-06-29 | 海力士半导体有限公司 | Interface apparatus for semiconductor integrated circuit and interfacing method thereof |
| CN105092081A (en) * | 2015-08-14 | 2015-11-25 | 深圳华远微电科技有限公司 | Anti-interference temperature signal receiver and signal processing method |
| CN105580282A (en) * | 2013-09-23 | 2016-05-11 | 高通股份有限公司 | A fully integrated modular millimeter-wave radio frequency system |
| CN111507054A (en) * | 2019-01-31 | 2020-08-07 | 株式会社村田制作所 | Digital output monitoring circuit and high-frequency front-end circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6421372B1 (en) * | 1999-11-10 | 2002-07-16 | Itt Manufacturing Enterprises, Inc. | Sequential-acquisition, multi-band, multi-channel, matched filter |
| FR2851391B1 (en) * | 2003-02-18 | 2005-05-06 | Wavecom | SYSTEM FOR PROCESSING SIGNALS RECEIVED AND ISSUED BY A RADIO COMMUNICATION APPARATUS HAVING TWO MODULES, MODULE AND DEVICE CORRESPONDING |
| US8903348B2 (en) * | 2003-02-19 | 2014-12-02 | Csr Technology Inc. | Serial radio frequency to baseband interface with power control |
| US8144810B2 (en) * | 2003-02-19 | 2012-03-27 | Csr Technology Inc. | Serial radio frequency to baseband interface with programmable clock |
| US6987953B2 (en) | 2003-03-31 | 2006-01-17 | Nortel Networks Limited | Digital transmitter and method |
| US7136430B2 (en) | 2003-03-31 | 2006-11-14 | Nortel Networks Limited | Digital receiver and method |
| DE10323349A1 (en) * | 2003-05-23 | 2004-12-23 | Newlogic Technologies Ag | Transferring data between radio transceiver unit and digital baseband processing unit involves transmitting data via serial digital interface, whereby connected communications protocol is used |
| EP1792410B1 (en) | 2004-09-06 | 2009-02-11 | Freescale Semiconductors, Inc. | Wireless communication device and data interface |
| US8090001B2 (en) | 2004-12-03 | 2012-01-03 | Lantiq Deutschland Gmbh | Fast frequency-hopping transceiver and method |
| GB0709813D0 (en) * | 2007-05-22 | 2007-07-04 | Nokia Corp | A radio frequency apparatus |
| US9841455B2 (en) * | 2015-05-20 | 2017-12-12 | Xilinx, Inc. | Transmitter configured for test signal injection to test AC-coupled interconnect |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5165055A (en) * | 1991-06-28 | 1992-11-17 | Digital Equipment Corporation | Method and apparatus for a PCB and I/O integrated electromagnetic containment |
| US5859878A (en) * | 1995-08-31 | 1999-01-12 | Northrop Grumman Corporation | Common receive module for a programmable digital radio |
| SE9703944L (en) * | 1997-10-29 | 1999-04-30 | Ericsson Telefon Ab L M | Radio communication device and method |
-
2002
- 2002-01-10 WO PCT/US2002/000895 patent/WO2002056488A2/en not_active Application Discontinuation
- 2002-01-10 AU AU2002241865A patent/AU2002241865A1/en not_active Abandoned
- 2002-01-10 CN CNA028048547A patent/CN1507698A/en active Pending
- 2002-01-10 EP EP02709016A patent/EP1350331A2/en not_active Withdrawn
- 2002-01-10 AU AU2002243524A patent/AU2002243524A1/en not_active Abandoned
- 2002-01-10 CN CNB028048555A patent/CN100449952C/en not_active Expired - Fee Related
- 2002-01-10 WO PCT/US2002/000896 patent/WO2002056487A2/en not_active Application Discontinuation
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102111142A (en) * | 2009-12-29 | 2011-06-29 | 海力士半导体有限公司 | Interface apparatus for semiconductor integrated circuit and interfacing method thereof |
| CN102111142B (en) * | 2009-12-29 | 2015-04-08 | 海力士半导体有限公司 | Interface apparatus for semiconductor integrated circuit |
| CN105580282A (en) * | 2013-09-23 | 2016-05-11 | 高通股份有限公司 | A fully integrated modular millimeter-wave radio frequency system |
| CN105580282B (en) * | 2013-09-23 | 2019-04-30 | 高通股份有限公司 | Fully integrated modularization mm wave RF system |
| CN105092081A (en) * | 2015-08-14 | 2015-11-25 | 深圳华远微电科技有限公司 | Anti-interference temperature signal receiver and signal processing method |
| CN105092081B (en) * | 2015-08-14 | 2017-12-12 | 深圳华远微电科技有限公司 | Anti-tampering temperature signal receiver and signal processing method |
| CN111507054A (en) * | 2019-01-31 | 2020-08-07 | 株式会社村田制作所 | Digital output monitoring circuit and high-frequency front-end circuit |
| CN111507054B (en) * | 2019-01-31 | 2023-11-03 | 株式会社村田制作所 | Digital output monitoring circuit and high frequency front-end circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2002056488A2 (en) | 2002-07-18 |
| EP1350331A2 (en) | 2003-10-08 |
| WO2002056488A3 (en) | 2003-03-06 |
| CN100449952C (en) | 2009-01-07 |
| WO2002056487A3 (en) | 2003-03-06 |
| AU2002241865A1 (en) | 2002-07-24 |
| WO2002056487A2 (en) | 2002-07-18 |
| CN1507698A (en) | 2004-06-23 |
| AU2002243524A1 (en) | 2002-07-24 |
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