CN1521634A - Virtual NOR type flash memory - Google Patents
Virtual NOR type flash memory Download PDFInfo
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- CN1521634A CN1521634A CNA031031978A CN03103197A CN1521634A CN 1521634 A CN1521634 A CN 1521634A CN A031031978 A CNA031031978 A CN A031031978A CN 03103197 A CN03103197 A CN 03103197A CN 1521634 A CN1521634 A CN 1521634A
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Abstract
A virtual NOR type flash memory comprises a static state random memory used as high speed buffer, a NAND type flash memory used for storing program and data, and a quick access control circuit in data transmission and communication with the external system, and connected to the static state random memory and the NAND type flash memory, so as to transform the first reading command in a time pulse cycle into a second reading command, and to read the quick access data stored in the static state random memory, thus transforming the first write command into the second write command.
Description
Technical field
The present invention relates to a kind of flash memory (Flash Memory), particularly a kind of virtual NOR type flash memory is in the electronic equipment or the signal conditioning package of mobile phone, computing machine, personal digital assistant, handheld computer etc.
Background technology
With regard to the structure of flash memory (Flash Memory), generally can be divided into NOR and NAND two macrostructures, some difference of its technical characteristic is respectively described below.
NOR type flash memory: be called program conversion hysteria flash memory again, this is the structure that is developed by Intel (Intel), writing speed is slow, reading speed is very fast, and can on unit block (Block), carry out the read/write of instruction repertorie, its characteristic is high voltage, long time of erasing and the relatively large block of erasing.This type product mostly is applied in storage and the read/write and the PC memory card of programmed instruction.Yet it has the problem of cost and capacity.
NAND type flash memory: be called data access type flash memory again, by the structure that Japanese Toshiba (Toshiba) is developed, the speed that reads and writes data is slower, but has less memory area (MemoryCell), and under equal densities, cost is low than NOR Type Flash.Be applicable in the product development and mass storage of high power capacity more, can be in order to substituting disc driver in the status in Portable market, or use as the consumption electronic products data storing.
The structure of present many use NOR type flash memories as shown in Figure 1, calcspar for known use NOR type flash memory, its memory construction mainly comprises NOR type flash memory 10 and static RAM 20, wherein NOR type flash memory is in order to stored routine or data, the high-speed cache when static RAM 20 is then carried out as program.NOR type flash memory 10 and static RAM 20 are by joining by bus 40 and circuit system memory interface 30, circuit system memory interface 30 is a NOR type flash interface, in order to carry out read operation, write operation according to the read cycle in the clock pulse, write cycle and the cycle of removing and to remove operation.
In order to meet the requirement of demand high storage capacity, only can adopt more NOR type flash memory at sort memory to increase memory capacity.It mainly is the relation of itself capacity limit.
Constantly weed out the old and bring forth the new at present carry-on digital product, function is also maked rapid progress, and constantly increases, and therefore is being subject under the condition of its volume, and the space of its storage can't obtain a preferable settling mode in the short time.Mainly be because need be than the storer of high storage capacity with store program code, must meet requirement low-cost and small size again simultaneously, therefore, a kind of storer can have the advantage of the data access speed and the NAND type flash memory stores capacity of NOR type flash memory simultaneously, for hand-held or portable electronic information products, be a technical task that needs to be resolved hurrily in fact.
Summary of the invention
In view of above problem, fundamental purpose of the present invention is to provide a kind of virtual NOR type flash memory, uses solving above-mentioned NOR type flash memory and the existing problem of NAND type flash memory simultaneously, and has the advantage of NOR type flash memory and NAND type flash memory simultaneously.
Disclosed virtual NOR type flash memory, mainly be utilize a NOR type flash interface circuit as with the interface of systems communicate data, the storage core of storer then adopts NAND type flash memory, and with static RAM as high-speed cache.Because many system designs at present all only can be done communication with NOR type flash memory, therefore, under the restriction of system itself, can be by NOR type flash interface originally and disclosed virtual NOR type flash memory communication Data transmission.Why be called virtual, be because system and storer with the foundation of NOR type flash interface as the data communication, and in fact program and data storing in NAND type flash memory.By this design, can take into account the advantage of NOR type flash memory and NAND type flash memory, solve the problem that present hand-held massaging device or electronic type device storage volume can't promote.
According to the notion of disclosed NOR type flash memory, get the interface of control circuit soon by means of one as data-switching, that is, with system carry out data link up with the interface that transmits be NOR type flash interface.At first receive one first data access order by NOR type flash interface, then the first data access command conversion is become the second data access order by getting control circuit soon, make that the second data access order can be by the static RAM interface carrying out the operation of data access (read/write/remove) to static RAM, or NAND type flash memory is carried out the operation of data access (read/write/remove) by NAND type flash interface.In cycle, the order of reading (read), writing (write) and removing (erase) is arranged respectively at different clock pulses in the data access order.When at read cycle, get control circuit soon and will carry out one and get function soon, whether in static RAM,, then carry out the order of a data acquisition and the hit page in the replacement high-speed cache to check the data that will read if data do not exist.When writing and remove the cycle, get control circuit soon and then first write command/first removed second write command/second that command conversion becomes may command NAND type high-speed cache and remove order.
Therefore, for reaching above-mentioned purpose, disclosed virtual NOR type flash memory includes a static RAM, in order to as high-speed cache; One NAND type flash memory is in order to store a program and data; And one get control circuit soon, carry out data transfer and communication by a NOR type flash interface and external system, and join with this static RAM and this NAND type flash memory, in order to convert clock pulse 1 in the cycle first reading order to a second reading command fetch, be stored in caching data in this static RAM to read, convert one first write command to one second write command, data are write in this NAND type flash memory, remove command conversion with one first and become one second to remove order, so that data are removed in this NAND type flash memory.
Wherein, get control circuit soon and more carry out a management of cache operation and a preload cache operations, wherein the operation of this management of cache in order to according to program performed in this NAND type flash memory with the required capacity of decision high-speed cache, the cache capacity that this preload cache operations is then determined according to this management of cache operation in this static RAM preload one zone as high-speed cache.
By disclosed interface control circuit, make on present running gear, portable electric device the primary structure with storer replace by NAND type flash memory, under present restriction, higher memory capacity is provided, and does not need to increase the area and the cost of memory chip.
About feature of the present invention and enforcement, conjunction with figs. is described in detail as follows as most preferred embodiment now.
Description of drawings
Fig. 1 is the calcspar of known use NOR type flash memory;
Fig. 2 is the calcspar of disclosed virtual NOR type flash memory; And
Fig. 3 is the calcspar of getting control circuit soon in the disclosed virtual NOR type flash memory.
Symbol description among the figure
10 NOR type flash memories
20 static RAM
30 circuit system memory interfaces
40 buses
50 NAND type flash memories
60 get control circuit soon
61 interface conversion circuits
62 get management circuit soon
63 static RAM interfaces
64 nand flash memory interfaces
70 NOR type flash interfaces
Embodiment
The present invention is mainly disclosing a kind of control circuit of getting soon, in order to will converting the second data access order of may command NAND type flash memory and static RAM with the first data access order (read/write/remove) in the data access of the NOR type flash memory compatibility control clock pulse to, this changes the mechanism and gets control circuit soon by one and finish.
Virtual NOR type flash memory about disclosed please refer to Fig. 2, is the calcspar of disclosed virtual NOR type flash memory, include a NAND type flash memory 50, one static RAM 20, is got control circuit 60 soon, and a NOR type flash interface 70.
Get soon that circuit block diagram please refer to Fig. 3 in the control circuit 60, include an interface conversion circuit 61, and get management circuit 62, a static RAM interface 63 and a nand flash memory interface 64 soon.The following description please also refer to Fig. 2 and Fig. 3.
At first receive one first data access order by NOR type flash interface 70, then the first data access command conversion is become the second data access order by getting control circuit 60 soon, make that the second data access order can be by static RAM interface 63 carrying out the operation of data access (read/write/remove) to static RAM 20, or carry out the operation of data access (read/write/remove) by 64 pairs of NAND types of NAND type flash interface flash memory 50.In cycle, the order of reading (read), writing (write) and removing (erase) is arranged respectively at different clock pulses in the data access order.When at read cycle, getting control circuit 60 soon will carry out one and get function soon, to check that the data that will read are whether in static RAM 20, if data do not exist, then carry out hold the data available command and replace the cache memory to the hit page.When writing and remove the cycle, get control circuit soon and then first write command/first removed second write command/second that command conversion becomes may command NAND type high-speed cache and remove order.
Use its data access speed of disclosed storer must be close,, make the hit rate of high-speed cache (cache memory) can rise to 100%, to avoid the loss of data by the assistance of software with NOR type flash memory.
The management circuit of getting soon in the control circuit 60 62 of getting soon is respectively management of cache operation and preload cache operations.Management of cache operation in order to according to program performed in the NAND type flash memory with the required capacity of decision high-speed cache, the preload cache operations cache capacity that then operation is determined according to management of cache in 20 years one zones of static RAM as high-speed cache.Use the time that shortens data access, and provide do not have lose (no-miss) get management (cache management) soon.
The present invention directly is directly connected in interface control circuit between NAND type flash memory and the circuit system memory interface.Directly connection will have a problem to take place, and not allow data to lose because get management soon, if the situation that has access data to lose will cause system to work as machine.Therefore cooperate disclosed memory construction, propose a program management software.The program research staff program is write finish after, again program compilation is become last execute file before, by program management software program is done scan and reform (pre-arrangement).In resurfacing operation, in order to the instruction of confirming long-range jump (far-jump) and relative address.Because in the program code of assembly language, the instruction of long-range jump makes system that the situation of machine takes place to work as easily, and the situation that data are lost also takes place in memory construction of the present invention easily.Therefore, weave into carry out shelves before, be about to program code earlier rearrange, order in getting soon in the control circuit by inserting a preload (pre-load), before original instruction is carried out, to require the pre-load order code, the situation that can avoid data to lose.
In the function of storer, generally static RAM is used as high-speed cache.The present invention equally with static RAM as high-speed cache.Because different programs may need different cache memory sizes, therefore, getting management circuit 62 soon will be according to the function of asking the planning cache memory sizes.
System does the transmission and the communication of data with NOR type flash interface and disclosed memory construction, that is read (read), write (write) and remove (erase) three kinds of operations and will finish by NOR type flash interface and disclosed memory construction, below illustrate how to reach this three kinds of operations respectively.
Carry out the preload cache operations by the management circuit of getting soon in the control circuit 60 62 of getting soon, all data will be stated from the random access memory 63 in advance in advance, therefore when the read cycle in the clock pulse signal arrives, interface conversion circuit can convert first reading order to the second reading command fetch with static RAM 20 compatibilities, getting control circuit 60 soon will will be stored in the data load system in the high-speed cache according to this read cycle, and its reading speed will be faster than NOR type flash memory.This be because, the access speed of NOR type flash memory is greatly about about 55ns, therefore the data reading speed of back level must be faster than 55ns, just do not have the situation that data lose and take place.By disclosed structure, its reading speed is greatly about about 35ns.Therefore, can meet this requirement.
When writing with read operation, to get management circuit 62 soon and enter idle mode, detailed process is described as follows.
When clock pulse is positioned at the cycle that writes, interface conversion circuit 61 can convert first write command to second write command with NAND type flash memory 64 compatibilities, then get management circuit 62 soon data are write high-speed cache in the static RAM 20 earlier, after getting management circuit 62 soon and entering idle mode, data are write in the NAND type flash memory 64 again.
Same, when clock pulse is positioned at the cycle that removes, interface conversion circuit 61 will remove command conversion with first and become with second of NAND type flash memory 64 compatibilities to remove order, with the data that remove earlier in the high-speed cache, after getting management circuit 62 soon to enter idle mode (idlemode), remove the data that are stored in the NAND type flash memory 64 again before removing again.
When new program was carried out, fast fetch pointer (cache pointer) can increase by 1 on original value.By getting the function of management soon, pointer will refer to forever in optimal address.
By disclosed interface control circuit, make on present running gear, portable electric device the primary structure with storer replace by NAND type flash memory, under present restriction, higher memory capacity is provided, and does not need to increase the area and the cost of memory chip.
Though the present invention discloses as above with aforesaid preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of art technology person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, therefore scope of patent protection of the present invention must be looked this instructions and claims scope person of defining is as the criterion.
Claims (18)
1. virtual NOR type flash memory in order to carrying out a read operation, write operation or to remove operation according to the clock pulse cycle of a NOR type flash memory, is characterized in that this storer includes:
One static RAM is in order to as high-speed cache;
One NAND type flash memory is in order to store a program and data; And
One gets control circuit soon, carry out data transfer and communication by a NOR type flash interface and external system, and join with this static RAM and this NAND type flash memory, in order to convert clock pulse 1 in the cycle first reading order to a second reading command fetch, be stored in caching data in this static RAM to read, convert one first write command to one second write command, data are write in this NAND type flash memory, remove command conversion with one first and become one second to remove order, so that data are removed in this NAND type flash memory.
2. virtual NOR type flash memory as claimed in claim 1, it is characterized in that, this is got control circuit soon and more includes an interface conversion circuit, join with this NOR type flash interface, in order to this first reading order, this first write command first are removed command conversion and become this second reading command fetch, this second write command and this second to remove order with this.
3. virtual NOR type flash memory as claimed in claim 1, it is characterized in that, more include one and get management circuit soon, in order to carry out a management of cache operation and a preload cache operations, wherein the operation of this management of cache in order to according to program performed in this NAND type flash memory with the required capacity of decision high-speed cache, the cache capacity that this preload cache operations is then determined according to this management of cache operation in this static RAM preload one zone as high-speed cache.
4. virtual NOR type flash memory as claimed in claim 1 is characterized in that this is got control circuit soon and more includes a static RAM interface, makes this second reading command fetch to read data in this static RAM by this interface.
5. virtual NOR type flash memory as claimed in claim 1, it is characterized in that, this is got control circuit soon and more includes a NAND type flash interface, makes this second write command and second remove order and can data be write in this NAND type flash memory or certainly by this interface and remove in this NAND type flash memory.
6. virtual NOR type flash memory as claimed in claim 1 is characterized in that, this first reading order and this NOR type flash memory compatibility.
7. virtual NOR type flash memory as claimed in claim 1 is characterized in that, this first write command and this NOR type flash memory compatibility.
8. virtual NOR type flash memory as claimed in claim 1 is characterized in that, this first removes order and this NOR type flash memory compatibility.
9. virtual NOR type flash memory as claimed in claim 1 is characterized in that, this second reading command fetch and this static RAM compatibility.
10. virtual NOR type flash memory as claimed in claim 1 is characterized in that, this second write command and this nand flash memory compatibility.
11. virtual NOR type flash memory as claimed in claim 1 is characterized in that, this second removes order and this nand flash memory compatibility.
12. a virtual NOR type flash memory get control circuit soon, one static RAM and a NAND type flash memory are carried out a read operation, write operation or are removed operation in order to the clock pulse cycle according to a NOR type flash memory, include:
One interface conversion circuit joins with a NOR type flash interface, becomes a second reading command fetch, one second write command and one second to remove order in order to clock pulse 1 in the cycle first reading order, first write command and one first are removed command conversion;
One gets management circuit soon, join with this interface conversion circuit, in order to carry out a management of cache operation and a preload cache operations, wherein the operation of this management of cache in order to according to program performed in this NAND type flash memory with the required capacity of decision high-speed cache, the cache capacity that this preload cache operations is then determined according to this management of cache operation in this static RAM preload one zone as high-speed cache;
One static RAM interface makes this second reading command fetch to read data in this static RAM by this interface; And
One NAND type flash interface makes this second write command and second remove order and can data be write in this NAND type flash memory or certainly by this interface and remove in this NAND type flash memory.
13. the virtual NOR type of void as claimed in claim 12 flash memory get control circuit soon, it is characterized in that this first reading order and this NOR type flash memory compatibility.
14. virtual NOR type flash memory as claimed in claim 12 get control circuit soon, it is characterized in that this first write command and this NOR type flash memory compatibility.
15. virtual NOR type flash memory as claimed in claim 12 get control circuit soon, it is characterized in that this first removes order and this NOR type flash memory compatibility.
16. virtual NOR type flash memory as claimed in claim 12 get control circuit soon, it is characterized in that this second reading command fetch and this static RAM compatibility.
17. virtual NOR type flash memory control circuit as claimed in claim 12 is characterized in that, this second write command and this NANNAND flash memory compatibility.
18. virtual NOR type flash memory as claimed in claim 12 get control circuit soon, it is characterized in that this second removes order and this nand flash memory compatibility.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA031031978A CN1521634A (en) | 2003-02-11 | 2003-02-11 | Virtual NOR type flash memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA031031978A CN1521634A (en) | 2003-02-11 | 2003-02-11 | Virtual NOR type flash memory |
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| Publication Number | Publication Date |
|---|---|
| CN1521634A true CN1521634A (en) | 2004-08-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA031031978A Pending CN1521634A (en) | 2003-02-11 | 2003-02-11 | Virtual NOR type flash memory |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100456266C (en) * | 2005-12-27 | 2009-01-28 | 三星电子株式会社 | Demand paging apparatus and method for embedded system |
| WO2009086692A1 (en) * | 2008-01-07 | 2009-07-16 | Fortune Spring Technology (Shenzhen) Corporation | A processing method for embedded system using nand flash to memorize and start up |
-
2003
- 2003-02-11 CN CNA031031978A patent/CN1521634A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100456266C (en) * | 2005-12-27 | 2009-01-28 | 三星电子株式会社 | Demand paging apparatus and method for embedded system |
| WO2009086692A1 (en) * | 2008-01-07 | 2009-07-16 | Fortune Spring Technology (Shenzhen) Corporation | A processing method for embedded system using nand flash to memorize and start up |
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