CN1520039A - Phase frequency detection device and method for reducing influence of mutation interference - Google Patents
Phase frequency detection device and method for reducing influence of mutation interference Download PDFInfo
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- CN1520039A CN1520039A CNA031029906A CN03102990A CN1520039A CN 1520039 A CN1520039 A CN 1520039A CN A031029906 A CNA031029906 A CN A031029906A CN 03102990 A CN03102990 A CN 03102990A CN 1520039 A CN1520039 A CN 1520039A
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Abstract
The detection device utilized in a phase locked loop compares target clock signal generated from feed back of the phase locked loop with an intended signal of reference clock as well as outputs a group of control signal. The said group of control signal is utilized to control the target clock signal to be synchronized with the intended signal of reference clock in following steps. The regulating system includes a reset module and a switching module. The reset module calculates the group of control signal, and if reset condition is accordant, the reset module outputs a group of reset signal. The switching module calculates the reset signal, and if switching condition is accordant, the switching module makes switching between normal operation mode and abrupt transition protection mode. When the detection device is in abrupt transition protection mode and the reset condition is accordant, the reset module outputs reset signal and resets the phase frequency detection device.
Description
Technical field
The present invention refers in particular to the phase frequency checkout gear and the method for the influence that can reduce mutation disturbance about the regulating system of a phase frequency checkout gear.
Background technology
See also Fig. 1, Fig. 1 is applied to the schematic diagram of a phase-locked loop 10 for known phase frequency checkout gear 12 with a pair of trigger structure.A known phase-locked loop 10 comprises a phase frequency checkout gear 12, and charges and discharge electric pump 40, a voltage controlled oscillator 42 and a frequency divider 44.Known phase frequency checkout gear 12 with a pair of trigger structure often is applied to phase-locked loop 10.Phase frequency checkout gear 12 is in order to comparing from a target clock signal 20 and a predetermined reference clock signal 22 of 10 feedback generation in phase-locked loop, and export one group of control signal 26,28, and in subsequent control target clock signal 20 with synchronous with reference clock signal 22.
Charging and discharging electric pump 40 is control signals 26,28 of being exported in order to receiving phase frequency detecting device 12, and exports a control voltage 46.Voltage controlled oscillator 42 is to produce a corresponding data clock signal 48 (data clock) according to control voltage 46.Frequency divider 44 be with a predetermined divisor with data clock signal 48 frequency divisions, and produce target clock signal 20.Phase frequency checkout gear 12 is promptly by above-mentioned flow process, constantly target clock signal 20 and reference clock signal 22 are compared, and constantly export this group control signal with feedback target clock signal 20, so that target clock signal 20 reaches synchronous with reference clock signal 22.
See also Fig. 2, Fig. 2 is the sequential chart of phase-locked loop 10 shown in Figure 1.In the sequential chart of Fig. 2, the transverse axis express time, the longitudinal axis is represented signal amplitude.During beginning, there is a phase difference P in target clock signal 20 with reference clock signal 22.When sudden change 16 betides target clock signal 20 or reference clock signal 22 suddenly (not being shown in Fig. 2), owing to sudden change 16 influence has changed control signal 26,28 by 12 outputs of phase frequency checkout gear, 16 control signals that influence 26,28 of being suddenlyd change demonstrate target clock signal 20 and have a phase difference Q with reference clock signal 22.Yet in fact only there is a phase difference P in target clock signal 20 with reference clock signal 22.Therefore because the cause of sudden change 16, the phase difference that often makes phase frequency checkout gear 12 take for target clock signal 20 and reference clock signal 22 changes suddenly, and export one group of 16 control signal that influence 26,28 of being suddenlyd change, this group control signal 26,28 is again via above-mentioned path, therefore the target clock signal 20 of another corresponding feedback of output has disturbed work originally greatly.
The reason of time, place and generation that sudden change 16 takes place all can't be done comprehensive prediction and prevention with mechanism.Known in addition phase-locked loop 10 only utilizes phase frequency checkout gear 12 and feedback control circuit 18, comes controlled target clock signal 20, makes itself and this reference clock signal 22 synchronous.Take place as sudden change 16, or the phase difference of target clock signal 20 and reference clock signal 22 often needs spend the long time just can make target clock signal 20 and reference clock signal 22 reach synchronous state when differing big.
Therefore, main purpose of the present invention is to provide a kind of regulating system 14 and method of control phase frequency detecting device 12, to address the above problem.
Summary of the invention
The purpose of this invention is to provide a kind of regulating system and method that is used for regulating the phase frequency checkout gear in the phase-locked loop, with the phase-locked ability that promotes this phase-locked loop and improve its phase-locked efficient.Particularly when sudden change entered this phase frequency checkout gear, regulating system of the present invention can be corrected the confusion that is caused because of sudden change in the short time.
According to of the present invention one preferred specific embodiment, the invention provides a kind of regulating system that is used for regulating a phase frequency checkout gear.This phase frequency checkout gear is to use in a phase-locked loop, comparing from a target clock signal and a predetermined reference clock signal of this phase-locked loop institute feedback generation, and export one group of control signal, and in this target clock signal of subsequent control with synchronous with this reference clock signal.This regulating system comprises a replacement module and all die change pieces.This replacement module is to be used for calculating this group control signal, and when meeting a default replacement condition, exports one group of reset signal.This handover module is to be used for calculating this group reset signal, and when meeting a default switching condition, this phase frequency checkout gear is suddenlyd change in a normal manipulation mode and switch between the protected mode.If this phase frequency checkout gear is to be under this sudden change protected mode, and when should the default replacement condition of replacement module meeting, this group reset signal this phase frequency checkout gear of can exporting and reset.
Therefore; regulating system provided by the present invention; when the phase frequency checkout gear is in the sudden change protected mode; if when having sudden change to take place; because the cause that reset signal can be reset the phase frequency checkout gear; therefore the control signal that will be suddenlyd change influences forces to make zero; thereby the reduction sudden change is for the influence that interference caused of control signal and this feedback control circuit; so can solve that the phase-locked loop is subjected to mutation disturbance and the shortcoming that reduced the operating efficiency of phase frequency checkout gear; and shorten making target clock signal and reference clock signal reach the synchronous time, and can promote the operating efficiency of phase-locked loop.
Can be about the advantages and spirit of the present invention by following detailed Description Of The Invention and appended graphic being further understood.
Description of drawings
Fig. 1 is applied to the schematic diagram of a phase-locked loop for known phase frequency checkout gear with a pair of trigger structure;
Fig. 2 is the sequential chart of phase-locked loop shown in Figure 1;
Fig. 3 is used for the schematic diagram of the regulating system of a phase-locked loop for the present invention;
Fig. 4 A and Fig. 4 B are the sequential chart of target clock signal, reference clock signal and control signal shown in Figure 3;
Sequential chart when Fig. 5 undergos mutation for the reference clock signal of Fig. 3;
Sequential chart when Fig. 6 undergos mutation for the target clock signal of Fig. 3;
The sequential chart of each coherent signal when Fig. 7 switches to the sudden change protected mode for normal manipulation mode of the present invention;
The sequential chart of each coherent signal when Fig. 8 switches to normal manipulation mode for sudden change protected mode of the present invention;
Fig. 9 is the schematic diagram of the phase frequency checkout gear of Fig. 3;
Figure 10 A and Figure 10 B are the sequential chart that the control signal of another embodiment of the present invention produces; And
Figure 11 is a control method flow chart of the present invention.
The drawing reference numeral explanation
10,11: phase-locked loop 12: the phase frequency checkout gear
14: regulating system 16,17,19,21: sudden change
17a, 19a: undesired pulse 18: feedback control circuit
20: target clock signal 22: reference clock signal
28: the second control signals of 26: the first control signals
30: replacement module 32 handover modules
40: charge and discharge electric pump 42: voltage controlled oscillator
44: frequency divider 46: control voltage
48: data clock signal 49: square pulse
50,50a, 50b, 50c: positive edge
52,52a, 52b, 52c: negative edge
54: leading pulse 56 falls behind pulse
60: the second counters of 58: the first counters
61: or door 62,75: with door
64: the second reset signals of 63: the first reset signals
65,66: count value
68: the second switching values of 67: the first switching values
69: sudden change protected mode enable signal
70: counting clock signal 71,73: switching point
74: the second triggers of 72: the first triggers
The input port 77 in 76: the first: dashed line segment
78: the first mouthful 80: the first delivery outlets of resetting
84: the second replacement mouths in 82: the second input ports
86: the second delivery outlets
Embodiment
The purpose of this invention is to provide a kind of regulating system 14 and method that is used for regulating the phase frequency checkout gear 12 in the phase-locked loop 10, this regulating system 14 can promote the phase-locked ability of this phase-locked loop 10 (Phaselcoked loop) and improve its phase-locked efficient, particularly when sudden change 16 enters this phase frequency checkout gear 12, compared to known phase-locked loop 10, this regulating system 14 can be corrected because of 16 confusions that caused of suddenling change in the shorter time.
See also Fig. 3, Fig. 3 is used for the schematic diagram of the regulating system 14 of a phase-locked loop 11 for the present invention.The present invention is the regulating system 14 in order to regulate a phase frequency checkout gear 12.Phase-locked loop 11 comprises a phase frequency checkout gear 12, a regulating system 14 and a feedback control circuit 18.
Phase frequency checkout gear 12 is that the target clock signal 20 (target clock) from 11 feedback generation in phase-locked loop is compared with a predetermined reference clock signal 22 (reference clock), and export one group of control signal 26,28, and make target clock signal 20 and reference clock signal 22 synchronous in subsequent control.And this group control signal comprises one first control signal 26 and one second control signal 28.
Regulating system 14 comprises a replacement module 30 and all die change pieces 32.Replacement module 30 is to be used for calculation control signal 26,28, and when meeting default replacement (reset) condition, exports one group of reset signal 63,64.And reset signal 63,64 comprises one first reset signal 63 and one second reset signal 64.
See also Fig. 4 A and Fig. 4 B, Fig. 4 A and Fig. 4 B are the sequential chart of target clock signal 20, reference clock signal 22 and control signal 26,28 shown in Figure 3.Transverse axis express time in the sequential chart, the longitudinal axis is represented the amplitude of signal.Target clock signal 20 all comprises a plurality of square pulses 49 with reference clock signal 22, and each square pulse 49 respectively has a positive edge 50 (positive edge) and a negative edge 52 (negative edge).When the positive edge 50b of the leading adjacent target clock signal 20 of the positive edge 50a of reference clock signal 22, first control signal 26 can corresponding to both phase difference and produce a leading pulse 54 (as Fig. 4 A).And when the positive edge 50a of reference clock signal 22 lags behind the positive edge 50c of adjacent target clock signal 20, second control signal 28 also can corresponding to both phase difference and produce one and fall behind pulse 56 (as Fig. 4 B).And both phase differences of reference clock signal 22 and target clock signal 20 are to be directly proportional with the width of leading pulse 54 or the width that falls behind pulse 56.Fig. 4 A promptly represents the positive edge 50b of the leading adjacent target clock signal 20 of positive edge 50a of reference clock signal 22, and Fig. 4 B represents that promptly the positive edge 50a of reference clock signal 22 lags behind the positive edge 50c of adjacent target clock signal 20.
Shown in Fig. 3 and Fig. 4 A, B, replacement module 30 comprise one first counter 58 (counter), one second counter 60, one or door 61 (Or gate) with one with door 62 (And gate).First counter 58 can calculate the length of leading pulse 54 in first control signal 26 with a counting clock signal 70 (counter clock).When the length of leading pulse 54 took the lead the pulse upper limit value above one, first counter 58 can produce first reset signal 63.Second counter 60 can calculate the length of second control signal, 28 decline afterpulses 56 with counting clock signal 70.When the length that falls behind pulse 56 fell behind the pulse upper limit value above one, second counter 60 can produce second reset signal 64.When or door 61 when being transfused to one of them of first reset signal 63 and second reset signal 64, promptly meet this default replacement condition.Or door 61 can be with first reset signal 63 or 64 outputs of second reset signal.
See also Fig. 5 and Fig. 6, the sequential chart that Fig. 5 underwent mutation for the reference clock signal 22 of Fig. 3, the sequential chart that Fig. 6 underwent mutation for the target clock signal 20 of Fig. 3 at 17 o'clock at 19 o'clock.Transverse axis express time in the sequential chart, the longitudinal axis is represented the amplitude of signal.As shown in Figure 5, when reference clock signal 22 produces a sudden change 17 the time for some reason, 26 of first control signals can corresponding generation one undesired pulse 17a.As shown in Figure 6, and produce a sudden change for some reason 19 the time when target clock signal 20,28 of second control signals can corresponding generation one undesired pulse 19a.And when phase frequency checkout gear 12 is reset, undesired pulse 17a, the 19a of this group control signal 26,28 are made zero, and reduce sudden change 17 and suddenly change 19 for control signal 26,28 interference that is caused and influences.
Handover module 32 (as Fig. 3) is to be used for calculating reset signal 63,64; and when meeting default switching condition, phase frequency checkout gear 12 is switched between a normal manipulation mode (normal mode) and a sudden change protected mode (glitch protection mode).Should comprise by default switching condition a normal mode rotation protection mode condition, and the protected mode norm formula condition of becoming a full member.
This normal mode rotation protection mode condition is described as follows.See also Fig. 4 A, B and Fig. 7, the sequential chart of each coherent signal when Fig. 7 switches to the sudden change protected mode for normal manipulation mode of the present invention.The length of the leading pulse 54 that in first control signal 26, is had; reached in the process of one first switching value 67 with the count value 65 of the sum total of the length of the backward pulse 56 that is had in second control signal 28; when not having any this first reset signal 63 or this second reset signal 64 to produce, promptly meet this normal mode rotation protection mode condition.32 of handover modules can switch to this sudden change protected mode from this normal manipulation mode with phase frequency checkout gear 12.Among Fig. 7; switching point 71 left sides represent that phase frequency checkout gear 12 is in normal manipulation mode; switching point 71 right sides represent that phase frequency checkout gear 12 is in the sudden change protected mode, and N represents first switching value 67, and N-2, N-1 then reach the process of N for this count value 65.
In other words; the length of promptly working as the leading pulse 54 that is had in first control signal 26; reached in the process of this first switching value 67 with the count value 65 of the sum total of the length of the backward pulse 56 that is had in second control signal 28; or door 61 do not export any reset signal 63,64, promptly meets this normal mode rotation protection mode condition.
See also Fig. 3 and Fig. 7.When phase frequency checkout gear 12 is when being in this normal manipulation mode; and when meeting this normal mode rotation protection mode condition; handover module 32 meeting output mutation protected mode enable signals 69 are to switch to this sudden change protected mode with phase frequency checkout gear 12 from this normal manipulation mode.When sudden change 21 takes place suddenly; replacement module 30 receive sudden change protected mode enable signal 69 simultaneously with door 62 from handover module 32; and the reset signal 63,64 that comes self reset module 30; at this moment; this reset signal 63,64 can by with door 62 outputs, and replacement phase frequency checkout gear 12.In this action of resetting takes place, can force first control signal 26 and second control signal 28 of 12 outputs of phase frequency checkout gear are made zero, with the rapid elimination sudden change 21 upset phenomenons that caused, so that target clock signal 20 and reference clock signal 22 reach synchronous state rapidly.
In other words; when phase frequency checkout gear 12 is in this sudden change protected mode; no matter suddenly change 16; 17; 19; the 21st, when betiding target clock signal 20 or reference clock signal 22 or both and all taking place; because reset signal 63; 64 causes with 12 replacements of phase frequency checkout gear; therefore will be suddenlyd change 16; 17; 19; the control signal 26 of 21 influences; 28 force to make zero; thereby reduce and suddenly change 16; 17; 19; 21 for control signal 26; 28 and the influence that interference caused of this feedback control circuit 18; therefore also reduced sudden change 16; 17; 19; the influence of the target clock signal 20 of 21 pairs of feedbacks is so can make target clock signal 20 and reference clock signal 22 reach synchronous state rapidly.
This protected mode norm formula condition stub of becoming a full member is as follows.See also Fig. 8, the sequential chart of each coherent signal when Fig. 8 switches to normal manipulation mode for sudden change protected mode of the present invention.When the count value 66 of 64 sum totals that produce continuously of first reset signal 63 and second reset signal has reached one second switching value 68, promptly meet this protected mode norm formula condition of becoming a full member.32 of handover modules can switch to this normal manipulation mode from this sudden change protected mode with phase frequency checkout gear 12.Among Fig. 8; switching point 73 left sides represent that phase frequency checkout gear 12 is in the sudden change protected mode; switching point 73 right sides represent that phase frequency checkout gear 12 is in normal manipulation mode, and M represents second switching value 68, and M-5, M-4 ... M-1 then reaches the process of M for this count value 66.
When phase frequency checkout gear 12 is to be in the sudden change protected mode; and replacement module 30 is reset for several times to phase frequency checkout gear 12 continuously; but when phase frequency checkout gear 12 still can't promptly make target clock signal 20 and reference clock signal 22 synchronously; and when meeting this protected mode and becoming a full member norm formula condition; handover module 32 can stop output mutation protected mode enable signal 69; so that phase frequency checkout gear 12 is switched to this normal manipulation mode from this sudden change protected mode, so that target clock signal 20 and reference clock signal 22 reach synchronous state rapidly.
As shown in Figure 3, feedback control circuit 18 comprises one and charges and discharge electric pump 40, a voltage controlled oscillator 42 and a frequency divider 44.Charging and discharging electric pump 40 is 26,28 control signals of being exported in order to receiving phase frequency detecting device 12, and exports a control voltage 46.Voltage controlled oscillator 42 is to produce a corresponding data clock signal 48 (data clock) according to control voltage 46.Frequency divider 44 be with a predetermined divisor with data clock signal 48 frequency divisions, and produce target clock signal 20.
First counter 58 and second counter, 60 employed these counting clock signals 70 can be the data clock signal 48 that voltage controlled oscillator 42 produced or the clock signal in other sources.Among Fig. 3, a dashed line segment 77 shows that the source of counting clock signal 70 can be the data clock signal 48 that voltage controlled oscillator 42 produced or the clock signal in other sources.But the frequency of the clock signal in data clock signal 48 or other sources is to be higher than first control signal 26 and second control signal 28, so that can calculate leading pulse 54 and the length that falls behind pulse 56.
See also Fig. 9, Fig. 9 is the schematic diagram of the phase frequency checkout gear 12 of Fig. 3.Phase frequency checkout gear 12 comprises one first trigger 72 (filp flop), one second trigger 74 and one and door 75 (And gate).First trigger 72 comprises one first input port 76, one first delivery outlet 80 and one first replacement mouth 78.First trigger 72 is understood via first input port, 76 input reference clock signals 22, and from first delivery outlet, 80 outputs, first control signal 26.Second trigger 74 comprises one second input port 82, one second delivery outlet 86 and one second replacement mouth 84.Second trigger 74 can be imported target clock signals 20 via second input port 82, and from second delivery outlet, 86 outputs, second control signal 28.With 75 output results that accept first delivery outlet 80 and second delivery outlet 86 of door, and should export the result and deliver to first replacement mouthful 78 and second replacement mouth 84.
Please refer to Figure 10 A and Figure 10 B, Figure 10 A and Figure 10 B are the sequential chart that the control signal 26,28 of another embodiment of the present invention produces.Transverse axis express time in the sequential chart, the longitudinal axis is represented the amplitude of signal.Another specific embodiment of the method that produces at control signal 26,28, target clock signal 20 all comprises a plurality of square pulses 49 with reference clock signal 22, and each square pulse 49 respectively has a positive edge 50 (positive edge) and a negative edge 52 (negative edge).Be with Fig. 4 A and Fig. 4 B difference, the mode that control signal 26,28 produces among Fig. 4 A and Fig. 4 B is that the positive edge 50 with square pulse 49 is a reference index, and control signal 26,28 producing methods of present embodiment be negative edge 52 with square pulse 49 are reference index.When the negative edge 52b of leading adjacent this target clock signal 20 of the negative edge 52a of reference clock signal 22, in first control signal 26 can corresponding to both phase difference and produce a leading pulse 54 (as Figure 10 A).And when the negative edge 52a of reference clock signal 22 lags behind the negative edge 52c of adjacent target clock signal 20, in second control signal 28 also can corresponding to both phase difference and produce one and fall behind pulse 56 (as Figure 10 B).And both phase differences of reference clock signal 22 and target clock signal 20 are to be directly proportional with the width of leading pulse 54 or the width that falls behind pulse 56.Figure 10 A promptly represents the negative edge 52b of the leading adjacent target clock signal 20 of negative edge 52a of reference clock signal 22, and Figure 10 B represents that promptly the negative edge 52a of reference clock signal 22 lags behind the negative edge 52c of adjacent target clock signal 20.
See also Figure 11, Figure 11 is a control method flow chart of the present invention.Below detailed description is applied to the control method of the regulating system of the present invention 14 of Fig. 3.The inventive method comprises the following step:
S71: utilize the phase frequency checkout gear 12 in the phase-locked loop 11, will compare with predetermined reference clock signal 22 from the target clock signal 20 of these 11 feedback generation in phase-locked loop, and export first control signal 26 and second control signal 28.
S73: the length of calculating leading pulse 54 in first control signal 26 with counting clock signal 70.
S75: the length of calculating this backwardness pulse 56 in this second control signal 28 with counting clock signal 70.
S77: judge whether the length of leading pulse 54 surpasses the higher limit of leading pulse 54 length.
S79: judge whether the length that falls behind pulse 56 surpasses the higher limit that falls behind pulse 56 length.
S81: if the judged result of S77 then produces first reset signal 63 for certainly.
S83: if the judged result of S79 then produces second reset signal 64 for certainly.
S85: judge whether phase frequency checkout gear 12 is in the sudden change protected mode.
S87: if the judged result of S85 is for certainly, the phase frequency checkout gear 12 of then resetting, and the sum total count value 65 that will take the lead pulse 54 length and fall behind pulse 56 length makes zero.
S89: the number of times summation of calculating first reset signal 63 and second reset signal 64.
S91: judging whether to meet this sudden change protected mode changes this normal mode condition.
S93: if the judged result of S91 is certainly, then this handover module 32 can switch to this normal manipulation mode from this sudden change protected mode with this phase frequency checkout gear 12.And the count value 66 of first reset signal 63 and second reset signal, the 64 continuous sum totals that produce is made zero.
S95: calculate length that takes the lead pulse 54 and the summation that falls behind the length of pulse 56.
S97: judge whether to meet this normal manipulation mode transposon mutant protected mode condition.
S99: if the judged result of S97 is certainly, then handover module 32 can switch to this sudden change protected mode from this normal manipulation mode with phase frequency checkout gear 12.And the sum total count value 65 that will take the lead pulse 54 length and backward pulse 56 length makes zero.
Compare with known phase-locked loop 10, wherein owing to the influence of sudden change 16,12 of phase frequency checkout gears need the extra time of cost handle sudden change 16 influences that caused, so have also reduced the operating efficiency of phase frequency checkout gear 12.
And regulating system 14 provided by the invention; for no matter being to betide target clock signal 20 or reference clock signal 22 or both all to undergo mutation 16; 17; 19; under 21 the situation; and when phase frequency checkout gear 12 is in this sudden change protected mode; because reset signal 63; 64 causes that phase frequency checkout gear 12 can be reset; therefore will be suddenlyd change 16; 17; 19; the control signal 26 of 21 influences; 28 force to make zero; thereby reduce and suddenly change 16; 17; 19; 21 for control signal 26; 28 and the influence that interference caused of this feedback control circuit 18; therefore also reduced sudden change 16; 17; 19; the influence of the target clock signal 20 of 21 pairs of feedbacks; so can solve phase-locked loop 10; 11 are suddenlyd change 16; 17; 19; 21 disturb and have reduced the shortcoming of the operating efficiency of phase frequency checkout gear 12; and shorten and make target clock signal 20 and reference clock signal 22 deliver to the synchronous time; make target clock signal 20 and reference clock signal 22 reach synchronous state rapidly, and can promote the operating efficiency of phase-locked loop 11.
Regulating system 14 of the present invention can make phase frequency checkout gear 12 interworking between this normal manipulation mode and this sudden change protected mode according to different situations; and the phase frequency checkout gear 12 of in good time resetting is to shorten the time that target clock signal 20 and reference clock signal 22 reach synchronous state.
By the detailed description of above preferred specific embodiment, be to wish to know more to describe feature of the present invention and spirit, and be not to come category of the present invention is limited with above-mentioned disclosed preferred specific embodiment.On the contrary, its objective is that hope can contain in the category of claim of being disposed at of various changes and tool equivalence institute of the present invention desire application.
Claims (20)
1. regulating system that is used for regulating a phase frequency checkout gear, this phase frequency checkout gear is to use in a phase-locked loop, comparing from a target clock signal and a predetermined reference clock signal of this phase-locked loop institute feedback generation, and export one group of control signal, and in this target clock signal of subsequent control and synchronous with this reference clock signal, this regulating system comprises:
One replacement module is used for calculating this group control signal, and when meeting a default replacement condition, exports one group of reset signal; And
All die change pieces are used for calculating this group reset signal, and when meeting a default switching condition, this phase frequency checkout gear is suddenlyd change in a normal manipulation mode and switch between the protected mode;
Wherein, if this phase frequency checkout gear is to be under this sudden change protected mode, and when should the default replacement condition of replacement module meeting, this replacement module can be exported this group reset signal and this phase frequency checkout gear of resetting.
2. regulating system as claimed in claim 1, wherein when this reference clock signal or this target clock signal produce a sudden change for some reason, this group control signal then can corresponding generation one undesired pulse, and when this phase frequency checkout gear is reset, the undesired pulse of this group control signal is made zero, and the interference effect that is caused for this group control signal that will suddenly change reduce.
3. regulating system as claimed in claim 1, wherein this target clock signal and this reference clock signal all comprise a plurality of square pulses, and these square pulses respectively have a positive edge and a negative edge.
4. regulating system as claimed in claim 3, wherein this group control signal comprises one first control signal and one second control signal, when the positive edge of this reference clock signal takes the lead the positive edge of adjacent this target clock signal, in this first control signal can corresponding to both phase difference and produce a leading pulse, and when the positive edge of this reference clock signal lags behind the positive edge of adjacent this target clock signal, in this second control signal also can corresponding to both phase difference and produce one and fall behind pulse.
5. regulating system as claimed in claim 4, wherein the phase difference of this reference clock signal and this target clock signal is to be directly proportional with the width of this leading pulse.
6. regulating system as claimed in claim 4, wherein the phase difference of this target clock and this reference clock signal is to be directly proportional with the width of this backwardness pulse.
7. regulating system as claimed in claim 4, wherein this group reset signal comprises one first reset signal and one second reset signal, and should the replacement module comprise:
One first counter can calculate the length that should take the lead pulse in this first control signal with a counting clock signal 70, and when the length of this leading pulse takes the lead the pulse upper limit value above one, produces this first reset signal; And
One second counter can calculate the length of this backwardness pulse in this second control signal with this counting clock signal, and when this length that falls behind pulse falls behind the pulse upper limit value above one, produces this second reset signal.
8. regulating system as claimed in claim 7 wherein produces or in this second reset signal produces or both all produce, promptly meets this default replacement condition when this first reset signal.
9. regulating system as claimed in claim 7, wherein the default switching condition of this group comprises a normal mode rotation protection mode condition, and this normal mode rotation protection mode condition is as follows:
When this first counter calculates the length of the leading pulse that is had in this first control signal and sum total that this second counter calculates the length of the backward pulse that is had in this second control signal has reached in the process of one first switching value; when not having any this first reset signal or this second reset signal to produce, this handover module can switch to this sudden change protected mode from this normal manipulation mode with this phase frequency checkout gear.
10. regulating system as claimed in claim 7, wherein the default switching condition of this group comprises the protected mode norm formula condition of becoming a full member, and this protected mode norm formula condition of becoming a full member is as follows:
When this first reset signal and this second reset signal the sum total that produces continuously when having reached one second switching value, this handover module can switch to this normal manipulation mode from this sudden change protected mode with this phase frequency checkout gear.
11. regulating system as claimed in claim 7, wherein this phase-locked loop comprises a feedback control circuit in addition to produce this target clock signal, and this feedback control circuit comprises:
One charges and discharge electric pump, in order to receiving this group control signal that this phase frequency checkout gear is exported, and exports a control voltage;
One voltage controlled oscillator is to produce a corresponding data clock signal according to this control voltage;
And
One frequency divider with this data clock signal frequency division, and produces this target clock signal with a predetermined divisor.
12. regulating system as claimed in claim 11, wherein this first counter and employed this counting clock signal of this second counter are this data clock signals that produces for this voltage controlled oscillator, and the frequency of this data clock signal is to be higher than this first control signal and this second control signal, so that can calculate the length of this leading pulse and this backwardness pulse.
13. regulating system as claimed in claim 4, wherein this phase frequency checkout gear comprises:
One first trigger comprises one first input port, one first delivery outlet and one first replacement mouth, and this first trigger can be accepted this reference clock signal via this first input port, and this first delivery outlet output should take the lead pulse certainly;
One second trigger comprises one second input port, one second delivery outlet and one second replacement mouth, and this second trigger can be accepted this target clock signal via this second input port, and this second delivery outlet is exported this backwardness pulse certainly; And
One with door, accept the output result of this first delivery outlet and this second delivery outlet, and should export the result and deliver to this and first reset mouthful and this second replacement mouth.
14. method that the control signal of being exported for a phase frequency checkout gear is regulated, this phase frequency checkout gear is to use in a phase-locked loop, comparing from a target clock signal and a predetermined reference clock signal of this phase-locked loop institute feedback generation, and export one group of control signal, and in this target clock signal of subsequent control with synchronous with this reference clock signal, this control method comprises:
Calculate this group control signal, and when meeting a default replacement condition, export one group of reset signal; And
Calculate this group reset signal, and when meeting a default switching condition, this phase frequency checkout gear is suddenlyd change in a normal manipulation mode and switch between the protected mode;
Wherein, if this phase frequency checkout gear is to be under this sudden change protected mode, and when should the default replacement condition of replacement module meeting, this replacement module can be exported this group reset signal and this phase frequency checkout gear of resetting.
15. control method as claimed in claim 14, wherein this target clock signal and this reference clock signal all comprise a plurality of square pulses, and these square pulses respectively have a positive edge and a negative edge.
16. control method as claimed in claim 15, wherein this group control signal comprises one first control signal and one second control signal, when the positive edge of this reference clock signal takes the lead the positive edge of adjacent this target clock signal, in this first control signal can corresponding to both phase difference and produce a leading pulse, and when the positive edge of this reference clock signal lags behind the positive edge of adjacent this target clock signal, in this second control signal also can corresponding to both phase difference and produce one and fall behind pulse.
17. control method as claimed in claim 16, wherein this group reset signal comprises one first reset signal and one second reset signal, and this control method comprises in addition:
Calculate the length that should take the lead pulse in this first control signal with a counting clock signal 70, and when the length of this leading pulse takes the lead the pulse upper limit value above one, produce this first reset signal; And
Calculate the length of this backwardness pulse in this second control signal with this counting clock signal, and when this length that falls behind pulse falls behind the pulse upper limit value above one, produce this second reset signal.
18. control method as claimed in claim 17 wherein produces or in this second reset signal produces or both all produce, promptly meets this default replacement condition when this first reset signal.
19. control method as claimed in claim 17, wherein the default switching condition of this group comprises a normal mode rotation protection mode condition, and this normal mode rotation protection mode condition is as follows:
When this first counter calculates the length of the leading pulse that is had in this first control signal and sum total that this second counter calculates the length of the backward pulse that is had in this second control signal has reached in the process of one first switching value; when not having any this first reset signal or this second reset signal to produce, this handover module can switch to this sudden change protected mode from this normal manipulation mode with this phase frequency checkout gear.
20. control method as claimed in claim 17, wherein the default switching condition of this group comprises the protected mode norm formula condition of becoming a full member, and this protected mode norm formula condition of becoming a full member is as follows:
When this first reset signal and this second reset signal the sum total that produces continuously when having reached one second switching value, this handover module can switch to this normal manipulation mode from this sudden change protected mode with this phase frequency checkout gear.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03102990 CN1272908C (en) | 2003-01-24 | 2003-01-24 | Phase frequency detection device and method for reducing influence of mutation interference |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03102990 CN1272908C (en) | 2003-01-24 | 2003-01-24 | Phase frequency detection device and method for reducing influence of mutation interference |
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| Publication Number | Publication Date |
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| CN1520039A true CN1520039A (en) | 2004-08-11 |
| CN1272908C CN1272908C (en) | 2006-08-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 03102990 Expired - Fee Related CN1272908C (en) | 2003-01-24 | 2003-01-24 | Phase frequency detection device and method for reducing influence of mutation interference |
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| Country | Link |
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| CN (1) | CN1272908C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101534135B (en) * | 2008-03-12 | 2013-06-26 | 华为技术有限公司 | Method for solving interference frequency, equipment and system thereof |
| CN103308763A (en) * | 2012-03-16 | 2013-09-18 | 国民技术股份有限公司 | Clock frequency detection device and method |
| CN109584773A (en) * | 2018-12-24 | 2019-04-05 | 惠科股份有限公司 | Time sequence control method, time sequence control chip and display device |
-
2003
- 2003-01-24 CN CN 03102990 patent/CN1272908C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101534135B (en) * | 2008-03-12 | 2013-06-26 | 华为技术有限公司 | Method for solving interference frequency, equipment and system thereof |
| CN103308763A (en) * | 2012-03-16 | 2013-09-18 | 国民技术股份有限公司 | Clock frequency detection device and method |
| CN103308763B (en) * | 2012-03-16 | 2016-02-03 | 国民技术股份有限公司 | A kind of clock frequency detection device and method |
| CN109584773A (en) * | 2018-12-24 | 2019-04-05 | 惠科股份有限公司 | Time sequence control method, time sequence control chip and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1272908C (en) | 2006-08-30 |
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