CN1516287A - Tunneling biasing metal oxide semiconductor transistor - Google Patents
Tunneling biasing metal oxide semiconductor transistor Download PDFInfo
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- CN1516287A CN1516287A CNA031009786A CN03100978A CN1516287A CN 1516287 A CN1516287 A CN 1516287A CN A031009786 A CNA031009786 A CN A031009786A CN 03100978 A CN03100978 A CN 03100978A CN 1516287 A CN1516287 A CN 1516287A
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Abstract
The invention relates to a tunnel bias metal oxide semiconductor (TBMOS) tube, able to be applied to traditional bulk substrate or the substrate with silicon covered on partial destitute insulating layer (PD SOI), and used to form tunnel connection between the grid and the substrate. The grid seat is slightly longer than the general one and two ends of the grid seat have reverse ion embedded regions, which admits cavities in N-type MOS transistor and electrons in P-type MOS transistor to tunnel through the grid into the substrate. In addition, it can avoid the crosstalk between the N- and P- MOS transistors.
Description
Technical field
The present invention relates to metal oxide semiconductor transistor (Metal-Oxide-SemiconductorTransistor; MOS) component structure and manufacture method thereof, specially referring to operating voltage can be greater than 0.7 volt metal-oxide semiconductor transistor component structure and manufacture method thereof.
Background technology
In recent years, portable communications product and electronic product, for example mobile phone and laptop computer etc. are popular fast, make that the transmission of information is more quick, so people increase considerably for the demand of this series products.In order more to increase the convenience of portable communications product and electronic product, how to prolong its battery and just become consideration emphasis on the circuit design service time.Because the development of semiconductor industry is rapid, the operating frequency of integrated circuit and operational capability fast rise, the capacity of storage device and hard disk sharply increases, thereby makes the ability of portable communications product and electronic product strengthen day by day, also causes the power consumption of system increasing.But the reserve of electricity of battery can not be caught up with the improvement speed of semiconductor technology now, and makes portable communications product and electronic product be subject on the electric power storage ability of battery.In addition,, also cause internal system to heat up easily and make the operating environment instability, especially get over hour easy more generation in the size of portable communications product and electronic product if the power consumption of portable communications product and electronic product is excessive.
From the above, the size of battery, weight and service time have limited the speed development of Circuits System and internal storing memory faster, therefore wishing under the lighter and thinner situation that portable communications product and electronic product will be done, must develop to the direction of design low power consumption circuit.For the technological development of follow-on deep-submicron CMOS (Complementary Metal Oxide Semiconductor) very lagre scale integrated circuit (VLSIC) (Sub-1 μ m CMOS VLSI), make circuit reach the target that low operating voltage and low power consumption develop just.Wherein, use low operating voltage can reach element stability and littler consumed power preferably.Utilize silicon-on-insulator (Silicon-On-Insulator; Be called for short SOI) circuit of technology made have that speed is fast, power consumption is low, component density is high, quadratic effect (Second-Order Effect) is little, capability of resistance to radiation strong and can with advantage such as existing integrated circuit technique compatibility, so silicon-on-insulator technology generally is the preferably selection that is used to reach the demand.
In metal-oxide-semiconductor element now, the top layer silicon monocrystalline of the hundreds of nanometer of only having an appointment basically (nm) is used to make the transmission that element service area (Active Layer) is used as electronics; The then conduct support mechanically of bottom silicon wafer beyond the element layer.Such structure causes the ghost effect (Parasitic Effect) of element and base material to produce easily, and is in addition, very difficult as dielectric insulation (Dielectric Insulator) with the silicon substrate with characteristic of semiconductor.So the conception of silicon-on-insulator technology just is suggested, will have the film that is electrically insulated and place under the surperficial thin silicon single-crystal element layer, and resolution element layer and silicon substrate, as shown in Figure 1.Fig. 1 is the generalized section of silicon-on-insulator base material, please refer to Fig. 1, and wherein, the silicon-on-insulator matrix structure is exactly on silicon substrate 10 originally, forms insulating barrier 12.Then, will build crystal silicon (Epitaxial Si) 14 and place on the insulating barrier 12, so just form the silicon-on-insulator matrix structure.
In addition, according to the difference in thickness of the crystal silicon of heap of stone 14 on the insulating barrier 12, can be divided into partially depleted (Partially Depleted again; PD) silicon-on-insulator and vague and general fully (Fully Depleted; Be called for short FD) silicon-on-insulator, as Fig. 2 and shown in Figure 3.Please refer to Fig. 2, Fig. 2 is the sectional structure chart of partially depleted silicon-on-insulator.Wherein, base material is by silicon substrate 30, insulating barrier 32, is formed with crystal silicon 36 of heap of stone, and is manufactured with the element service area on crystal silicon 36 of heap of stone, and this element service area comprises grid (Gate) 40, source electrode (Source) 42, and (Drain) 44 that drain.And partially depleted silicon-on-insulator is exactly the thickness of the degree of depth of the exhaustion region 38 in the finger element less than crystal silicon 36 of heap of stone.In addition, please refer to Fig. 3, Fig. 3 is the sectional structure chart of complete vague and general silicon-on-insulator.Wherein, have insulating barrier 62 on the silicon substrate 60, and have grid 64, source electrode 66, with the element service area of drain electrode 68, wherein the element service area is to utilize crystal silicon of heap of stone to make.Because the thickness of crystal silicon of heap of stone just in time is the exhaustion region degree of depth of element in the complete vague and general silicon-on-insulator, thus the crystal silicon of not drawing among Fig. 3 of heap of stone just with the location overlap of element service area.And cover in the silicon on the above-mentioned different insulative layer, partially depleted element with silicon-coated insulating layer can be with less voltage-operated and than traditional silicon wafer lower power loss is arranged, and can easily this partially depleted silicon-on-insulator technology be transferred to existing silicon wafer technology fully, and the circuit design of quoting complete vague and general silicon-on-insulator must be passed through appropriate correction, but it can effectively resist the soft error effect, and be easy to make shallow junction, compare with partially depleted element with silicon-coated insulating layer and better electrical performance arranged.Therefore, the producer can be selected according to its needs respectively.
Summary of the invention
In order to adapt to the circuit developing direction of low operating voltage and low power consumption, one of the object of the invention provides a kind of transistor unit, can be adapted at operating under low-voltage and the lower powered situation.And another object of the present invention also makes above-mentioned transistor unit, can use under room temperature and the operating environment greater than 0.7 volt of operating voltage, and can avoid the excessive shortcoming that meets face leakage current (Junction Leakage).In addition, the present invention also provides the manufacture method of above-mentioned transistor unit.
According to above-described purpose, the invention provides a kind of tunnel bias voltage metal oxide semiconductor transistor (TBMOS) of wearing, this transistor arrangement can be N transistor npn npn or P transistor npn npn structure, the invention is not restricted to this.Wherein, wearing tunnel bias voltage metal oxide semiconductor transistor with the N type is example, and structure of the present invention comprises: a P type main body, and this P type main body has an end face; One first insulating regions is extended downwards by end face, thereby isolates a volume in P type main body, so as to forming a P well construction; Grid holder with relative two long limits, an end of this grid holder extend across the P well construction and arrive the other end of grid holder; One dielectric layer is positioned between grid holder and end face; One N type zone is arranged in the P well construction, and N type zone is adjacent to the long limit of grid holder, and this N type zone has one source pole and with respect to a drain electrode of source electrode, and source electrode and drain electrode are positioned at the relative both sides on the long limit of grid holder; And one the p type island region territory be positioned at a side in N type zone, and surround the other end of grid holder, this p type island region territory forms one and wears tunnel (Tunneling) and be connected between P well construction and grid holder.
The N type is worn tunnel bias voltage metal oxide semiconductor transistor among the present invention, can be applicable in partially depleted silicon-on-insulator (PD SOI) base material or body (Bulk) base material.If wherein be applied to partially depleted silicon-on-insulator base material, then said structure comprises that also one second insulating regions is arranged in P type main body and has a distance with end face, this second insulating regions is formed under first insulating regions and with first insulating regions and is connected, and the P well construction is positioned on second insulating regions.If be applied in the body base material, then said structure comprises that also a unsteady N moldeed depth well construction is arranged in P type main body, this unsteady N moldeed depth well construction is formed in this volume that first insulating regions isolates, and links with first insulating regions, and is positioned under the P well construction.Above-mentioned dielectric layer can be selected from by silica, silicon nitride, high-k material or other and can be used as the group that material constituted of gate dielectric, and the first above-mentioned insulating regions is made of at least one irrigation canals and ditches that fill up an oxide layer, and second insulating regions is to imbed oxide layer (Buried Oxide Layer).In addition, the thickness of above-mentioned dielectric layer is between 100 to 5 , the thickness of grid holder is between 20000 to 10 , the width of grid holder is between 10000 microns to 0.005 micron, the length of grid holder is between 1000 microns to 0.005 micron, and first above-mentioned insulating regions and end face distance apart are between 10000 to 100 .And above-mentioned p type island region territory has several acceptor ions (Accepter Ions), and the concentration of acceptor ions is between every square centimeter 10
19Individual ion is to every square centimeter 10
20Between the individual ion.
Utilizing the present invention to wear tunnel bias voltage metal oxide semiconductor transistor can use when 0.7 volt in the big hand of power supply supply voltage, except can reducing the body contact area, also have good current driving capability (Current Drive) and less subcritical fluctuation (Sub-threshold Swing).
Brief Description Of Drawings
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in further detail.
In the accompanying drawing,
Fig. 1 is the generalized section of silicon-on-insulator base material;
Fig. 2 is the sectional structure chart of partially depleted silicon-on-insulator;
Fig. 3 is the sectional structure chart of complete vague and general silicon-on-insulator;
Fig. 4 wears the layout top view of tunnel bias voltage metal oxide semiconductor transistor for N type of the present invention;
Fig. 5 wears the equivalent circuit diagram that tunnel bias voltage metal oxide semiconductor transistor is applied in partially depleted silicon-on-insulator base material for N type among Fig. 4 of the present invention;
Fig. 6 wears for N type among Fig. 4 of the present invention that tunnel bias voltage metal oxide semiconductor transistor is applied in partially depleted silicon-on-insulator base material and along the sectional structure chart of A-A ' hatching;
Fig. 7 wears the layout top view of tunnel bias voltage metal oxide semiconductor transistor for P type of the present invention;
Fig. 8 wears for P type among Fig. 7 of the present invention that tunnel bias voltage metal oxide semiconductor transistor is applied in partially depleted silicon-on-insulator base material and along the sectional structure chart of B-B ' hatching;
Fig. 9 wears another layout top view of tunnel bias voltage metal oxide semiconductor transistor for N type of the present invention;
Figure 10 wears another layout top view of tunnel bias voltage metal oxide semiconductor transistor for P type of the present invention;
Figure 11 is applied to the data comparison diagram of wearing tunnel bias voltage metal oxide semiconductor transistor of partially depleted silicon-on-insulator base material for common dynamic critical voltage mos field effect transistor and the present invention; And
Figure 12 for according to the present invention among Fig. 4 the N type wear that tunnel bias voltage metal oxide semiconductor transistor is applied to the body base material and along the sectional structure chart of A-A ' hatching.
Embodiment
Please refer to Fig. 4 and Fig. 5, Fig. 4 is the layout top view that N type of the present invention is worn tunnel bias voltage metal oxide semiconductor transistor, and Fig. 5 wears the equivalent circuit diagram that tunnel bias voltage metal oxide semiconductor transistor is applied in partially depleted silicon-on-insulator base material for N type among Fig. 4 of the present invention.Please refer to Fig. 4, on P type base material 120, have a grid holder 128, and grid holder 128 lays respectively at N
+Ion implantation region and adjacent P
+In the ion implantation region, and N
+Relative to each other source electrode is positioned at the both sides up and down of grid holder 128 with drain electrode in the ion implantation region.Wherein, surround the P of grid holder 128 1 ends
+Ion implantation region can be worn tunnel (Tunneling) in 128 formation one of P type base material 120 and grid holder and be connected.And Fig. 7 wears the layout top view of tunnel bias voltage metal oxide semiconductor transistor for P type of the present invention.Please refer to Fig. 7, wherein except with N
+Ion implantation region and P
+The position of ion implantation region it seems from top view outside exchanging that P type and N type are worn layout and the no significant difference between the tunnel bias voltage metal oxide semiconductor transistor, and the present invention does not give unnecessary details at this.
Below disclose manufacture method of the present invention, illustrate that simultaneously the present invention wears the cross-section structure of tunnel bias voltage metal oxide semiconductor transistor.Fig. 6 and Fig. 8 are applied to sectional structure chart in the partially depleted silicon-on-insulator base material for the present invention.Please refer to Fig. 6, Fig. 6 wears for N type among Fig. 4 of the present invention that tunnel bias voltage metal oxide semiconductor transistor is applied in partially depleted silicon-on-insulator base material and along the sectional structure chart of A-A ' hatching.In this preferred embodiment of the present invention, partly vague and general, 0.1 micron the complementary metal oxide semiconductor and the technology of silicon-on-insulator have been utilized.Base material uses has 8 o'clock wafers that about 1500 of thickness imbed oxide layer, and partially depleted crystal silicon of heap of stone is made on the thick silicon fiml of about 1900 of thickness.In addition, also utilize shallow trench isolation, and after utilizing thermal oxidation method to grow up to grid oxic horizon, the deposit spathic silicon grid holder is on oxide layer again as the electrical isolation structure between transistor.Size and manufacture method that it should be noted that said structure only are for example, are not to be used for limiting the scope of the invention, and other can reach the structure and the manufacture method of same effect, all can be used among the present invention, the invention is not restricted to this.
At first, provide the P type base material 120 with an insulating barrier 122, wherein, the surface of this insulating barrier 122 and P type base material 120 is at a distance of a distance 124.This insulating barrier 122 can be imbeds oxide layer structure (BuriedOxide; BOX), generally can adopt silicon dioxide (SiO
2) come as constituent material, mainly be to consider that the silicon dioxide via the growth of silicon heat has the good insulation characteristic, and with the process integration height of Silicon Wafer, but the invention is not restricted to this.Then, in P type base material 120, form another insulating regions 130.Wherein, this insulating regions 130 can be made of the irrigation canals and ditches structure of filling up oxide layer, extends downward insulating barrier 122 by the surface of P type base material 120, and isolates a volume, so as to forming a P well construction.Follow again, form dielectric layer 126 on the surface of P type base material 120.In a preferred embodiment of the present invention, the thickness of dielectric layer 126 is between 100 to 5 , and the material of this dielectric layer 126 can be made of for example institutes such as silica, silicon nitride or other high-k material, the invention is not restricted to this.
Then, form a grid holder 128 again on dielectric layer 126, this grid holder 128 is oblique line part as shown in Figure 4.In a preferred embodiment of the present invention, the thickness of grid holder 128 is between 20000 to 10 , and width is between 10000 microns to 0.005 micron, and length is between 1000 microns to 0.005 micron.Grid holder 128 of the present invention is an elongate structure, and the one end span is crossed the P well construction and extended to the other end.Then, remove not by behind the dielectric layer of 128 cover parts of grid holder.Carry out an ion implantation step, with Donor Ion, i.e. N
+Ion is implanted in the zone.This N
+Ion implantation region is overlapping with the grid holder 128 of part, and in the both sides of grid holder 128, the long leg that is elongate structure divides source electrode and the drain electrode that forms relative to each other.Then, carry out another ion implantation step, with acceptor ions, i.e. P
+Ion is implanted in and is positioned at N
+In another zone on ion implantation region side.In a preferred embodiment of the present invention, wherein above-mentioned P
+Ion and, N
+The implant concentration of ion is between every square centimeter 10 approximately
19Individual ion is to every square centimeter 10 approximately
20Between the individual ion.P of the present invention
+In ion implantation region and the grid holder 128, not by N
+The end that ion implantation region comprised is overlapping, therefore at P
+Ion implantation region territory, P well construction and 128 of the part of grid pole seats of part can form one and wear tunnel and be connected.Wherein, I
N+Representative is at the N of polysilicon layer
+The tunnel electric current is worn in oxidation in the ion implantation region territory, and I
P+Representative is at the P of polysilicon layer
+The tunnel electric current is worn in oxidation in the ion implantation region.
Above-mentionedly illustrated that the present invention is applied to the N type structure of wearing tunnel bias voltage metal oxide semiconductor transistor of partially depleted silicon-on-insulator base material, and Fig. 8 wears for P type among Fig. 7 of the present invention that tunnel bias voltage metal oxide semiconductor transistor is applied in partially depleted silicon-on-insulator base material and along the sectional structure chart of B-B ' hatching.Please refer to Fig. 8, except P type base material is replaced into N type base material, and form the N well area therein, and N
+Ion implantation region and P
+Outside the position of ion implantation region was exchanged, all to wear tunnel bias voltage metal oxide semiconductor transistor identical with the N type for other element, so the present invention does not give unnecessary details at this.
It should be noted that, tunnel bias voltage metal oxide semiconductor transistor worn by the invention described above N type or the P type is worn in the tunnel bias voltage metal oxide semiconductor transistor, the shape of grid holder is only for for example, visual product and arts demand and change the invention is not restricted to this.In addition, no matter the N type is worn tunnel bias voltage metal oxide semiconductor transistor or the P type is worn tunnel bias voltage metal oxide semiconductor transistor, wherein N
+Ion implantation region and P
+Ion implantation region is except overseas as can be separate and nonoverlapping two antiphase regions among Fig. 4 and Fig. 7, also can be as shown in Fig. 9 and Figure 10, and overlapped, the invention is not restricted to this.
Layout characteristics of wearing tunnel bias voltage metal oxide semiconductor transistor of the present invention is gate dielectric and P on the extension of grid holder and the P well construction
+The increase in ion implantation region territory and existence are worn the tunnel connection thereby can provide.Utilize the present invention to wear the characteristics of tunnel bias voltage metal oxide semiconductor transistor, being applied in the N type wears can provide in the tunnel bias voltage metal oxide semiconductor transistor and wears tunnel hole (Holes), so as to when element is initial state, improve buoyancy aid current potential (Floating Body Potential).Similarly, be applied in the P type and wear to provide in the tunnel bias voltage metal oxide semiconductor transistor and wear tunnel electronics (Electrons),, reduce the buoyancy aid current potential so as to when element is initial state.In addition, the unnecessary carrier in the buoyancy aid (Excess Carriers) can reduce critical voltage (Threshold Voltage) to obtain higher current drives (Current Drive).
After testing, find, utilize the present invention to wear tunnel bias voltage metal oxide semiconductor transistor and can significantly improve saturated drain current (I
D, sat), and keep better drain leakage (I
Off).In addition, as grid voltage (V
G) equal diode cut-ff voltage (V
Dd) time can reduce and connects the face leakage current, and when element was initial state (Turn-OnState), the buoyancy aid current potential can remain on below the 0.7V.Figure 11 is common dynamic critical voltage mos field effect transistor (Dynamic Threshold Voltage MOSFET; DTMOS) be applied to the data comparison diagram of wearing tunnel bias voltage metal oxide semiconductor transistor of partially depleted silicon-on-insulator base material with the present invention.Please refer to Figure 11, wherein curve X represents existing transistorized source/drain current (Source-to-Drain Current) and grid voltage (Gate Voltage) relation, and curve Y represents transistorized source/drain current of the present invention and grid voltage relation.Can learn according to curve X and curve Y, generally be applied to the dynamic critical voltage mos field effect transistor in the partially depleted silicon-on-insulator technology, when operating voltage is too big, might make the element internal body that source electrode (Body-Source) or body are produced great leakage current to the knot of the P-N between drain electrode (Body-Drain) (P-N Junction) because of forward bias conducting (Forward Bias), use less than the situation under the 0.7V thereby only be confined to operating voltage.And the present invention wears the diode cut-ff voltage (V that tunnel bias voltage metal oxide semiconductor transistor can use in power supply supply
Dd) during greater than 0.7V, scope is extensively more many than dynamic critical voltage mos field effect transistor, also need not make unnecessary body contact area (BodyContact Region).Add the present invention and wear tunnel bias voltage metal oxide semiconductor transistor and have good current driving capability and less advantages such as subcritical fluctuation, the tunnel bias voltage metal oxide semiconductor transistor of wearing of the present invention is the good element that is applied in the partially depleted silicon-on-insulator technology really.
The layout that N type of the present invention or P type are worn tunnel bias voltage metal oxide semiconductor transistor also can be applicable on body (Bulk) base material, as shown in figure 12 except can be applicable to partially depleted silicon-on-insulator base material.Figure 12 for according to the present invention among Fig. 4 the N type wear that tunnel bias voltage metal oxide semiconductor transistor is applied to the body base material and along the sectional structure chart of A-A ' hatching, the present invention utilizes manufacturing process that transistorized structure is described simultaneously.Please refer to Figure 12, at first, provide P type base material 162, and array structure under in P type base material 162, forming: several insulating regions 164, be positioned at (Floating) N moldeed depth well (Deep-Well) structure 166 and be positioned at the shallow well (Shallow Retrograde P-Well) 168 of stepping back of P type on the N moldeed depth well construction 166 that floats of floating of 164 of above-mentioned insulating regions.Wherein, above-mentioned insulating regions 164 can be shallow slot isolation structure, and the unsteady N moldeed depth well construction 166 that is positioned at 164 of insulating regions does not link to each other mutually, with insulating regions 164 as isolation.Then, form dielectric layer 170 on the surface of P type base material 162, and form grid holder 172 on dielectric layer 170, this grid holder is as shown in Figure 4 oblique line part also, is distributed in N
+Ion implantation region and P
+In the ion implantation region.In addition, because P type structure there is no too big difference except that electrically exchanging, the present invention repeats no more.
In the existing metal oxide semiconductor transistor that utilizes the body base material, general deep-well structure is positioned at the shallow slot isolation structure below, and step back well construction ability between shallow trench, therefore cause crosstalk phenomenon easily between P transistor npn npn of being manufactured on the same base material and the N transistor npn npn.And utilize the structure of the invention described above, thereby, transistor can avoid crosstalking the structure except having separately unsteady deep-well structure, also can reduce existing need and make the surperficial channel of deep-well structure or the step of surperficial contact point in addition, therefore have the advantage of simplifying element.In addition, what the invention described above was applied to the body base material wears tunnel bias voltage metal oxide semiconductor transistor, be applied to the silicon-on-insulator base material and also have same advantage, just can be applicable to operating voltage greater than 0.7 volt situation, and have good current driving capability and less subcritical fluctuation.
Understand as the person skilled in the art, the above only is preferred embodiment of the present invention, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed design and changes or modification, all should be included in the claim of the present invention.
Claims (10)
1. a N type is worn tunnel bias voltage metal oxide semiconductor transistor, it is characterized in that, comprises at least:
One P type main body, wherein this P type main body has an end face;
One first insulating regions is arranged in this P type main body and is extended downwards by this end face, thereby isolates a volume in this P type main body, so as to forming a P well construction;
Grid holder with relative two long limits, wherein an end of this grid holder extends across this P well construction and arrives the other end of this grid holder;
One dielectric layer is positioned between this grid holder and this end face;
One N type zone is arranged in this P well construction, and this N type zone is adjacent to these long limits of this grid holder, wherein this N type zone has one source pole and with respect to a drain electrode of this source electrode, and this source electrode and this drain electrode are positioned at the relative both sides on these long limits of this grid holder; And
One p type island region territory is positioned at a side in this N type zone, and surrounds this other end of this grid holder, and wherein this p type island region territory forms one and wears tunnel and be connected between this P well construction and this grid holder.
2. N type according to claim 1 is worn tunnel bias voltage metal oxide semiconductor transistor, it is characterized in that, above-mentioned P type main body is made of the vague and general silicon-on-insulator base material of a part, and this N type is worn tunnel bias voltage metal oxide semiconductor transistor, also having one second insulating regions is arranged in this P type main body and has a distance with this end face, wherein this second insulating regions is positioned under this first insulating regions and with this first insulating regions and is connected, and this P well construction is positioned on this second insulating regions.
3. N type according to claim 1 is worn tunnel bias voltage metal oxide semiconductor transistor, it is characterized in that, above-mentioned P type main body is made of a body base material, and this N type is worn tunnel bias voltage metal oxide semiconductor transistor, also have a unsteady N moldeed depth well construction and be arranged in this P type main body, the N moldeed depth well construction that wherein should float is arranged in this volume that this first insulating regions is isolated, and links with this first insulating regions, and is positioned under this P well construction.
4. N type according to claim 1 is worn tunnel bias voltage metal oxide semiconductor transistor, it is characterized in that, above-mentioned p type island region territory has several acceptor ions, and the concentration of these acceptor ions is between every square centimeter 10
19Individual ion is to every square centimeter 10
20Between the individual ion.
5. a P type is worn tunnel bias voltage metal oxide semiconductor transistor, it is characterized in that, comprises at least:
One N type main body, wherein this N type main body has an end face;
One first insulating regions is arranged in this N type main body and is extended downwards by this end face, thereby isolates a volume in this N type main body, so as to forming a N well construction;
Grid holder with relative two long limits, wherein an end of this grid holder extends across this N well construction and arrives the other end of this grid holder;
One dielectric layer is positioned between this grid holder and this end face;
One p type island region territory is arranged in this N well construction, and this p type island region territory is adjacent to these long limits of this grid holder, wherein this p type island region territory has one source pole and with respect to a drain electrode of this source electrode, and this source electrode and this drain electrode are positioned at the relative both sides on these long limits of this grid holder; And
One N type zone is positioned at a side in this p type island region territory, and surrounds this other end of this grid holder, and wherein this N type zone forms one and wears tunnel and be connected between this N well construction and this grid holder.
6. P type according to claim 5 is worn tunnel bias voltage metal oxide semiconductor transistor, it is characterized in that, above-mentioned N type main body is made of a silicon-on-insulator base material, and this P type is worn tunnel bias voltage metal oxide semiconductor transistor, also having one second insulating regions is arranged in this N type main body and has a distance with this end face, wherein this second insulating regions is positioned under this first insulating regions and with this first insulating regions and is connected, and this N well construction is positioned on this second insulating regions.
7. P type according to claim 5 is worn tunnel bias voltage metal oxide semiconductor transistor, it is characterized in that, above-mentioned N type main body is made of a body base material, and this P type is worn tunnel bias voltage metal oxide semiconductor transistor, also have a unsteady P moldeed depth well construction and be arranged in this N type main body, the P moldeed depth well construction that wherein should float is arranged in this volume that this first insulating regions is isolated, and links with this first insulating regions, and is positioned under this N well construction.
8. P type according to claim 5 is worn tunnel bias voltage metal oxide semiconductor transistor, it is characterized in that, above-mentioned N type zone has several Donor Ions, and the concentration of these Donor Ions is between every square centimeter 10
19Individual ion is to every square centimeter 10
20Between the individual ion.
9. the manufacture method that the N type is worn tunnel bias voltage metal oxide semiconductor transistor is characterized in that, comprises at least:
One P type base material is provided, and wherein this P type base material has an end face;
Form one first insulating regions, and this first insulating regions is downward by this end face, thereby in this P type base material, isolates a volume, so as to forming a P well construction;
Form a dielectric layer on this end face;
Form a grid holder on this dielectric layer, wherein this grid holder has relative two long limits, and these ends of growing limits extend across this P well construction and arrive the other end that these grow limits;
Remove not by this dielectric layer of this grid holder institute cover part;
Implant several Donor Ions in a first area, and the long limit of this first area and these is overlapping, and so as to forming one source pole and with respect to a drain electrode of this source electrode, and this source electrode and this drain electrode be positioned at this grid holder these grow the relative both sides on limits; And
Implant several acceptor ions in a second area, and an end of this second area and this grid holder is overlapping, forms one between this grid holder and wear tunnel and be connected so as to this P well construction of the part in this second area and part.
10. the manufacture method that the P type is worn tunnel bias voltage metal oxide semiconductor transistor is characterized in that, comprises at least:
One N type base material is provided, and wherein this N type base material has an end face;
Form one first insulating regions, and this first insulating regions extends downwards by this end face, thereby in this N type base material, isolate a volume, so as to forming a N well construction;
Form a dielectric layer on this end face;
Form a grid holder on this dielectric layer, wherein this grid holder has relative two long limits, and these ends of growing limits extend across this N well construction and arrive the other end that these grow limits;
Remove not by this dielectric layer of this grid holder institute cover part;
Implant several acceptor ions in a first area, and the long limit of this first area and these is overlapping, and so as to forming one source pole and with respect to a drain electrode of this source electrode, and this source electrode and this drain electrode be positioned at this grid holder these grow the relative both sides on limits; And
Implant several Donor Ions in a second area, and an end of this second area and this grid holder is overlapping, forms one between this grid holder and wear tunnel and be connected so as to this N well construction of the part in this second area and part.
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|---|---|---|---|
| CNB031009786A CN1310337C (en) | 2003-01-08 | 2003-01-08 | Tunneling biasing metal oxide semiconductor transistor |
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|---|---|---|---|
| CNB031009786A CN1310337C (en) | 2003-01-08 | 2003-01-08 | Tunneling biasing metal oxide semiconductor transistor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013086693A1 (en) * | 2011-12-14 | 2013-06-20 | Qualcomm Incorporated | Gate rounding for reduced transistor leakage current |
| WO2013155740A1 (en) * | 2012-04-19 | 2013-10-24 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method therefor |
| CN105845734A (en) * | 2016-04-15 | 2016-08-10 | 中国科学院上海微系统与信息技术研究所 | P-type dynamic threshold transistor, preparation method and method for increasing operating voltage |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2217264Y (en) * | 1994-06-24 | 1996-01-10 | 电子科技大学 | High speed tunnel insulated gate bipolar transistor |
| KR100243297B1 (en) * | 1997-07-28 | 2000-02-01 | 윤종용 | Poly silicon tft-lcd and method for producing the same |
| US6037223A (en) * | 1998-10-23 | 2000-03-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stack gate flash memory cell featuring symmetric self aligned contact structures |
| JP2001118942A (en) * | 1999-10-21 | 2001-04-27 | Matsushita Electronics Industry Corp | Tunnel channel transistor and method of driving the same |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013086693A1 (en) * | 2011-12-14 | 2013-06-20 | Qualcomm Incorporated | Gate rounding for reduced transistor leakage current |
| US9153659B2 (en) | 2011-12-14 | 2015-10-06 | Qualcomm Incorporated | Gate rounding for reduced transistor leakage current |
| WO2013155740A1 (en) * | 2012-04-19 | 2013-10-24 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method therefor |
| CN103378129A (en) * | 2012-04-19 | 2013-10-30 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN103378129B (en) * | 2012-04-19 | 2016-03-23 | 中国科学院微电子研究所 | A kind of semiconductor structure and manufacture method thereof |
| US9373722B2 (en) | 2012-04-19 | 2016-06-21 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor structure and method for manufacturing the same |
| CN105845734A (en) * | 2016-04-15 | 2016-08-10 | 中国科学院上海微系统与信息技术研究所 | P-type dynamic threshold transistor, preparation method and method for increasing operating voltage |
| CN105845734B (en) * | 2016-04-15 | 2019-09-13 | 中国科学院上海微系统与信息技术研究所 | P-type dynamic threshold transistor, preparation method and the method for improving operating voltage |
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| CN1310337C (en) | 2007-04-11 |
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