CN1514356A - Address storage method for supporting precision abnormal model of CPU medium and low expense - Google Patents
Address storage method for supporting precision abnormal model of CPU medium and low expense Download PDFInfo
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- CN1514356A CN1514356A CNA031161375A CN03116137A CN1514356A CN 1514356 A CN1514356 A CN 1514356A CN A031161375 A CNA031161375 A CN A031161375A CN 03116137 A CN03116137 A CN 03116137A CN 1514356 A CN1514356 A CN 1514356A
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Abstract
The feature of this method is as follows: only next command addrss is kept when comamnd is transmitted, its address and next command address can be provided to CPU abnormal processing unit when any one of commands is retired at any condition through guarantee from some other logic circuits so accurate and abnormal model can be realized.
Description
Technical field
The present invention relates to the address storage means of the precise abnormal model of support of low expense among a kind of CPU.
Background technology
Abnormality processing (comprising instruction exception and external interrupt) is an important technology of processor, when some anomalous events produces, is used for making processor to change processing to these incidents over to.These incidents comprise hard error, instruction execution error and user request service or the like.Exception handling ability is an important technology index of processor, and it directly affects the reliability of processor design proposal and the operational performance of instruction.Modern CPU requires response abnormality in time, and reduces the expense of abnormality processing.The key of abnormality processing is exactly when unusual the generation, preserves the state of the current operating instruction of CPU, the state when withdrawing from abnormality processing before the recovery abnormality processing.
Modern CPU handles the precise abnormal model of unusual general use.The feature of precise abnormal model is meant that abnormality processing will guarantee the atomic operation that instructs, and does not change original instruction stream.In order to accomplish this point, processed on the border of instruction unusually, i.e. CPU response when the instruction retirement is interrupted, and preserves the address of the instruction that next bar is performed when withdrawing from abnormality processing.For abnormality processing does not influence the performance of CPU, the instruction before CPU will avoid repeating after abnormality processing finishes.The address of interrupted instruction when the address that unusual service is returned may be response abnormality also may be the address of its next bar instruction.Thereby before the instruction retirement, these two addresses all need to provide, and which address Exception Type and the decision of interrupted instruction type are stored in the abnormal address register.For example, if anomalous event is the external interrupt services request, interrupted instruction will normal retirement and is changed the state of CPU, and the address of its next bar instruction will be stored in the abnormal address register inlet of instruction when interrupting returning; If anomalous event is to be produced by the divide instruction of division by 0, because this instruction can not be finished, it is will be unusual retired but do not change the state (promptly not changing the value of register) of CPU, the address of this divide instruction will be stored in the abnormal address register, and CPU continues to carry out this divide instruction when interrupt service routine returns.
Unusual generation is unpredictable, and each bar instruction all may produce.Generally in order to realize precise abnormal model, CPU need preserve these two addresses.Along with increasing of firing order in the CPU streamline, the physical overhead of storing these two addresses simultaneously can increase, and has also increased power consumption.
Summary of the invention
The address storage means that the purpose of this invention is to provide the precise abnormal model of support of low expense among a kind of CPU.
Its implementation step is as follows:
1) in the retired impact damper of CPU, stores the address that next bar instructs for territory of each bar instruction definition;
2) retired address register of definition in the retired controller of CPU;
3) whether territory recording instruction of definition is finished in retired impact damper;
When 4) non-jump instruction is launched, the address of its next bar instruction is write in the corresponding territory of retired impact damper;
5) for jump instruction, in the execute phase, in the corresponding territory of address write buffer of its next bar instruction;
When 6) instruction is retired, instruction address in the retired impact damper is transferred in the retired address register;
7) during the CPU response abnormality, select suitable address to deliver to the exception processing unit of CPU.
Advantage of the present invention is: the hardware spending of circuit is lower, and data channel is few, has avoided using a lot of registers and MUX for preserving two addresses of every instruction preservation; Control circuit is fairly simple, and during unusually by response, CPU is easy to store the address of returning when unusual service finishes, and has guaranteed the quick response of anomalous event.
Description of drawings
Fig. 1 has shown the CPU structure of the precise abnormal model of simplifying of support;
Fig. 2 has shown the streamline synoptic diagram of memory address.
Embodiment
The address storage means of the support accurate model of low expense.Its implementation method is as follows:
1) in the retired impact damper of CPU, the address of holding instruction for the register (for the address bus of 32 bit wides) of one 32 bit wide of each inlet definition of impact damper;
2) register of one 32 bit wide of definition is used to store the address that the pensioner is instructed in the retired controller of CPU;
3) whether territory recording instruction of definition is finished in retired impact damper;
4) for jump instruction, in the execute phase, in the corresponding territory of address write buffer of its next bar instruction;
5) for other instruction, the address of its next bar instruction just can be determined in the stage of decoding, when transmitting instructions, this address was write in the corresponding territory of retired impact damper;
When 6) instruction is retired, the address of next bar instruction in the retired impact damper is stored in the retired address register of retired controller;
7) during the CPU response abnormality, be to store in the abnormal address register the address of retired instructions or the address of its next bar instruction according to just whether finishing decision in pensioner's instruction.
For this method clearly is described, we will explain this method according to its structural drawing, and this method has versatility to the CPU of the precise abnormal model of all kinds of supports.
Fig. 1 has shown a concise and to the point CPU structure, and the abbreviated functional description of various piece is as follows:
1) gets the finger unit and be responsible for instruction fetch from storer, give decoding and transmitting instructions unit;
2) decoding and transmitting instructions unit are deciphered the instruction of fetching and are determined when to launch and be transmitted into that functional unit, and distribute an inlet in retired impact damper;
3) functional unit is responsible for execution command, and common functional unit has arithmetic logical unit, shift operation unit, multiplication and division arithmetic element and jump instruction processing unit or the like;
4) retired impact damper is responsible for writing down that each bar has been launched but the information that also do not have the pensioner to instruct, and retired impact damper has four inlets can deposit four instructions among Fig. 1.Entry_vld indicates whether this inlet distributes to instruction, and complete indicates whether the instruction of this inlet has been finished, and next_pc then is used to deposit the address of next bar instruction;
5) retired controller retirement operation and the abnormality processing being responsible for instructing;
6) the CPU state controller is responsible for upgrading the state of CPU when the instruction retirement.
Usually CPU takes the instruction executive mode of pipeline organization.Fig. 2 has shown the instruction pipelining operation of the CPU of Fig. 1, wherein, and IF: instruction fetch; DE: instruction decode and emission; EX: ordering calculation; WB: the result writes back.
To serve as theme with this structural drawing below and introduce the address storage means of supporting precise abnormal model in detail.
The present invention is stored in the address of its next bar instruction in the retired impact damper when firing order, and does not store the address of the current instruction that is launched.Instruction 1 as shown in Figure 2 and instruction 2.
Article one, instruction is through after deciphering, and the address of next bar instruction is by the type decided of instruction.For non-jump instruction, the address of its next bar instruction is that the address of present instruction adds 2 (to 16 bit instruction collection) or adds 4 (to 32 bit instruction collection); For condition redirect and some absolute jump instructions, the address of its next bar instruction only could be determined in the execute phase, be written in the retired impact damper in this address of execute phase.Instruction 3 as shown in Figure 2.
When the instruction retirement, the current address of instructing as next bar in the retired address register is deposited in the address of next the bar instruction in retired impact damper.Although next bar instruction may also not be launched, when last instruction retirement, its address is determined.Unless anomalous event takes place, next bar instruction is article one instruction of unusual service routine.When this article one instruction was launched, the address of next bar instruction not only will write retired impact damper, and its address also will write retired address register.So just guaranteed that the address of its address and the instruction of next bar all provides when any instruction is retired, CPU can realize precise abnormal model, has reduced the physical overhead of two addresses of storage when transmitting instructions.If the retirement impact damper is only stored the address of present instruction when transmitting instructions, so retired controller also will be followed the tracks of the inlet label of next bar instruction, and steering logic is relatively complicated, and has introduced more MUX on data path.
When retired controller had captured anomalous event, if just finished in pensioner's instruction, the address of its next bar instruction was deposited in the abnormal address register so; Otherwise the address of retired instructions is deposited in the abnormal address register.After CPU withdraws from unusual service routine, get finger as the address of next bar instruction with the value of abnormal address register.
Claims (8)
1. the address storage means of the precise abnormal model of support of low expense among the CPU is characterized in that its step:
1) in the retired impact damper of CPU, stores the address that next bar instructs for territory of each bar instruction definition;
2) retired address register of definition in the retired controller of CPU;
3) whether territory recording instruction of definition is finished in retired impact damper;
When 4) non-jump instruction is launched, the address of its next bar instruction is write in the corresponding territory of retired impact damper;
5) for jump instruction, in the execute phase, in the corresponding territory of address write buffer of its next bar instruction;
When 6) instruction is retired, instruction address in the retired impact damper is transferred in the retired address register;
7) during the CPU response abnormality, select suitable address to deliver to the exception processing unit of CPU.
2. the address storage means of the precise abnormal model of support of low expense among a kind of CPU according to claim 1, it is characterized in that: each inlet of said retired impact damper has defined the register of one 32 bit wide, and is that it has write down each bar emission but do not have the address of next bar instruction that the pensioner instructs.
3. the address storage means of the precise abnormal model of support of low expense among a kind of CPU according to claim 1 is characterized in that: the retired address register of one 32 bit wide of definition in the said retired controller, it has just write down the address in pensioner's instruction.
4. the address storage means of the precise abnormal model of support of low expense among a kind of CPU according to claim 1, it is characterized in that: said all instructions are to launch according to the order of sequence, non-preface is finished, can whether territory recording instruction of definition be finished in retired impact damper, retirement and control the selection of abnormal address during exception response with decision instruction.
5. the address storage means of the precise abnormal model of support of low expense among a kind of CPU according to claim 1, it is characterized in that for non-jump instruction, when they were launched, the address of its next bar instruction was confirmable, and is written in the corresponding territory of retired impact damper.
6. the address storage means of the precise abnormal model of support of low expense is characterized in that for jump instruction among a kind of CPU according to claim 1, and the address of its next bar instruction could be determined in the execute phase.This class instruction will write the address of next bar instruction in the execute phase to retired buffer request.
7. the address storage means of the precise abnormal model of support of low expense among a kind of CPU according to claim 1, it is characterized in that all pensioners instruction, the address of its next bar instruction will write in the retired address register will pensioner's instruction as next bar the address.If retired impact damper is empty, the address of firing order is directly stored in the retired address register.
8. the address storage means of the precise abnormal model of support of low expense among a kind of CPU according to claim 1, when it is characterized in that response abnormality, if pensioner's instruction has been finished, the address of next bar instruction writes the abnormal address register; Otherwise the address of pensioner's instruction writes the abnormal address register.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA031161375A CN1514356A (en) | 2003-03-31 | 2003-03-31 | Address storage method for supporting precision abnormal model of CPU medium and low expense |
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| CNA031161375A CN1514356A (en) | 2003-03-31 | 2003-03-31 | Address storage method for supporting precision abnormal model of CPU medium and low expense |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104461468A (en) * | 2014-10-27 | 2015-03-25 | 杭州中天微系统有限公司 | Accurate anomaly maintenance method and device based on quick completion of processor instruction |
| CN108415729A (en) * | 2017-12-29 | 2018-08-17 | 北京智芯微电子科技有限公司 | A kind of processing method and processing device of cpu instruction exception |
| CN111290851A (en) * | 2018-12-20 | 2020-06-16 | 展讯通信（上海）有限公司 | Information processing method, device and storage medium |
-
2003
- 2003-03-31 CN CNA031161375A patent/CN1514356A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104461468A (en) * | 2014-10-27 | 2015-03-25 | 杭州中天微系统有限公司 | Accurate anomaly maintenance method and device based on quick completion of processor instruction |
| CN108415729A (en) * | 2017-12-29 | 2018-08-17 | 北京智芯微电子科技有限公司 | A kind of processing method and processing device of cpu instruction exception |
| CN111290851A (en) * | 2018-12-20 | 2020-06-16 | 展讯通信（上海）有限公司 | Information processing method, device and storage medium |
| CN111290851B (en) * | 2018-12-20 | 2022-11-29 | 展讯通信（上海）有限公司 | Information processing method, device and storage medium |
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