CN1512590A - Structure of flash memory and its operation method - Google Patents
Structure of flash memory and its operation method Download PDFInfo
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- CN1512590A CN1512590A CNA021600872A CN02160087A CN1512590A CN 1512590 A CN1512590 A CN 1512590A CN A021600872 A CNA021600872 A CN A021600872A CN 02160087 A CN02160087 A CN 02160087A CN 1512590 A CN1512590 A CN 1512590A
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Abstract
A flash memory structure is composed of a P-type basis, a deep N-type trap zone on the basis, a P-type trap zone in the deep trap zone, a pair of grids structure on the basis, a selection grid between the pair and a N-type source/drain zone in the P-type trap at both sides of the pair to increase the integrity of elements due to sharing one selection grid by every two adjacent double grid structure.
Description
Technical field
The invention relates to a kind of memory component, and particularly relevant for a kind of structure and method of operation thereof of flash memory.
Background technology
Flash element is owing to have and can repeatedly carry out the actions such as depositing in, read, erase of data, and the data that deposit in the advantage that also can not disappear after outage, so become extensively a kind of non-volatile memory component of employing of personal computer and electronic equipment institute.
Typical flash element is to make floating grid (Floating Gate) and control grid (Control Gate) with the polysilicon that mixes.And, the control grid. be set directly on the floating grid, floating grid is separated by with dielectric layer with controlling between the grid, and between floating grid and substrate with tunnel oxide (Tunnel Oxide) be separated by (that is so-called stacked gate flash memory).
When flash memory being carried out the operation that data write, be by applying bias voltage with source/drain regions, so that electronics injection floating grid in the control grid.During data in reading flash memory, be to apply an operating voltage on the control grid, this moment, the electriferous state of floating grid can influence the ON/OFF of its lower channel (Channel), and the ON/OFF of this passage is the foundation of interpretation data value " 0 " or " 1 ".When flash memory when carrying out the erasing of data, it is relative current potential raising with substrate, leakage (source) polar region or control grid, and utilize tunneling effect to make electronics pass tunnel oxide (Tunneling Oxide) and drain into (being Substrate Erase or Drain (Source) Side Erase) in substrate or the leakage (source) extremely by floating grid, or pass dielectric layer and drain into control grid in.
Yet, during data in the flash memory of erasing,, have positive charge so easily make floating grid discharge polyelectron, excessively erase (Over-Erase) that calls because the electron amount of discharging from floating grid is wayward.When this phenomenon of excessively erasing is too serious, in addition the passage that can make the floating grid below grid is undressed continues to be conducting state when making voltage in control, and cause the erroneous judgement of data.Therefore, in order to solve the problem that element is excessively erased, many flash memories can adopt the design of separated grid (Split Gate), its architectural feature is except control grid and floating grid, also have and be positioned at one of control grid and floating grid sidewall, substrate top and select grid (or being called the grid of erasing), this selects grid (grid of erasing) and controls between grid, floating grid and the substrate to be separated by with a gate dielectric layer.The phenomenon of so then ought excessively erasing is too serious, grid is undressed when doing promptly to continue to open under the voltage status in control and make under the floating grid square channel, select the passage of grid (grid of erasing) below still can keep closed condition, make that drain/source region can't conducting, and can prevent the erroneous judgement of data.Have bigger memory cell size owing to separated grid structure needs bigger separated grid zone, thus its memory cell size to have the memory cell size of stacked gate flash memory big, and produce the so-called problem that can't increase the element integrated level.So industry proposes a kind of double quick flash memory cell structure at present, make two memory cell share one and select grid (grid of erasing), and then the size of dwindling memory.
Fig. 1 is the profile of known a kind of double quick flash memory cell structure.Please refer to Fig. 1, this flash memory has two memory cell 101a, 101b in substrate 100.Memory cell 101a, 101b comprise grid structure 102a, 102b separately, these two grid structure 102a, 102b have tunnel oxide 104a, 104b in regular turn from substrate 100, floating grid 106a, 106b, gate dielectric 108a, 108b, control grid 110a, 110b and cap layer 112a, 112b.Sidewall at grid structure 102a, 102b has clearance wall 114a, 114b.Opposition side at two grid structure 102a, 102b is formed with source/drain regions 116a and 116b separately.Have the grid 118 of selection on grid structure 102a, 102b surface, this selects grid 118 to extend to another source/drain regions 116b from source/drain regions 116a.
When the memory cell 101a to this double quick flash memory cell knot programmed, memory cell 101b was as channel transistor.That is, on control grid 110a, apply 10 volts bias voltage; Applying 10 volts of bias voltages on the control grid 110b opens the passage of memory cell 101b below; Select to apply 2 volts bias voltage on the grid 118; Apply 2 volts bias voltage on the source/drain regions 116a, source/drain regions 116b is 0 volt.So, when sequencing, electronics is to be moved to source/drain regions 116a by source/drain regions 116b, and quickened by the high channel electric field and produce hot electron at source/drain regions 116a end, its kinetic energy is enough to overcome the energy barrier of tunnel oxide 104a, add on the control grid 110a and be applied with high positive bias, make hot electron inject floating grid 106a from source/drain regions 116a end, and sequencing memory cell 101a.Same, when memory cell 101b was carried out sequencing, memory cell 101a was as channel transistor.That is on control grid 110b, apply 10 volts bias voltage; The bias voltage that applies 10 volts on the control grid 110a is opened the passage of memory cell 101a below; Select to apply 2 volts bias voltage on the grid 118; Source/drain regions 116a is 0 volt, applies 2 volts bias voltage on the source/drain regions 116b.So, when sequencing, electronics is moved to source/drain regions 116b by source/drain regions 116a, and quickened by the high channel electric field and produce hot electron at source/drain regions 116b end, its kinetic energy is enough to overcome the energy barrier of tunnel oxide 104b, add on the control grid 110b and be applied with high positive bias, make hot electron inject floating grid 106b from source/drain regions 116b end.
In the method for programming of above-mentioned double quick flash memory cell, after memory cell 101a carried out sequencing, when again memory cell 101b being carried out sequencing, because memory cell 101b can be subjected to the influence of the memory cell 101a of sequencing, and make sequencing electric current step-down, so memory cell 101b sequencing speed can be lower than the sequencing speed of memory cell 101a.So will cause the asymmetric problem of memory cell sequencing, cause memory cell operation speed slack-off.
Summary of the invention
In view of this, structure and the method for operation thereof of a purpose of the present invention for a kind of flash memory is provided can improve the integrated level of memory component.
Structure and the method for operation thereof of another object of the present invention for a kind of flash memory is provided, it is asymmetric not have the memory cell sequencing, can reduce memory cell current, and improves the service speed of memory component.
Structure and the method for operation thereof of another object of the present invention for a kind of flash memory is provided can avoid memory cell excessively to erase.
The invention provides a kind of structure of flash element, the structure of this flash element is by the first conductivity type substrate, second conductivity type, first wellblock, first conductivity type, second wellblock, a pair of grid structure, select grid, with a pair of first conductivity type source electrode/drain region is constituted.Wherein, second conductivity type, first wellblock is arranged in the first conductivity type substrate; First conductivity type, second wellblock is arranged in second conductivity type, first wellblock; A pair of grid structure is arranged in the first conductivity type substrate; Select grid to be arranged between a pair of grid structure; A pair of first conductivity type source electrode/drain region is arranged at respectively in first conductivity type, second wellblock of a pair of grid structure both sides.
Above-mentioned a pair of grid structure is made of floating grid, tunnel oxide, control grid, gate dielectric, first clearance wall and second clearance wall.Wherein, floating grid is arranged on the first conductivity type substrate; Tunnel oxide is arranged between the floating grid and the first conductivity type substrate; The control grid is arranged on the floating grid; Gate dielectric is arranged between control grid and the floating grid; First clearance wall is arranged at the sidewall and the top of control grid; Second clearance wall is arranged at the sidewall of floating grid.And tunnel oxide more comprises being arranged at and selects between the grid and the first conductivity type substrate.
In flash element of the present invention, because sharing one, two adjacent two grid structures (memory cell) select grid, therefore can increase the integrated level of element.
The present invention provides a kind of method of operation of flash element in addition, is applicable to operation one flash element, and this flash element comprises the substrate of P type; The deep N-well district is arranged in the substrate of P type; The p type wells district is arranged in the deep N-well district; First memory cell and second memory cell are arranged in the substrate of P type, and first memory cell comprise first control grid, second memory cell comprise second control grid; Select grid, be arranged between first memory cell and second memory cell; First source/drain regions and second source/drain regions are arranged at respectively in the p type wells district of a side of first memory cell and second memory cell, and first source/drain regions and second source/drain regions are N type conductivity; And the method is when first memory cell of sequencing flash element, the first control grid is applied first positive voltage, the p type wells district is applied first negative voltage, making and selecting grid is that ground connection, first source/drain regions and second source/drain regions are for floating, to utilize F-N tunneling effect sequencing first memory cell; When reading first memory cell of flash element, to selecting grid to apply second positive voltage, the first control grid is applied second positive voltage, the second control grid is applied the 3rd positive voltage, second source/drain regions is applied one the 4th positive voltage, with first source/drain regions and p type wells district ground connection, to read the data of first memory cell; During memory cell on same character line of the flash element of erasing, to selecting grid to apply the 5th positive voltage, first control grid, very 0 volt of second control gate, first source/drain regions and second source/drain regions be for floating, to utilize the erase flash element of full page of F-N tunneling effect.
The method of operation of above-mentioned flash element more comprises: when second memory cell of sequencing flash element, the second control grid is applied first positive voltage, the p type wells district is applied first negative voltage, make and select grounded-grid, first source/drain regions and second source/drain regions for floating, to utilize F-N tunneling effect sequencing second memory cell.
In the flash element of the present invention, the p type wells district of isolation is set in the deep N-well district, therefore when programming operations, apply appropriate voltage by p type wells district in control grid and isolation, and utilize the F-N tunneling effect to make electronics pass tunnel oxide and enter in the floating grid by substrate (the p type wells district of isolation), therefore, after the first memory cell sequencing, when continuation is carried out programming operations to second memory cell, second memory cell can not be subjected to the influence of first memory cell of sequencing, and can avoid the asymmetric problem of memory cell sequencing.
In addition, the programming operations of passage flash memory devices of the present invention adopts the F-N tunneling effect, and its electron injection efficiency is higher, thus can reduce the memory cell current when encoding, and can improve service speed simultaneously.Because the sequencing and the action of erasing all utilize the F-N tunneling effect, its current drain I effectively reduces the power loss of whole memory component, also can be applied to the bypass procedureization of the large scale page/erase simultaneously.
Description of drawings
Fig. 1 is a kind of profile of known flash memory;
Fig. 2 is the vertical view of flash memory of the present invention;
Fig. 3 A and Fig. 3 F are along the manufacturing process profile of A-A ' line among Fig. 2;
Fig. 4 A and Fig. 4 D are along the manufacturing process profile of B-B ' line among Fig. 2;
Fig. 5 is the section of structure of flash memory of the present invention;
Fig. 6 is the electrical schematic diagram of flash memory of the present invention;
Fig. 7 A is the programming operations pattern diagram of flash memory of the present invention;
Fig. 7 B is the erase operation for use pattern diagram of flash memory of the present invention.
100,200,300,500: substrate
101a, 102b: memory cell
102a, 102b, 506: grid structure
104a, 104b, 308,512: tunnel oxide
106a, 106b, 208,514: floating grid
108a, 108b, 516: gate dielectric
110a, 110b, 206,518: control grid
112a, 112b: cap layer
114a, 114b, 216,218,316,322,520,522: clearance wall
116a, 116b, 210,320,508: source/drain regions
118,214,328,510: select grid
202,302: isolation structure
204: active region
212,306,504, PW0, PW1:P type wellblock
220,524: cell group
304,502: the deep N-well district
310,310a, 314,326: conductor layer
312,312a: dielectric layer
318,324: the patterning cover curtain layer
321,526: select grid oxic horizon
Qn1, Qn2, Qn3, Qn4, Qn5, Qn6, Qn7, Qn8: memory cell
BL0/S0, BL1/S1, BL2/S2: bit line/source electrode line
SG0 (WL0), SG1 (WL1): select gate line
Tn1, Tn2, Tn3, Tn4: select transistor
GC0, GC1, GC2, GC3: control gate line
Embodiment
Fig. 2 is the vertical view of flash memory of the present invention.Please refer to Fig. 2, flash memory of the present invention is by substrate 200, component isolation structure 202, active region 204, control grid 206 (character line), floating grid 208, N type source/drain regions 210, p type wells district 312 and selects grid 214.Constitute.Wherein, select between grid 214 and control grid 206, the floating grid 208 insulating barrier (clearance wall) 216 and insulating barrier (clearance wall) 218 to be set.Be provided with deep N-well district (not icon) in the substrate 200, p type wells district 212 is arranged in the deep N-well district.Component isolation structure 202 is arranged in the substrate 200, in order to define active region 204, makes 212 in p type wells district be arranged in active region 204.Control grid 206 is arranged in the substrate 200, and perpendicular to active region 204.Floating grid 208 is arranged at substrate 200 belows of control grid 206 (character line) across active region 204.In same active region 204, be one group with per two memory cell 220, between adjacent two memory cell, be provided with and select grid 214.N type source/drain regions 210 is arranged in the p type wells district 212 of each cell group 220 both sides.Selection grid 214 in the same active region 204 is to select gate line (not icon) electric property coupling together, and then electric property coupling together with bit line (not icon) for the N type source/drain regions 210 of same array in the different active 204.
Flash memory making method of the present invention then is described, Fig. 3 A to Fig. 3 F, Fig. 4 A to Fig. 4 D are for illustrating among Fig. 2 the manufacturing process profile along A-A ' line, B-B ' line respectively.
At first please refer to Fig. 3 A and Fig. 4 A, a P type substrate 300 is provided, this P type substrate 300 has formed component isolation structure 302, this component isolation structure 302 layout into strips, and in order to define active region.The formation method of component isolation structure 302 for example is regional oxidizing process (Local Oxidation, LOCOS) or shallow trench isolation method (Shallow TrenchIsolation, STI), wherein the degree of depth of component isolation structure 302 wants to isolate the p type wells district 306 of follow-up formation.Then, form deep N-well district 304 in P type substrate 300, and form p type wells district 306 in this deep N-well district 304, wherein the degree of depth in p type wells district 306 can not surpass the degree of depth of isolation structure 302.Afterwards, form layer of oxide layer 308 in P type substrate 300 surfaces, as the usefulness of tunnel oxide, the formation method of oxide layer 308 for example is a thermal oxidation method.
Then, please refer to Fig. 3 B and Fig. 4 B, form one deck conductor layer (not icon) on oxide layer 308, its material for example is the polysilicon that mixes, the formation method of this conductor layer for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, to carry out the ion implantation step to form it.The thickness of conductor layer for example is the 200 Izod right sides, the admixture of implanting conductor layer for example is an arsenic ion, be beneficial to erase round-shaped in order in follow-up thermal oxidation technology, being formed with, then with this conductor layer patterning, make its surface that exposes subelement isolation structure 302, and form as the conductor layer 310 in graphic.
Then, please refer to Fig. 3 C and Fig. 4 C.After forming one dielectric layer 312, one deck conductor layer (not icon) in the P type substrate 300, utilize the cover curtain in regular turn, in order to define conductor layer 314 as the usefulness of control grid with the conductor layer patterning.The material of dielectric layer 312 for example is a silicon oxide/silicon nitride/silicon oxide etc., and the formation method of dielectric layer 312 for example is a Low Pressure Chemical Vapor Deposition.Certainly, the material of this dielectric layer 312 also can be silicon oxide layer, silicon oxide/nitride layer etc.The material of conductor layer 314 for example is the polysilicon that mixes, and the formation method of conductor layer 314 for example is in the mode of (In-Situ) dopant ion of coming personally, and utilizes chemical vapour deposition technique to form it.
Remove after the cover curtain, form insulating barrier 316 in the sidewall and the top of conductor layer 314.The material of insulating barrier 316 for example is a silica, and the method that forms insulating barrier 316 for example is a thermal oxidation method.
Then please refer to Fig. 3 D and Fig. 4 D, serves as cover curtain definition dielectric layer 312, conductor layer 310 with conductor layer 314 and insulating barrier 316, makes it form dielectric layer 312a and conductor layer 310a respectively.Wherein, conductor layer 3 10a are as the usefulness of floating grid.That is the conductor layer of icon (control grid) 314, dielectric layer 312a, conductor layer (floating grid) 310a and oxide layer 308 (tunnel oxide) constitute grid structure.Then, form one deck patterning cover curtain layer 318 in whole substrate 300, this patterning cover curtain layer 318 exposes the predetermined zone that forms source/drain regions 320.Then, carrying out the ion implantation step, serves as the cover curtain with patterning cover curtain layer 318, and the p type wells district 306 in the substrate 300 of grid structure one side implants admixture and forms source/drain regions 320.Wherein, two grid structures can be considered a grid structure group.In the grid structure group, predetermined formation selected grid between the grid structure, and source/drain regions 320 then is formed in the grid structure group substrate on two sides.Because the structure of B-B ' the line section of Fig. 2 is all identical in subsequent technique, therefore following the technology at A-A ' the line section of Fig. 2 explains.
Then please refer to Fig. 3 E, remove patterning cover curtain layer 318 after, in the substrate between the grid structure 300, form to select grid oxic horizon 321, and form insulating barrier (clearance wall) 322 in the sidewall of conductor layer 310a (floating grid).Selecting the grid oxic horizon 321 and the material of insulating barrier (clearance wall) 322 for example is silica, and selecting the grid oxic horizon 321 and the formation method of insulating barrier (clearance wall) 322 for example is thermal oxidation method.Wherein, selecting the thickness of grid oxic horizon 321 for example is the 250 Izod right sides.Then, form another layer pattern cover curtain layer 324 in substrate 300, this patterning cover curtain layer 324 covers source/drain regions 320, and exposes the predetermined zone of selecting grid that forms.Then, in substrate 300, form one deck conductor layer 326.The material of conductor layer 326 for example is the polysilicon that mixes, and the formation method of conductor layer 326 for example is in the mode of the dopant ion of coming personally, and utilizes chemical vapour deposition technique to form it.
Then please refer to Fig. 3 F, remove segment conductor layer 326 and the surface of patterning cover curtain layer 326, select grid 328 and between grid structure, form up to exposure insulating barrier 316.Afterwards, remove the patterning cover curtain layer.The follow-up technology of finishing flash memory is known by known skill person, does not repeat them here.
Fig. 5 is the section of structure of flash memory of the present invention.
Please refer to Fig. 5, flash memory of the present invention is by P type substrate 500, deep N-well district 502, the p type wells district 504 that isolates, grid structure 506, N type source/drain regions 508, selects grid 510 to be constituted.Grid structure 506 is to be made of tunnel oxide 512, floating grid 514, gate dielectric 516, control grid 518 and 520,522 of clearance walls.
Deep N-well district 502 is arranged in P type substrate 500.The p type wells district 504 that isolates is arranged in deep N-well district 502.Grid structure 506 is positioned in the P type substrate 200, and per two neighboring gates structures 506 are a grid structure group 524.N type source/drain regions is arranged in the p type wells district 504 of grid structure group 524 both sides.Select between adjacent two grid structures 506 of grid 5 10 in the grid structure group.Selecting to have the grid oxic horizon 526 of selection between grid 510 and the substrate 500.Clearance wall 520 is positioned at control grid 518 tops and sidewall.Clearance wall 522 is positioned at floating grid 514 sidewalls.
The present invention shares one in per two adjacent two grid structures 506 (memory cell) and selects grid 510, therefore can increase the integrated level of element.
Fig. 6 is the electrical schematic diagram of flash memory of the present invention.P type wells district PW0 to PW1, the bit line/source electrode line BL0/S0 that in Fig. 5, illustrate a plurality of memory cell Qn1 to Qn8, selects transistor T n1 to Tn4, isolation to bit line/source electrode line BL2/S2, control gate line CG0 to control gate line CG3 with select gate line (character line) SG0 (WL0) to SG1 (WL1).A plurality of memory cell are selected transistor to be one group with per two memory cell and and are formed a plurality of cell group.Wherein select transistor to be arranged between two memory cell.Above-mentioned a plurality of cell group is arranged into delegation/column array, and adjacent two cell group are shared source.The source/drain regions of each memory cell in each cell group in each row all couples pairing one bit lines/source electrode line; The control grid of each memory cell of each row all couples a corresponding control gate line, each memory cell of each row is electrically connected with the p type wells district that isolates, and the transistorized grid of the selection of each row all couples a corresponding selection gate line (character line).For instance, in same row, memory cell Qn1, selection transistor T n1, memory cell Qn2 are one group, memory cell Qn3, selection transistor T n2, memory cell Qn4 are one group, memory cell Qn5, selection transistor T n3, memory cell Qn6 are one group, and memory cell Qn7, selection transistor T n4, memory cell Qn8 are one group.The source/drain of memory cell Qn1, Qn5 side is coupled to bit line/source electrode line BL0/S0, the source/drain of memory cell Qn2, Qn3, Qn6, Qn7 side is coupled to bit line/source electrode line BL1/S1, and the source/drain of memory cell Qn4, Qn8 side is coupled to bit line/source electrode line BL2/S2.Control gate line CG0 connects the control grid of memory cell Qn1, Qn5, control gate line CG1 connects the control grid of memory cell Qn2, Qn6, control gate line CG2 connects the control grid of memory cell Qn3, Qn7, and control gate line CG3 connects the control grid of memory cell Qn4, Qn8.Select gate line (character line) SG0 (WL0) to connect the grid of selecting transistor T n1, Tn2, select gate line (character line) SG1 (WL1) to connect the grid of selecting transistor T n3, Tn4.Memory cell Qn1, Qn2, Qn3 and Qn4 with the p type wells district PW0 electric property coupling of isolating together, memory cell Qn5, Qn6, Qn7 and Qn8 are with the p type wells district PW1 electric property coupling of isolation together.
Memory cell array of the present invention is to share one with per two memory cell to select transistor (selection grid), therefore can dwindle the size of memory cell, and by this kind design, make memory cell array of the present invention also have the less advantage of size of NAND gate (NAND) type memory cell array as is well known, and can increase integrated level.
Then, please refer to Fig. 7 A and Fig. 7 B, with the operator scheme of the flash element of understanding preferred embodiment of the present invention, it comprises sequencing (Program, Fig. 7 A), data read (Read), and (the Erase that erases, Fig. 7 B) operator scheme such as, and be to be example with memory cell Qn1 shown in Figure 6, Qn2.
When memory cell Qn1 is carried out sequencing, on control grid 606a (CG0), apply a positive bias V
CGp, it for example is about 10 volts to 12 volts, and applies back bias voltage-V on p type wells district 604 (PW0)
PWp, it for example is-6 volts to about-8 volts, and source/drain regions 612 (BL0/S0), source/drain regions 614 (BL1/S1) are for floating, and selecting grid 610 (SG0) is 0 volt.So, when sequencing, so, can between floating grid 606a and substrate 600, set up a big electric field, be entered among the floating grid 606a and utilize passage F-N tunneling effect (Channel F-N Tunneling) to make electronics pass tunnel oxide 616.Same, when memory cell Qn2 is carried out sequencing, on control grid 606b (CG1), apply a positive bias V
CGp, it for example is about 10 volts to 12 volts, and applies back bias voltage-V on p type wells district 604 (PW0)
PWp, it for example is-6 volts to about-8 volts, and source/drain regions 612 (BL0/S0) and source/drain regions 614 (BL1/S1) are for floating, and selecting grid 610 (SG0) is 0 volt.So, when sequencing, so, can between floating grid 606b and substrate 600, set up a big electric field, be entered among the floating grid 606b and utilize the F-N tunneling effect to make electronics pass tunnel oxide 616, shown in Fig. 7 A.
When carrying out the said procedure operation, memory cell Qn5, Qn6 can't sequencing.This is because the p type wells district (PW1) that isolates is 0V, so memory cell Qn5, Qn6 can't produce the F-N tunneling effect, certainly just can not sequencing Qn5, Qn6.
In addition, the voltage of the control gate line CG3 of the control gate line CG2 of connection memory cell Qn3, Qn7, connection memory cell Qn4, Qn8 is 0 volt, so memory cell Qn3, Qn4, Qn7 and Qn8 can't produce the F-N tunneling effect.
When carrying out the read operation of memory cell Qn1, memory cell Qn1 reads bias voltage and can be set as follows: the bias voltage of source/drain regions 612 (BL0/S0) is V
d, it for example is about 1 volt to 1.5 volts, select the bias voltage of grid 610 (SG0 (WL0)) be Vcc its for example be about 3.3 volts, the bias voltage of control grid 608a (CG0) be Vcc its for example be about 3.3 volts, the bias voltage of control grid 608b (CG1) is V
CGR, it for example is about 10 volts, source/drain regions 614 (BL1/S1) is ground connection with the p type wells district 604 (PW0) that isolates.When carrying out the read operation of memory cell Qn2, memory cell Qn2 reads bias voltage and then can be set as follows: the bias voltage of source/drain regions 614 (BL1/S1) is V
d, it for example is about 1 volt to 1.5 volts, select the bias voltage of grid 610 (SG0 (WL0)) be Vcc its for example be about 3.3 volts, the bias voltage of control grid 608b (CG1) be Vcc its for example be about 3.3 volts, the bias voltage of control grid 608a (CG0) is V
CGR, it for example is about 10 volts, source/drain regions 612 (BL0/S0) is ground connection with the p type wells district 604 (PW0) that isolates.Because it is very little that floating grid has the pathway closure and the electric current of memory cell of electronics, and floating grid does not have that the passage of the memory cell of electronics is opened and electric current is big, so can judge that the digital information that is stored in this memory cell is " 1 " or " 0 " by the channel switch/channel current size of memory cell.
When to memory cell Qn1, when Qn2 erases, on control grid 608a (CG0), control grid 608b (CG0), apply 0 volt; To selecting grid 610 (SG0) to apply a positive bias is V
SGEIt for example is about 10 volts to 12 volts, source/drain regions 612 (BL0/S0), source/drain regions 614 (BL1/S1) and the p type wells district (PW1) that isolates be for floating.So, can and select at floating grid 606a, floating grid 606b to set up a big electric field between the grid 610, be selected the grid and utilize the F-N tunneling effect that electronics is drawn out to from floating grid 606a, floating grid 606b, shown in Fig. 7 B.
When carrying out above-mentioned erase operation for use, because sharing one, selection transistor T n1 between memory cell Qn1, the Qn2 and the selection transistor T n2 between memory cell Qn3, the Qn4 select gate line (character line) SG0 (WL0), therefore when erasing memory cell Qn1, Qn2, the memory cell Qn3 of the same page, Qn4 also can be erased.And selection gate line (character line) SG1 (WL1) that selection transistor T n3 between memory cell Qn5, the Qn6 and the selection transistor T n4 between memory cell Qn7, the Qn8 are shared is not applied with voltage, so memory cell Qn5, Qn6, Qn7 and Qn8 can't produce FN-tunneling effect (Channel FNTunneling) and data in the memory cell of erasing.That is, flash memory of the present invention is to be unit with a page when carrying out erase operation for use, therefore when flash memory of the present invention is carried out erase operation for use, as long as it for example is bias voltage about 10 volts to 12 volts that the selection gate line (character line) of the predetermined page of erasing is applied, and to make control gate line be 0 volt, can utilize to produce erase data in the memory cell of a full page of FN-tunneling effect.
In the flash element of the present invention, the p type wells district of isolation is set in the deep N-well district, therefore when programming operations, apply appropriate voltage by p type wells district in control grid and isolation, and utilize the F-N tunneling effect to make electronics pass tunnel oxide and enter in the floating grid by substrate (the p type wells district of isolation), therefore, after memory cell Qn1 sequencing, when continuation is carried out programming operations to memory cell Qn2, memory cell Qn2 can not be subjected to the influence of the memory cell Qn2 of sequencing, and can avoid the asymmetric problem of memory cell sequencing.And the present invention also can be by applying a positive bias V simultaneously on control grid 606a (CG0) and control grid 606b (CG1)
CGp, and on p type wells district 604 (PW0), apply back bias voltage-V
PWp, source/drain regions 612 (BL0/S0) and source/drain regions 614 (BL1/S1) are for floating, and selecting grid 610 (SG0) is 0 volt, and the memory cell of sequencing simultaneously Qn1, Qn2.
And the programming operations of passage flash memory devices of the present invention adopts the F-N tunneling effect, and its electron injection efficiency is higher, thus can reduce the memory cell current when encoding, and can improve service speed simultaneously.Because the sequencing and the action of erasing all utilize the F-N tunneling effect, its current drain I effectively reduces the power loss of whole memory component, also can be applied to the bypass procedureization of the large scale page/erase simultaneously.
Claims (18)
1. the structure of a flash element is characterized in that, the structure of this flash element comprises:
One first conductivity type substrate;
One second conductivity type, first wellblock, this second conductivity type, first wellblock is arranged in this substrate;
One first conductivity type, second wellblock, this first conductivity type, second wellblock are arranged in this second conductivity type, first wellblock;
A pair of grid structure, this is arranged in this first conductivity type substrate grid structure;
One selects grid, and this selection grid is arranged at this between the grid structure; And
A pair of first conductivity type source electrode/drain region, this is arranged at respectively in this this first conductivity type, second wellblock to the grid structure both sides first conductivity type source electrode/drain region.
2. the structure of flash element as claimed in claim 1 is characterized in that, this first conductivity type substrate comprises the substrate of P type.。
3. the structure of flash element as claimed in claim 1 is characterized in that, this second conductivity type, first wellblock comprises N type wellblock.
4. the structure of flash element as claimed in claim 1 is characterized in that, this first conductivity type, second wellblock comprises the p type wells district.
5. the structure of flash element as claimed in claim 1 is characterized in that, this is to first conductivity type source electrode/drain region doped N-type ion.
6. the structure of flash element as claimed in claim 1 is characterized in that, each comprises at least to grid structure:
One floating grid, this floating grid are arranged on this first conductivity type substrate;
One tunnel oxide, this tunnel oxide are arranged between this floating grid and this first conductivity type substrate;
One control grid, this control grid is arranged on this floating grid;
One gate dielectric, this gate dielectric are arranged between this control grid and this floating grid;
One first clearance wall, this first clearance wall is arranged at the sidewall and the top of this control grid; And
One second clearance wall, this second clearance wall is arranged at the sidewall of this floating grid.
7. the structure of flash element as claimed in claim 6 is characterized in that, comprises that more one selects grid oxic horizon, is arranged between this selection grid and this first conductivity type substrate.
8. the structure of flash element as claimed in claim 6 is characterized in that, the material of this first clearance wall comprises silica.
9. the structure of flash element as claimed in claim 6 is characterized in that, the material of this second clearance wall comprises silica.
10. the method for operation of a flash element is applicable to operation one flash element, and this flash element comprises a P type substrate; One N type wellblock is arranged in this P type substrate; One p type wells district is arranged in this N type wellblock; One first memory cell and one second memory cell are arranged in this P type substrate, and this first memory cell comprises that one first control grid and this second memory cell comprise one second control grid; One selects grid, is arranged between this first memory cell and this second memory cell; One first source/drain regions and one second source/drain regions are arranged at respectively in this p type wells district of a side of this first memory cell and this second memory cell, and this first source/drain regions and this second source/drain regions are N type conductivity; It is characterized in that this method comprises:
When this first memory cell of this flash element of sequencing, this first control grid is applied one first positive voltage, this p type wells district is applied one first negative voltage, make this selection grounded-grid, this first source/drain regions and this second source/drain regions are for floating, to utilize this first memory cell of F-N tunneling effect sequencing;
When reading this first memory cell of this flash element, this selection grid is applied one second positive voltage, this first control grid is applied this second positive voltage, this second control grid is applied one the 3rd positive voltage, this second source/drain regions is applied one the 4th positive voltage, this first source/drain regions and this p type wells district are floated, to read the data of this first memory cell; And
When this first memory cell of this flash element of erasing, this selection grid is applied one the 5th positive voltage, make very 0 volt of this first control grid, this second control gate, this first source/drain regions and this second source/drain regions be for floating, to utilize F-N tunneling effect this flash element of erasing.
11. the method for operation of flash element as claimed in claim 10 is characterized in that, this method more comprises:
When this second memory cell of this flash element of sequencing, this second control grid is applied this first positive voltage, this p type wells district is applied this first negative voltage, make this selection grounded-grid, this first source/drain regions and this second source/drain regions are for floating, to utilize this second memory cell of F-N tunneling effect sequencing.
12. the method for operation of flash element as claimed in claim 10 is characterized in that, this method more comprises: when this first memory cell of this flash element of erasing, and this second memory cell of erasing simultaneously.
13. the method for operation of flash element as claimed in claim 10 is characterized in that, this first positive voltage is about 10 volts to 12 volts.
14. the method for operation of flash element as claimed in claim 10 is characterized in that, this first negative voltage is about-6 volts to-8 volts.
15. the method for operation of flash element as claimed in claim 10 is characterized in that, this second positive voltage is about 3.3 volts.
16. the method for operation of flash element as claimed in claim 10 is characterized in that, the 3rd positive voltage is about 10 volts.
17. the method for operation of flash element as claimed in claim 10 is characterized in that, the 4th positive voltage is about 1 volt to 1.5 volts.
18. the method for operation of flash element as claimed in claim 10 is characterized in that, the 5th positive voltage is about 10 volts to 12 volts.
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| CN 02160087 CN1259723C (en) | 2002-12-31 | 2002-12-31 | Structure of flash memory and its operation method |
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| CN 02160087 CN1259723C (en) | 2002-12-31 | 2002-12-31 | Structure of flash memory and its operation method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100511715C (en) * | 2006-02-13 | 2009-07-08 | 旺宏电子股份有限公司 | Dual-gate, non-volatile memory cells, arrays thereof, methods of manufacturing the same and methods of operating the same |
| CN106158870A (en) * | 2015-03-10 | 2016-11-23 | 物联记忆体科技股份有限公司 | Non-volatile Memory And Erasing Method Thereof |
| CN106952924A (en) * | 2016-01-05 | 2017-07-14 | 台湾积体电路制造股份有限公司 | Flush memory device with high coupling ratio |
| CN112951833A (en) * | 2019-12-11 | 2021-06-11 | 力旺电子股份有限公司 | Memory cell with isolation well region and related non-volatile memory |
-
2002
- 2002-12-31 CN CN 02160087 patent/CN1259723C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100511715C (en) * | 2006-02-13 | 2009-07-08 | 旺宏电子股份有限公司 | Dual-gate, non-volatile memory cells, arrays thereof, methods of manufacturing the same and methods of operating the same |
| CN106158870A (en) * | 2015-03-10 | 2016-11-23 | 物联记忆体科技股份有限公司 | Non-volatile Memory And Erasing Method Thereof |
| CN106158870B (en) * | 2015-03-10 | 2019-06-11 | 物联记忆体科技股份有限公司 | Non-volatile memory and erasing method thereof |
| CN106952924A (en) * | 2016-01-05 | 2017-07-14 | 台湾积体电路制造股份有限公司 | Flush memory device with high coupling ratio |
| CN112951833A (en) * | 2019-12-11 | 2021-06-11 | 力旺电子股份有限公司 | Memory cell with isolation well region and related non-volatile memory |
| CN112951833B (en) * | 2019-12-11 | 2023-06-16 | 力旺电子股份有限公司 | Memory cell with isolated well region and related nonvolatile memory |
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| Publication number | Publication date |
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| CN1259723C (en) | 2006-06-14 |
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