CN1509024A - Apparatus for realizing SPI4 phase II bus support multi path physical device - Google Patents
Apparatus for realizing SPI4 phase II bus support multi path physical device Download PDFInfo
- Publication number
- CN1509024A CN1509024A CNA021580170A CN02158017A CN1509024A CN 1509024 A CN1509024 A CN 1509024A CN A021580170 A CNA021580170 A CN A021580170A CN 02158017 A CN02158017 A CN 02158017A CN 1509024 A CN1509024 A CN 1509024A
- Authority
- CN
- China
- Prior art keywords
- data
- bus
- spi4
- phase
- interface module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Bus Control (AREA)
Abstract
The device comprises low speed bus interface module, SPl4 Phase II interface module, up running data mapping module, running downwards data mapping module, configuration bus interface module. The device maps the low speed bus interface module received 2.5Gbps bus data of multiple physical devices to SPl4 Phase II bus data by using the up running data mapping module as well as through SPl4 Phase II interface module sends the received 2.5Gbps bus data to the SPl4 Phase II bus. Meanwhile, the SPl4 Phase II bus data received by the SPl4 Phase II interface module through the running downwards data mapping module are mapped to multiple 2.5Gbps bus data, which through the low speed bus interface module are sent to multiple physical devices connected to 2.5Gbps bus.
Description
Technical field
The present invention relates to a kind of application technology of STD bus, particularly a kind of SPI4 Phase II bus that realizes is supported the device of multichannel physical equipment.
Background technology
SPI4 Phase II bus is a kind of light internet forum (Optical InternetworkingForum, OIF) STD bus that is used for communications field high speed data delivery of formulating and recommending.SPI4 PhaseII bus is applicable to that data link layer device (Link Layer Device) and the data between the physical layer equipment (PHY Device) in the communication system transmit, throughput satisfies OC-192c speed, and promptly the data flow of 10Gbps speed transmits requirement.SPI4 Phase II bus mainly contains following characteristics:
A, interface bus level use low-voltage differential level (LVDS) I/O (I/O), and transmit-receive position is 16 (bit) bus interface separately, but owing to be differential signal, actual signal quantity should be each 32 of transmit-receive positions;
B, the minimum clock frequency 311Mhz of bus, 16 pairs of LVDS differential data line can provide the message transmission rate that is not less than 9.952Gbps;
Data transmit control signal in C, the band, are with outer back-pressure flow control signal;
D, point-to-point data mode can only can not be divided into a plurality of independently low speed bus as an overall work.Promptly only support a physical equipment.But can support the ability of maximum 256 physics subports in the physical equipment.
The application of SPI4 Phase II bus is referring to Fig. 1, and Fig. 1 is the schematic diagram of SPI4 Phase II bus application model, and as shown in Figure 1, SPI4 Phase II bus 1 can only be connected to a link layer device 101 on the physical layer equipment 102.
Along with the demand to OC-192c, gigabit Ethernet (10GE) and other higher rate ports of Communications Market from now on constantly increases, SPI4 Phase II bussing technique will be used widely.SPI4Phase II can satisfy the major applications occasion, but can face big difficulty when single 10Gbps passage is supported a plurality of variety classes mixed low speed port.
At present, Chang Yong low speed bus as: it is that 2.5Gbps uses that POS-PHY Level 3 buses, SPI3 bus etc., these two kinds of bus standards, bus throughput satisfy OC-48c.Can not satisfy the SPI4 Phase II bus realization intercommunication that OC-192c is a 10Gbps speed with throughput.Wherein, POS-PHY Level 3 buses are used for point-to-point high speed data delivery, for example the butt joint between link layer and the physical chip.SPI3 is the bus standard that the OIF of International Standards Organization formulates on the basis of POS-PHY Level 3, and content and POS-PHYLevel 3 are much at one.General nothing specifies that SPI3 and POS-PHY Level 3 just are meant same bus.
POS-PHY Level 3 bus standards are used to realize the interconnection between optical-fiber network (SONET/SDH) physical layer and the link layer device, can support multiple upper-layer protocol, as: High level data link control (HDLC), PPP(Point-to-Point Protocol) etc.POS-PHY Level 3 interface bus standards adopt out of band signal transmission packet header (SOP), bag tail (EOP), and current loading error occurrings (ERR) etc. adopt inband signaling to transmit the logical sub port numbers.Data bit width can adopt 8Bit or 32Bit.Maximum functional clock frequency 100Mhz.The maximum data rate can reach 2.4G.When data bit width adopts 32Bit, referring to Fig. 2, Fig. 2 is POS-PHY Level 3 system reference model schematic diagrames: as shown in Figure 2, link layer device 201 links to each other with multichannel physical equipment 202 by POS-PHY Level 3 buses 2, and multichannel physical equipment 202 has connected four optical transceivers 203.
At present, SPI4 Phase II bussing technique, can not realize that single 10Gbps passage supports a plurality of variety classes mixed low speed ports, and there is not ripe solution SPI4 Phase II to support the solution of a plurality of physics subsets, can only use a plurality of logical sub ports in the SPI4 Phase II bus support single one physical equipment, support a plurality of diverse phy chips simultaneously owing to not providing like this, limited the range of application of SPI4 Phase II bus.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of SPI4 of realization Phase II bus to support the device of multichannel physical equipment, make SPI4 Phase II bus can support the multichannel physical equipment, the range of application of extended SPI 4 Phase II buses.
For achieving the above object, technical scheme of the present invention specifically is achieved in that
A kind of SPI4 Phase II bus that realizes is supported the device of multichannel physical equipment, and this device comprises:
The low speed bus interface module comprises an above low speed bus input interface, an above low speed bus output interface, and this module is used to connect the physical equipment more than a tunnel; The low speed bus input interface receives the 2.5Gbps bus data that every road physical equipment sends, and sends to the upstream data mapping block; The data that SPI3 bus output interface downlink data receiving mapping block sends are on the physical equipment that the 2.5Gbps bus more than a tunnel sends to this 2.5Gbps bus links to each other;
SPI4 Phase II interface module, comprise an above logical sub port, this module is used to receive the data that the upstream data mapping block sends, and data are sent on the SPI4 Phase II bus according to the logical sub port numbers, or receive SPI4 Phase II bus data, and send to the downlink data mapping block by the logical sub port;
The upstream data mapping block, it is used to receive the data that the low speed bus input interface sends, and number data is mapped on the logical sub port of SPI4 Phase II interface module one by one according to physical device number and low speed bus input interface;
The downlink data mapping block, it is used to receive the data that the SPI4 interface module sends, and according to the logical sub port numbers data is mapped on the fixing corresponding low speed bus output interface one by one;
The configuration bus interface module, the state that it is used to dispose and control SPI4 Phase II interface module, upstream data mapping block and reads the low speed bus interface module.
Wherein, the low speed bus interface module can further comprise Date Conversion Unit, it will be converted to 64 bit wides from the 32 bit wide data that the 2.5Gbps bus receives, and to be combined into bit wide with control signal corresponding be 70 data, send into the upstream data mapping block, the address signal of each low speed bus input interface is lumped together send into the configuration bus interface module simultaneously; Or go out 64 payload user data, control signal corresponding and address signal from the extracting data that the downlink data mapping block reads, corresponding control signal and data-signal are converted to the standard 2.5Gbps bus data that meets 32 bit wides, output to corresponding low speed bus output interface.
The upstream data mapping block can further comprise: first functional unit, it receives the data of 70 bit wides from the low speed bus input interface, from configuration bus interface module receiver address signal, and 70 bit data are sent into corresponding synchronous first-in first-out buffer memory according to address signal; Synchronous first-in first-out buffer memory more than one after its data that functional unit one is sent are kept in, sends to second functional unit; Second functional unit, it is according to first data of reading from each synchronous first-in first-out buffer memory simultaneously, state information with each synchronous first-in first-out buffer memory, selecting can be to sending data synchronization first-in first-out buffer memory outside, when more than one synchronous first-in first-out buffer memory can send data, the data that the address is minimum sent to asynchronous first-in first-out buffer memory; Asynchronous first-in first-out buffer memory more than one after its data that second functional unit is sent are kept in, sends to the 3rd functional unit; The 3rd functional unit, it reads asynchronous first-in first-out buffer memory, and the data that read out are outputed to SPI4 Phase II interface module by SPI4 Phase II bus format.
One of the first-in first-out buffer memory can send flow-control information to first functional unit by output synchronously, and first functional unit stops to send data to synchronous first-in first-out buffer memory according to this flow-control information, or continues to send data to synchronous first-in first-out buffer memory.
An output of asynchronous first-in first-out buffer memory can send flow-control information to two functional units, and second functional unit stops to send data to asynchronous first-in first-out buffer memory according to this flow-control information, or continues to send data to asynchronous first-in first-out buffer memory.
An output of SPI4 Phase II interface module can send flow-control information to the 3rd functional unit, the 3rd functional unit stops to send data to SPI4 Phase II interface module according to this information, or continues to send data to SPI4 Phase II interface module.
The downlink data mapping block can further comprise asynchronous first-in first-out buffer memory more than, this asynchronous first-in first-out buffer memory is corresponding one by one with the low speed bus output interface, the data that receive from SPI4 Phase II interface module send to asynchronous first-in first-out buffer memory temporary after, re-send to the low speed bus output interface.
SPI4 Phase II interface module can be the SPI4 Phase II interface logic ip module (Intellectual Property Core) of commercialization, also can be independently developed SPI4 Phase II interface module.
Low speed bus interface module wherein can be the SPI3 interface module.
In addition, this device itself can be used as the reusable design part in Programmable Logic Device or the application-specific integrated circuit (ASIC).
As seen from the above technical solutions, this realization SPI4 Phase II bus of the present invention is supported the device of multichannel physical equipment, the physical equipment that multichannel 2.5Gbps bus is connected is mapped on the SPI4Phase II bus, solve single 10Gbps passage and can not support the problem of a plurality of variety classes mixed low speed ports, realize SPI4 Phase II bus support multichannel physical equipment, and expanded the range of application of SPI4Phase II bus.
Description of drawings
Fig. 1 is the schematic diagram of SPI4 Phase II bus application model;
Fig. 2 is POS-PHY Level 3 system reference model schematic diagrames;
Fig. 3 is the logic diagram of one embodiment of the invention;
Fig. 4 is the logic diagram of middle upstream data mapping block embodiment illustrated in fig. 3;
Fig. 5 is the logic diagram of middle downlink data mapping block embodiment illustrated in fig. 3.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with embodiment and accompanying drawing, the present invention is described in more detail.
The present invention mainly pays close attention to and solves the scheme that SPI4 Phase II supports a plurality of low speed physical interfaces, below describes as an embodiment in the 2.5Gbps interface that needs among the present invention to use with the SPI3 bus interface.Do not explicitly call in actual applications and must use the SPI3 bus, use the present invention but not have the application of SPI3 interface requirements, only need to change the corresponding interface circuits module and can realize the present invention for needs.
The realization SPI4 Phase II bus of present embodiment is supported the device of multichannel physical equipment, be to utilize the maximum characteristics of supporting 256 logical sub ports of SPI4 Phase II bus, on a plurality of SPI3 buses, is all physical equipments of the SPI3 bus of 2.5Gbps on connecting thereby make SPI4 Phase II bus can connect a plurality of speed with SPI4 Phase II logical sub port mapping.
Consider that SPI4 Phase II bus does not often need 256 logical sub ports in actual applications, because SPI3 bus itself also can maximumly be supported 256 logical sub ports, for simplified design, one embodiment of the present of invention design every road SPI3 bus physical equipment and support four logical sub ports, then the technical scheme of present embodiment has realized four separate physical equipment of SPI4 Phase II bus support, 16 logical sub ports.
The structure of present embodiment is referring to Fig. 3, and Fig. 3 is the logic diagram of one embodiment of the invention.As shown in Figure 3, present embodiment has comprised SPI3 interface module 310, and it has comprised four SPI3 bus input interfaces 311 and four SPI3 bus output interfaces 312, upstream data mapping block 320, downlink data mapping block 350, SPI4 Phase II interface module 330 and configuration bus interface (CBI) modules 340.Wherein, SPI3 interface module 310 comprises also that a data converting unit, SPI4 Phase II interface module 330 also comprise 16 logical sub ports, downlink data mapping block 350 also comprises four asynchronous first-in first-out buffer memorys, and is not shown.
Below by data flow this embodiment is described.Uply be meant from No. four physical equipments to SPI4Phase II bus descending being meant from SPI4 Phase II bus to No. 4 physical equipments.Referring to Fig. 3, wherein, the up process of this embodiment is:
Data are input to 4 SPI3 bus input interfaces 311 of SPI3 interface module 310 respectively from four physical equipments.In up process, because the SPI3 bus has adopted and has been operated in 32 interface modes that (bit) is wide, so Date Conversion Unit is converted to 64 bit wides with the data of 32 bit wides, and signals such as control signal corresponding such as SOP, EOP, ERR and data message lumped together, the composition bit wide is 70 data, sends into upstream data mapping block 320.Simultaneously with 2 bit address signals of each SPI3 interface data totally 8 bit address lump together and send into CBI interface module 340.
Upstream data mapping block 320 receives the data that SPI3 input interfaces 311 send, and according to physical device number and SPI3 bus input interface number data is mapped to one by one on the logical sub port of SPI4 Phase II interface module 330 just on the logical sub port of SPI4 Phase II bus.
SPI4 Phase II interface module 330 receives the data that upstream data mapping block 320 sends, and according to the logical sub port numbers data is sent on the SPI4 Phase II bus.
Wherein, the logical construction of upstream data mapping block 330 is referring to Fig. 4, and Fig. 4 is the logic diagram of middle upstream data mapping block embodiment illustrated in fig. 3.As shown in Figure 4, the upstream data mapping block comprises three functional units 401,404 and 406, also comprises 403, two asynchronous FIFOs 405 of 16 synchronous first-in first-out buffer memorys (FIFO).
First functional unit 401, receiving bit wides from SPI3 interface module 310 is 70 data, from CBI interface module 340 receiver address signals, and according to address signal 70 bit data is sent into corresponding synchronization fifo 403;
Synchronization fifo 403 after the data that first functional unit 401 is sent are temporary, sends to second functional unit 404; Synchronization fifo 403 further sends flow-control information according to the state of synchronization fifo 403 to first functional unit 401, and first functional unit 401 stops to send data to synchronization fifo 403 according to this flow-control information, or continues to send data to synchronization fifo 403.
Second functional unit 404, according to first data of from each synchronization fifo 403, reading simultaneously, state information with each synchronization fifo 403, selecting those synchronization fifos 403 can be to sending data outside, when a plurality of synchronization fifo 403 can send data, the data that the address is minimum sent to asynchronous FIFO 405.
Asynchronous FIFO 405 after the data that second functional unit 404 is sent are temporary, sends to the 3rd functional unit 406; Asynchronous FIFO 405 further sends flow-control information according to the state of asynchronous FIFO 405 to second functional unit 404, and second functional unit 404 stops to send data to asynchronous FIFO 405 according to this flow-control information, or continues to send data to asynchronous FIFO 405.
The 3rd functional unit 405 reads asynchronous FIFO 405, and the data based address that will read out outputs on the logical sub port corresponding in the SPI4 Phase II interface module by SPI4Phase II bus format.
In addition, the 3rd functional unit 406 can further receive the flow-control information that SPI4 Phase II interface module sends, the 3rd functional unit 406 stops to send data to SPI4 Phase II interface module according to this information, or continues to send data to SPI4 Phase II interface module.
Referring to Fig. 3, the descending process of this embodiment is:
Data are input to downlink data mapping block 350 from each logical sub port of SPI4 Phase II interface module 330, and the structure of downlink data mapping block 350 is referring to Fig. 5, and Fig. 5 is the logic diagram of middle downlink data mapping block embodiment illustrated in fig. 3.As shown in Figure 5, downlink data mapping block 350 mainly comprises descending map unit 502 and four asynchronous FIFOs 501, respectively deliver to four asynchronous FIFOs 501 by descending map unit 502 by the fixing address mapping relation of each logical sub port from the data that SPI4 Phase II interface module 330 receives, four corresponding one by one respectively four SPI3 bus output interfaces 312 of asynchronous FIFO 501, data send on the corresponding SPI3 bus output interface 312 from asynchronous FIFO 501.Date Conversion Unit in the SPI3 interface module 310, in the data downstream process, the extracting data that reads from downlink data mapping block 350 goes out 64 payload user data, control signal corresponding such as SOP, EOP, ERR and address signal, SPI4Phase II interface module logical sub port and SPI3 logical sub port mapping relation according to prior regulation, corresponding control signal and data-signal become meet the reference format that bit wide is 32 a SPI3 bus data, output to corresponding SPI3 bus output interface 312.Data send on the corresponding physical equipment from SPI3 bus output interface 312.Configuration bus interface module 340 is in descending process, according to the configuration order configuration SPI4 Phase II interface module of external system.
Above-mentioned SPI4 Phase II interface module can also can be independently developed SPI4 Phase II interface module for the SPI4 Phase II interface logic IP Core of commercialization.
By the above embodiments as seen, this realization SPI4 Phase II bus of the present invention is supported the device of multichannel physical equipment, the physical equipment that a plurality of SPI3 buses are connected is mapped on the SPI4 Phase II bus, solve single 10Gbps passage and can not support the problem of a plurality of variety classes mixed low speed ports, realize SPI4 Phase II bus support multichannel physical equipment, and expanded the range of application of SPI4 Phase II bus.
Claims (10)
1, a kind of SPI4 Phase II bus that realizes is supported the device of multichannel physical equipment, it is characterized in that this device comprises:
The low speed bus interface module comprises an above low speed bus input interface, an above low speed bus output interface, and this module is used to connect the physical equipment more than a tunnel; The low speed bus input interface receives the 2.5Gbps bus data that every road physical equipment sends, and sends to the upstream data mapping block; The data that low speed bus output interface downlink data receiving mapping block sends are on the physical equipment that the 2.5Gbps bus more than a tunnel sends to this 2.5Gbps bus links to each other;
SPI4 Phase II interface module, comprise an above logical sub port, this module is used to receive the data that the upstream data mapping block sends, and data are sent on the SPI4 Phase II bus according to the logical sub port numbers, or receive SPI4 Phase II bus data, and send to the downlink data mapping block by the logical sub port;
The upstream data mapping block, it is used to receive the data that the low speed bus input interface sends, and number data is mapped on the logical sub port of SPI4 Phase II interface module one by one according to physical device number and low speed bus input interface;
The downlink data mapping block, it is used to receive the data that the SPI4 interface module sends, and according to the logical sub port numbers data is mapped on the fixing corresponding low speed bus output interface one by one;
The configuration bus interface module, the state that it is used to dispose and control SPI4 Phase II interface module, upstream data mapping block and reads the low speed bus interface module.
2, device as claimed in claim 1, it is characterized in that: described low speed bus interface module further comprises Date Conversion Unit, it will be converted to 64 bit wides from the 32 bit wide data that the 2.5Gbps bus receives, and to be combined into bit wide with control signal corresponding be 70 data, send into the upstream data mapping block, the address signal of each low speed bus input interface is lumped together send into the configuration bus interface module simultaneously;
Or go out 64 payload user data, control signal corresponding and address signal from the extracting data that the downlink data mapping block reads, corresponding control signal and data-signal are converted to the 2.5Gbps bus data that meets 32 bit wides, output to corresponding low speed bus output interface.
3, device as claimed in claim 2 is characterized in that, described upstream data mapping block further comprises:
First functional unit, it receives the data of 70 bit wides from the low speed bus input interface, from configuration bus interface module receiver address signal, and according to address signal 70 bit data is sent into corresponding synchronous first-in first-out buffer memory;
Synchronous first-in first-out buffer memory more than one after its data that functional unit one is sent are kept in, sends to second functional unit;
Second functional unit, it is according to first data of reading from each synchronous first-in first-out buffer memory simultaneously, state information with each synchronous first-in first-out buffer memory, selecting can be to sending data synchronization first-in first-out buffer memory outside, when more than one synchronous first-in first-out buffer memory can send data, the data that the address is minimum sent to asynchronous first-in first-out buffer memory;
Asynchronous first-in first-out buffer memory more than one after its data that second functional unit is sent are kept in, sends to the 3rd functional unit;
The 3rd functional unit, it reads asynchronous first-in first-out buffer memory, and the data that read out are outputed to SPI4 Phase II interface module by SPI4 PhaseII bus format.
4, device as claimed in claim 3, it is characterized in that: an output of described synchronous first-in first-out buffer memory sends flow-control information to first functional unit, first functional unit stops to send data to synchronous first-in first-out buffer memory according to this flow-control information, or continues to send data to synchronous first-in first-out buffer memory.
5, device as claimed in claim 3, it is characterized in that: an output of described asynchronous first-in first-out buffer memory sends flow-control information to two functional units, second functional unit stops to send data to asynchronous first-in first-out buffer memory according to this flow-control information, or continues to send data to asynchronous first-in first-out buffer memory.
6, device as claimed in claim 3, it is characterized in that: an output of SPI4 Phase II interface module sends flow-control information to the 3rd functional unit, the 3rd functional unit stops to send data to SPI4Phase II interface module according to this information, or continues to send data to SPI4 Phase II interface module.
7, device as claimed in claim 2, it is characterized in that, described downlink data mapping block further comprises asynchronous first-in first-out buffer memory more than, this asynchronous first-in first-out buffer memory is corresponding one by one with the low speed bus output interface, the data that receive from SPI4 Phase II interface module send to asynchronous first-in first-out buffer memory temporary after, re-send to the low speed bus output interface.
8, device as claimed in claim 1 is characterized in that: described low speed bus interface module is the SPI3 interface module.
9, device as claimed in claim 1 is characterized in that: described SPI4 Phase II interface mould is determined and is commercial SPI4 Phase II interface logic ip module.
10, device as claimed in claim 1 is characterized in that: this device is Programmable Logic Device or application-specific integrated circuit (ASIC).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02158017 CN1264315C (en) | 2002-12-20 | 2002-12-20 | Apparatus for realizing SPI4 Phase II bus support multi path physical device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02158017 CN1264315C (en) | 2002-12-20 | 2002-12-20 | Apparatus for realizing SPI4 Phase II bus support multi path physical device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1509024A true CN1509024A (en) | 2004-06-30 |
| CN1264315C CN1264315C (en) | 2006-07-12 |
Family
ID=34236816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02158017 Expired - Fee Related CN1264315C (en) | 2002-12-20 | 2002-12-20 | Apparatus for realizing SPI4 Phase II bus support multi path physical device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1264315C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101247234B (en) * | 2008-03-18 | 2010-09-08 | 中兴通讯股份有限公司 | Network processing card and operation method thereof |
| CN101287016B (en) * | 2008-05-28 | 2010-12-22 | 杭州华三通信技术有限公司 | Inter-connecting method and system between Ethernet interface and SPI-4 |
| CN101552733B (en) * | 2009-05-15 | 2011-07-20 | 华为终端有限公司 | Data transmission realizing method and system based on SPI |
| CN103559161A (en) * | 2013-09-24 | 2014-02-05 | 北京时代民芯科技有限公司 | Bus multi-width switching circuit for configuration of field programmable gate array (FPGA) |
-
2002
- 2002-12-20 CN CN 02158017 patent/CN1264315C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101247234B (en) * | 2008-03-18 | 2010-09-08 | 中兴通讯股份有限公司 | Network processing card and operation method thereof |
| CN101287016B (en) * | 2008-05-28 | 2010-12-22 | 杭州华三通信技术有限公司 | Inter-connecting method and system between Ethernet interface and SPI-4 |
| CN101552733B (en) * | 2009-05-15 | 2011-07-20 | 华为终端有限公司 | Data transmission realizing method and system based on SPI |
| CN103559161A (en) * | 2013-09-24 | 2014-02-05 | 北京时代民芯科技有限公司 | Bus multi-width switching circuit for configuration of field programmable gate array (FPGA) |
| CN103559161B (en) * | 2013-09-24 | 2016-02-10 | 北京时代民芯科技有限公司 | A kind of bus many width change-over circuit for FPGA configuration |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1264315C (en) | 2006-07-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101252537B (en) | Switching network communicating system, method and master control board | |
| CN109194679B (en) | Multi-protocol interface data acquisition device and acquisition method based on SpaceFibre interface | |
| EP0596645A1 (en) | Frame-based transmission of data | |
| CN1575560A (en) | Method and apparaturs for translating sdh/sonet frames to Ethernet frames | |
| CN101039148A (en) | Optical module and method and network equipment for supporting GE optical connector and FE optical connector | |
| US20070242676A1 (en) | Interface between a synchronous network and high-speed ethernet | |
| US7164860B1 (en) | Advanced multi-protocol optical transport network | |
| WO2011009402A1 (en) | Universal service transport transitional encoding | |
| CN1832474A (en) | Variable communication capacity data transmission device and data transmission device | |
| US7099584B1 (en) | Advanced error correcting optical transport network | |
| CN101277196A (en) | Communication system, communication method and cable fastener plate based on PCIE switching network | |
| CN101035143B (en) | Physical layer chip, method for transferring the signal and switcher | |
| US7031324B1 (en) | Local area network/wide area network switch | |
| CN100568841C (en) | A kind of converging device of Ethernet service and method | |
| CN1747606B (en) | Service data transmission method and apparatus thereof | |
| JPH07321842A (en) | Apparatus for interfacing packet switching network to plurality of data terminals,module for interfacing plurality of end points to system that switches frame relay packet,and method for interfacing terminal to system that switches data packet | |
| CN1728629A (en) | Transmission set of multiplexing multiplepath interface in physical layer | |
| CN1905558A (en) | Individualized ethernet exchange plate and data exchanging method | |
| CN100518140C (en) | SPI4II interface remote transmission realizing method and apparatus | |
| US7787502B1 (en) | Port multiplexing apparatus and methods | |
| CN1264315C (en) | Apparatus for realizing SPI4 Phase II bus support multi path physical device | |
| WO2003019873A1 (en) | Methods and systems for improving utilization of high-speed time division multiplexed communications links at signal transfer point | |
| CN101030844A (en) | Fiber-optic channel service duplexer, data transmitting system and method | |
| CN1980187A (en) | Network-unit apparatus management information transmission method and apparatus and network-unit apparatus | |
| CN102377482B (en) | A kind of fiber channel services fault transmission method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060712 Termination date: 20141220 |
|
| EXPY | Termination of patent right or utility model |