CN1507155A

CN1507155A - Digital potential converter and integrated circuit thereof

Info

Publication number: CN1507155A
Application number: CNA2003101006897A
Authority: CN
Inventors: 詹姆斯・R・朗勃格; 詹姆斯·R·朗勃格
Original assignee: INTELLIGENCE FIRST CO
Current assignee: INTELLIGENCE FIRST CO
Priority date: 2002-12-11
Filing date: 2003-10-13
Publication date: 2004-06-23
Anticipated expiration: 2023-10-13
Also published as: TW200410489A; CN1303761C; TWI238598B

Abstract

A digital level shifter for driving the input of a scaled P-channel driver device within a voltage shifted range to preclude gate-oxide breakdown of the scaled driver device. The scaled driver device has an output operative within an elevated voltage range, so that the voltage shifted range biases the voltage associated with a logic signal from a lower voltage level to an intermediate level to preclude gate-oxide breakdown and protect the scaled driver device. The digital level shifter is implemented using digital devices thereby avoiding analog bias devices. The digital level shifter and the scaled driver device may be implemented on the same integrated circuit (IC) and fabricated using the same process as core circuitry so that the IC may directly interface external devices operating at elevated voltage levels without damaging the core circuitry or the scaled driver device.

Description

Numeral electric potential transducer and integrated circuit thereof

Technical field

The present invention is relevant for voltage conversion circuit, especially refer to a digital electric potential transducer, for the driving element that is used for being coupled to the outer member that operates on high potential, can keep its gate oxide integrity, wherein this driving element is contracted to and can not bears high-tension input.

Background technology

The application's case is advocated the priority of following U. S. application case: application number is 10/317,241, and the applying date is on December 11st, 2002.

Along with integrated circuit (IC) design and process technique development for many years, operating voltage has the trend of down adjusting along with component size.Very lagre scale integrated circuit (VLSIC) (VLSI), particularly microprocessor dwindle (scaling) last to occuping leading at size and voltage.Therefore, the VLSI element that operates on low-voltage must be coupled to outer member by an interface, goes into (I/O) element and so on as output, and the degree of dwindling of this kind element is also so big not as the VLSI element.But the driving voltage of outer member is far above the core voltage of VLSI element, and therefore the many existing VLSI of dwindling elements provide voltage conversion circuit, to increase I/O signal voltage amplitude, makes it can successfully be coupled to high-tension outer member.

But in recent years, VLSI size of component and operating voltage be all toward descending, so that in some cases, for dwindling for the P pass element as the interface that is coupled to the high voltage outer member, if same high potential is used for driving its input, the collapse of grid oxic horizon then can take place.Because these P pass elements dwindle significantly, it is very thin that its grid oxic horizon becomes, so if its grid is in the minimum voltage (as 0 volt) of digital voltage scope, source electrode is connected to high voltage (as 3.3 volts) simultaneously, then source electrode is to grid voltage V _SG, passage is to grid voltage V _CGWith drain to grid voltage V _DG, can be called V above the breakdown voltage of grid oxic horizon all _BROX

Before this, voltage conversion circuit all is very simple, because it need to improve the current potential (as from 3.3 volts to 5 volts) of logical one, and the current potential of keeping logical zero is zero volt.Yet along with silicon cell dwindles constantly, existing current potential switch technology obviously becomes unfavorable.For example, the VLSI element is with 0.18 micron system manufacturing now, and therefore in a typical element, the thickness of grid oxic horizon is approximately 40 dusts.Those skilled in the art as can be known, silicon dioxide (SIO ₂) breakdown voltage be about 10 ⁷Volt/cm (V/CM), and be appropriate with gate-voltage limit in 60% of about collapse value.Therefore, for 0.18 micron element, a suitable collapse critical value V _BROXBe about 2.4 volts.0.18 the micron element generally operates on VDD=I.8 volt (with respect to 0 volt of ground connection), so its logical one is 1.8 volts and logical zero is 0 volt.Therefore, under the core current potential, do not have the problem of grid oxic horizon collapse.But these elements generally all must be coupled to outside CMOS (Complementary Metal Oxide Semiconductor) (CMOS) element that operates on high potential (as 3.3 volts).Consequently, 0.18 micron P passage output element is drawn high to 3.3 volts, and grid voltage is maintained 0 volt simultaneously, so damage the grid oxic horizon of P pass element most probably.So traditional voltage conversion circuit is impracticable in these cases.

The technology of newer adjustment output potential is to utilize two kinds of circuit of numeral and simulation, and the logical one that will be positioned at the core current potential is increased to the high potential of outer member, and logical zero is risen to an intermediate potential from 0 volt.This intermediate potential is low to being enough to conducting P pass element, and height is to the collapse that can prevent grid oxic horizon.The bias voltage that analog circuit then is used for producing logical zero so just can be set in logical zero on the relative 0 volt intermediate potential to digital circuit.Yet the analog element volume is big and power consumption is many, and is not suitable for the application of VLSI element.

Therefore, needed is to control the technology of dwindling P passage output driving element, and this kind element makes its grid oxic horizon too thin because the degree of dwindling is very big, can't bear as the input signal current potential as its required high output potential, and the collapse that is easy to produce grid oxic horizon.

Summary of the invention

The invention provides the embodiment of a digital electric potential transducer, it drives an input that dwindles driving element in a voltage conversion range, dwindles the collapse of driving element generation grid oxic horizon to avoid this.This dwindles driving element and has the output that operates on a high voltage range, is offset to an intermediate potential so this voltage conversion range is a associated voltage with a logical signal from one than electronegative potential, to keep the collapse critical value and to protect this to dwindle driving element.This numeral electric potential transducer is to do so that digital element is real, to avoid using the analog bias element.This numeral electric potential transducer and this dwindle driving element and can be embodied on the same integrated circuit (IC), and use identical process technique with core circuit, so that this IC can directly be coupled to the outer member that operates on high potential, and can not damage core circuit or dwindle driving element.

The embodiment of digital electric potential transducer provided by the present invention, it comprises a digital voltage limiter and a digital current potential change over switch.This digital voltage limiter is coupled to first and second voltage sources that have first and second current potentials respectively, to define first voltage range.This digital voltage limiter receives a digital input signals that operates in the first voltage range, and provide the voltage limit signal of a correspondence, it operates in the deboost scope between second current potential and an intermediate potential, and wherein this intermediate potential is between first and second current potentials.Choosing of this intermediate potential is in order to avoid importing overvoltage to dwindling driving element.This numeral current potential change over switch is coupled to the tertiary voltage source and first voltage source, and wherein the tertiary voltage source has the 3rd current potential that is higher than second current potential.This numeral current potential change over switch receives this voltage limit signal, and cooperates the switching of this voltage limit signal, in the voltage conversion range that intermediate potential and the 3rd current potential are defined, switches a voltage transitions digital signal accordingly.

The present invention also provides another embodiment of a digital electric potential transducer, and it comprises a digital potentiometer (digital voltage divider) and a digital current potential change over switch.This digital potentiometer includes the P pass element, is coupled between a reference voltage and first voltage source.This digital potentiometer receives the digital input signals in the voltage range that operates between the reference voltage and first voltage source, and has a contact, to form a voltage limit signal.This voltage limit signal operates on the deboost scope between first voltage source and an intermediate voltage, and has a current potential between between the reference voltage and first voltage source.This numeral current potential change over switch comprises with complementary configuration and is coupled to P passage and N pass element between the reference voltage and second voltage source.This second voltage source has the current potential that is higher than first voltage source.This digital switch has the input that is used for receiving this voltage limit signal, and the output that a conversion digital signal is provided, wherein the voltage conversion range of this conversion digital signal running between the intermediate voltage and second voltage source.

The present invention also provides the embodiment of an integrated circuit (IC), and it includes a core circuit, a digital electric potential transducer and dwindles driving element.This core circuit is coupled to a reference voltage and first voltage source, and produces first digital signal in the low voltage scope that operates on, and wherein this low voltage scope is defined by the reference voltage and first voltage source.This numeral electric potential transducer is coupled to the reference voltage and first voltage source, and is coupled to second voltage source.Second voltage source is higher than first voltage source.This numeral electric potential transducer receives first digital signal, and the conversion digital signal of an expression first digital signal is provided.This conversion digital signal operates between second voltage source and the intermediate voltage, and wherein this intermediate voltage is between between the reference voltage and first voltage source.This dwindles driving element and receives this conversion digital signal, and second digital signal of an expression first digital signal is provided.This second digital signal operates on a high voltage range that is defined by the reference voltage and second voltage source.This conversion digital signal operates on intermediate voltage, to prevent to dwindle the collapse of driving element generation oxide layer.

Technical scheme of the present invention is achieved in that

A kind of digital electric potential transducer is characterized in that, in order to driving an input that dwindles driving element, this dwindles driving element and has an output that operates on a high voltage range, and this numeral electric potential transducer comprises:

One digital voltage limiter, be coupled to one first and one second voltage source that has first and second current potentials respectively, to define a first voltage range, this second current potential is higher than this first current potential, this digital voltage limiter reception one operates in the digital input signals of this first voltage range, and provide the voltage limit signal of a correspondence, in the deboost scope of this voltage limit signal operation between this second current potential and an intermediate potential, wherein this intermediate potential is between this first and second current potential; And

One digital current potential change over switch, be coupled to a tertiary voltage source and this first voltage source, wherein this tertiary voltage source has one the 3rd current potential that is higher than this second current potential, this numeral current potential change over switch receives this voltage limit signal, and cooperate the switching of this voltage limit signal, in the voltage conversion range that this intermediate potential and the 3rd current potential are defined, switch a voltage transitions digital signal accordingly;

Wherein choosing of this intermediate potential collapsed in order to avoid this grid oxic horizon that dwindles driving element.

This digital voltage limiter comprises a digital potentiometer, and this digital potentiometer has the input of this digital input signals of reception, and the contact of this voltage limit signal of formation.

This numeral current potential change over switch comprises:

One P channel circuit is coupled between this tertiary voltage source and at least one bias voltage node, and this P channel circuit is coupled to this contact, receiving this voltage limit signal, and cooperates the switching of this voltage limit signal, switches this voltage transitions digital signal; And

One N channel circuit, be coupled to this first and second voltage source, and be coupled on this at least one bias voltage node with a complementary configuration and this P channel circuit, this N channel circuit receives this digital input signals, and makes this P channel circuit be easy to switch this voltage transitions digital signal.

This digital voltage limiter comprises:

One the one P pass element has a grid receiving this digital input signals, and has one source pole and a drain electrode is coupled between this second voltage source and the contact; And

One the 2nd P pass element has one source pole and is coupled to this contact, and a drain electrode is coupled to this first voltage source, and a grid receives this digital input signals;

Wherein the size of the 2nd P pass element is to decide with respect to a P pass element, is lower than this intermediate potential with the size of avoiding this voltage limit signal.

The size of the 2nd P pass element is greater than a P pass element so that when this digital input signals when this first current potential switches, the 2nd P pass element begins to close.

Also comprise:

One the 3rd P pass element has a grid, and has one source pole and drain electrode is coupled between this second voltage source and this contact; And

One inverter has an input that receives this digital input signals, and is coupled to an output of this grid of the 3rd P pass element;

Wherein the 3rd P pass element is pulled to this second current potential with this contact when conducting.

This numeral current potential change over switch comprises:

First, second and the 3rd P pass element, each P pass element has N type well, is coupled to this tertiary voltage source, and each P pass element has one source pole, a drain electrode and a grid;

The source electrode of the one P pass element is coupled to this tertiary voltage source, its drain electrode then is coupled to an output node, this output node is coupled to the source electrode of the 2nd P pass element and the grid of the 3rd P pass element, and wherein this output node forms this voltage transitions digital signal;

The drain electrode of the 2nd P pass element is coupled to this first voltage source, and its grid then is coupled to this contact that this voltage limit signal is provided;

The source electrode of the 3rd P pass element is coupled to this tertiary voltage source, and its drain electrode then is coupled to the grid of a P pass element; And

One the one N pass element, its source electrode is coupled to this contact, and its drain electrode is coupled to the drain electrode of a P pass element, and its grid then is coupled to the grid of a P pass element.

This numeral current potential change over switch also comprises:

One the 2nd N pass element has one source pole, a drain electrode is coupled to the drain electrode of the 2nd P pass element, and a grid is coupled to this second voltage source;

One the 3rd N pass element has one source pole and is coupled to this first voltage source, and a drain electrode is coupled to the source electrode of the 2nd N pass element, and a grid is in order to receive an anti-phase digital input signals; And

One inverter has an input that receives this digital input signals, and an output that this rp input signal is provided.

The present invention also provides a kind of digital electric potential transducer, it is characterized in that including:

One digital potentiometer, comprise a plurality of P pass elements, be coupled between a reference voltage and one first voltage source, this digital potentiometer receives the digital input signals in the first voltage range that operates between this reference voltage and this first voltage source, and has a contact, to form a voltage limit signal, this voltage limit signal operates on the deboost scope between this first voltage source and an intermediate voltage, and this intermediate voltage has a current potential between between this reference voltage and this first voltage source; And

One digital current potential change over switch, comprise and a plurality ofly be coupled to P passage and N pass element between this reference voltage and one second voltage source with a complementary configuration, this second voltage source has the current potential that is higher than first voltage source, this digital switch has an input that is used for receiving this voltage limit signal, and the output that a conversion digital signal is provided, the voltage conversion range of this conversion digital signal running between this intermediate voltage and this second voltage source.

This digital potentiometer comprises:

One the one P channel transistor, have a grid with receive this digital input signals, one source pole is coupled to this first voltage source, and a drain electrode is coupled to one first contact;

One the 2nd P channel transistor has that one source pole is coupled to this first contact, a drain electrode is coupled to this reference voltage, and a grid is to receive this digital input signals;

One inverter has an input receiving this digital input signals, and an output to be to provide a rp input signal, and wherein this digital input signals and this rp input signal all operate in this first voltage range;

One the 3rd P channel transistor, have a grid with receive this rp input signal, one source pole is coupled to this first voltage source, and a drain electrode is coupled to one second contact;

One the 4th P channel transistor has that one source pole is coupled to this second contact, a drain electrode is coupled to this second voltage source, and a grid is to receive this digital input signals;

Wherein the size of this second and the 4th P channel transistor is decided with respect to this first and second P channel transistor respectively, so that the voltage limit signal of a pair of complementation forms respectively at this first and second contact, and all operates in this deboost scope;

One the 5th P channel transistor has that one source pole is coupled to this first voltage source, a drain electrode is coupled to this first contact, and a grid is to receive this rp input signal; And

One the 6th P channel transistor has that one source pole is coupled to this first voltage source, a drain electrode is coupled to this second contact, and a grid is to receive this digital input signals.

This numeral current potential change over switch comprises:

One the 7th P channel transistor has a grid and is coupled to this first contact, and has an one source pole and a drain electrode;

One the 8th P channel transistor has that one source pole is coupled to this second voltage source, a drain electrode is coupled to the source electrode of the 8th P channel transistor and a grid;

One the 9th P channel transistor has that one source pole is coupled to this tertiary voltage source, a drain electrode is coupled to the grid of the 8th P channel transistor, and a grid is coupled to the drain electrode of the 8th P channel transistor;

The tenth a P channel transistor has a grid and is coupled to the drain electrode that this second contact, one source pole are coupled to the 9th P channel transistor, and a drain electrode;

One the one N channel transistor has one source pole and is coupled to this reference voltage, a grid receiving this rp input signal, and a drain electrode;

One the 2nd N channel transistor has drain electrode, the grid that one source pole is coupled to a N channel transistor and be coupled to this first voltage source, and a drain electrode is coupled to the drain electrode of the 7th P channel transistor;

One the 3rd N channel transistor has one source pole and is coupled to the grid that this first contact, a grid are coupled to the 8th P channel transistor, and a drain electrode is coupled to the drain electrode of the 8th P channel transistor;

One the 4th N channel transistor has one source pole and is coupled to this reference voltage, a grid receiving this digital input signals, and a drain electrode;

One the 5th N channel transistor has drain electrode, the grid that one source pole is coupled to the 4th N channel transistor and be coupled to this first voltage source, and a drain electrode is coupled to the drain electrode of the tenth P channel transistor; And

One the 6th N channel transistor has one source pole and is coupled to the grid that this second contact, a grid are coupled to the 9th P channel transistor, and a drain electrode is coupled to the drain electrode of the 9th P channel transistor;

Wherein the digital output signal of a pair of complementation is formed at the grid of the 8th and the 9th P channel transistor, and all operates on this voltage conversion range.

This first, second, third, fourth, the 5th and the 6th P channel transistor all has the N type well that is coupled to this first voltage source, and the 7th, the 8th, the 9th and the tenth P channel transistor all has the N type well that is coupled to this second voltage source.

This second and the 5th N channel transistor maintains conducting state under normal operation, to share the load of this first and the 4th N channel transistor respectively.

The the 3rd and the 6th N channel transistor operates in other linear zone under normal operation, and inoperation is in the saturation region.

The present invention also provides a kind of integrated circuit, includes:

One core circuit is coupled to a reference voltage and one first voltage source, operates on one first digital signal in the low voltage scope in order to generation, and wherein this low voltage scope is defined by this reference voltage and this first voltage source;

One digital electric potential transducer, be coupled to this reference voltage and this first voltage source, and be coupled to one second voltage source, this second voltage source is higher than this first voltage source, this numeral electric potential transducer is in order to receive this first digital signal, and provide one the expression this first digital signal conversion digital signal, wherein this conversion digital signal operates between this second voltage source and the intermediate voltage, this intermediate voltage is between between this reference voltage and first voltage source; And

One dwindles driving element, in order to receive this conversion digital signal, and provide one the expression this first digital signal second digital signal, wherein this second digital signal operates on a high voltage range that is defined by this reference voltage and second voltage source, wherein this conversion digital signal operates on this intermediate voltage, dwindles the collapse of driving element generation oxide layer to prevent this.

This numeral electric potential transducer includes:

One digital voltage limiter is coupled to this reference voltage and first voltage source, cooperates the switching of this first digital signal, switches a voltage limit digital signal between this intermediate voltage and this reference voltage; And

One digital current potential change over switch is coupled to this digital voltage limiter, and is coupled to this reference voltage and second voltage source, cooperates the switching of this voltage limit digital signal, switches this conversion digital signal between this intermediate voltage and this reference voltage.

This digital voltage limiter includes:

A plurality of P channel transistors have the size of dwindling, and are coupled to a digital potentiometer, to receive this first digital signal and to have a contact so that this voltage limit digital signal to be provided; And

Wherein should include a plurality of P passages and N channel transistor by numeral current potential change over switch, be coupled to a complementary configuration, have the output that an input and that receives this voltage limit digital signal provides this conversion digital signal.

Description of drawings

Fig. 1 one comprises the simplification calcspar of the system of digital electric potential transfer circuit, and wherein this circuit is done according to one embodiment of the invention institute is real;

Fig. 2 is the simplification calcspar of an example embodiment of the electric potential transfer circuit of Fig. 1 of the present invention;

Fig. 3 is the detailed circuit diagram of another example embodiment of the electric potential transfer circuit of Fig. 1 of the present invention.

Wherein, description of reference numerals is as follows:

100 systems, 101 core circuits

103 digital electric potential transfer circuits 105 dwindle driving element

107 outer members, 109 IC

111 first voltage source pins, 113 second voltage source pins

115 tertiary voltage source pins

201 digital voltage limiters

203 digital current potential change over switch 205 P channel circuits

207 N channel circuits

301 inverters, 303 contacts

305 contacts, 307 first output nodes

309 complementary output nodes

Embodiment

Other features and advantages of the present invention, after the detailed description of consulting below in conjunction with accompanying drawing, can be clearer.

The following description provides under the train of thought of a specific embodiment and necessary condition thereof, can make those skilled in the art can utilize the present invention.Yet the various modifications that this preferred embodiment is done will be apparent to those skilled in the art, and, in this General Principle of discussing, and can be applied to other embodiment.Therefore, the present invention is not limited to this place and shows specific embodiment with narration, but has the maximum magnitude that the disclosed principle in place therewith conforms to novel feature.

This case the inventor notice, has to need to use to dwindle driving element, and it must have high output voltage, but can not allow high input voltage.Therefore, the inventor proposes a kind of digital electric potential transfer circuit, can drive in suitable potential to dwindle driving element, and to avoid its grid oxic horizon collapse, the part of following texts and pictures 1 to Fig. 3 is described.

Fig. 1 is the simplification calcspar that includes the system 100 of a digital electric potential transfer circuit 103, and wherein this digital electric potential transfer circuit 103 is to do according to a specific embodiment of the present invention is real.Herein " numeral " to be finger element operate in the mode of a similar switch, this switch has the operating point of a plurality of separation, each operating point is associated with different logic states and current potential.One core circuit 101 is via the first voltage source signal VDDL received power, and this first voltage source signal has with respect to a current potential or voltage common or reference voltage source signal REF, and reference voltage source signal REF and be sent to core circuit 101.One power source or voltage source (not shown) produce a source voltage between VDDL and REF.VDDL and REF determine first or the low voltage scope jointly, are convenient to provide power to the element in the core circuit 101.Core circuit 101 produces a logical signal or digital signal LDS at least, to offer the input of electric potential transfer circuit 103.The LDS signal has and is positioned at or near first logic state of the current potential of REF, and is positioned at or near second logic state of the current potential of VDDL.These logic states are commonly called logic one or " 1 " and logical zero or " 0 ".Positive logic or negative logic all can adopt herein, so any logic state 1 or 0 all may correspond to REF or VDDL.Electric potential transfer circuit 103 is coupled to VDDL and REF, and the digital circuit of power to inside can be provided, and the detecting with the logic state of activation LDS signal hereinafter can further specify.

Electric potential transfer circuit 103 sends a conversion logic or digital signal SDS, delivers to an input that dwindles driving element 105.Dwindle driving element 105 and be coupled to the second voltage source signal VDDH and REF between the two, and both have determined second or high voltage range these.Another power source or voltage source (not shown) produce a source voltage between VDDH and REF.The size of VDDH is than VDDL height, so second voltage range relevant with VDDH also is greater than the first voltage range relevant with VDDL.Usually voltage source V DDL and VDDH just are all, but the present invention then uses negative voltage source.Dwindle driving element 105 generation one logic output signals or digital output signal ODS and give at least one " outside " element 107 that also is coupled to VDDH and REF.The ODS signal operates on second voltage range, and this voltage range has first and second logic states 0 and 1, and its current potential separately is the current potential of VDDH or REF.Because positive logic or negative logic all can adopt, any logic state 1 or 0 all may correspond to REF or VDDH.Outer member 107 is to belong to " outside " for core circuit 101, and may be that the I/O element is gone in the output of arbitrary type, with the interface as core circuit 101.

In running, can wish the logical message of LDS signal that core circuit 101 is set, be sent to outer member 107.Yet outer member 107 is that the logical signal that utilizes current potential to be defined in the second voltage range VDDH-REF operates in design, and this high voltage range VDDH-REF is greater than first or low voltage scope VDDL-REF.Therefore, outer member 107 must be driven to the current potential that is higher than the LDS signal, so that logic is switched.By electric potential transfer circuit 103, the LDS signal is converted into the SDS signal, and wherein, the SDS signal operates in the voltage conversion range based on the VDDH current potential, and is applicable to and drives the input dwindle driving element 105.This voltage conversion range does not extend to whole high voltage range, so the SDS signal is still the voltage transitions signal of a numeral.VDDH is sent to electric potential transfer circuit 103, and electric potential transfer circuit 103 can be operated in this voltage conversion range.Dwindle the switching that driving element 105 cooperates the SDS signal, in whole high voltage range, switch the ODS signal, to drive the input of outer member 107.Therefore, electric potential transfer circuit 103 with dwindle driving element 105 and will operate with joint efforts in the LDS conversion of signals of low voltage scope (being applicable to core circuit 101) and become the ODS signal of running whole voltage range (being applicable to outer member 107).In this way, core circuit 101 can successfully be sent to logical message outer member 107.

Dwindle driving element 105 and include one or more and dwindle P pass element (not shown), with the required interface of the high potential that outer member 107 is provided.Yet if whole high potential scope is used to drive the input that these dwindle the P pass element, the collapse of grid oxic horizon may take place in it.Especially, dwindling driving element 105 may be with the ODS signal sets in the current potential near VDDH, but the SDS signal can not be pulled to the current potential of REF simultaneously, because can cause the grid oxic horizon collapse of inner P pass element 105 across the potential difference VDDH-REF that dwindles driving element 105.Electric potential transfer circuit 103 can switch the SDS signal at the voltage conversion range between between an intermediate potential (INT) and VDDH current potential.The size of INT current potential is higher than REF, and choosing of its value is the breakdown voltage that voltage conversion range VDDH-INT can not exceeded dwindle the P pass element in the driving element 105.More particularly, when SDS was driven to the INT current potential, the ODS signal can be driven to the current potential of VDDH, and needn't emit the danger that causes the grid oxic horizon collapse of dwindling P pass element in the driving element 105.

As previously mentioned, the progress of integrated circuit (IC) design and process technique makes operating voltage dwindle along with component size and down adjustment.VLSI circuit, particularly microprocessor dwindle one to occuping leading at size and voltage.Therefore, often need be at the VLSI element of low voltage running by an interface, the outer member so not big with the degree of dwindling couples.For example, core circuit 101 may be the VLSI element that is integrated into IC 109, and we wish and IC 109 directly can be couple to outer member 107.In one embodiment, electric potential transfer circuit 103 with dwindle driving element 105 and all be integrated into identical IC 109, as core circuit 101.Further, core circuit 101, electric potential transfer circuit 103 and dwindle driving element 105 and all use the identical circuit technology of dwindling to do in fact can make the N passage that constitutes these circuit all have the grid oxic horizon that quite approaches with the P pass element.In this way, IC 109 has comprised the source pin or the terminal of several outsides, in order to be coupled to other voltage source.For example, as shown in the figure, IC 109 includes the first voltage source pin 111 that is coupled to VDDL, is coupled to the second voltage source pin 113 of REF, and the tertiary voltage source pin 115 that is coupled to VDDH.In IC 109, VDDL is coupled to core circuit 101 and electric potential transfer circuit 103, and VDDH is coupled to electric potential transfer circuit 103 and dwindles driving element 105, and REF then is coupled to core circuit 101, electric potential transfer circuit 103 and dwindles driving element 105.

It should be noted that the present invention is not limited to aforesaid embodiment, promptly electric potential transfer circuit 103 is with real work of same process and the situation on same IC, as core circuit 101 with dwindling driving element 105.In fact, each circuit can separate real work, and can not break away from the spirit and scope of the present invention.But, with these circuit design or be manufactured on same the IC, tangible advantage is arranged, just as known to those skilled in the art with similar manufacturing technology.In addition, also can use two kinds of circuit of numeral and simulation, with the logic state transition of high voltage high potential to outer member 107, and with logic state transition to a high potential (as INT) of low voltage, to carry out the adjustment of output voltage.In this case, analog circuit is to be used to provide a logic bias voltage to give digital circuit.Therefore and be not suitable for the VLSI element yet the analog element size is big, and power hungry is big.Analog element directly is made on the IC 109, has just run counter to the purpose of VLSI, and, can exhaust the space and the power of valuable circuit board again if analog element is implemented into the IC outside.

One more specifically among the embodiment, IC 109 adopts the VLSI element that 0.18 micron system is made, and it comprises metal-oxide semiconductor (MOS) (MOS) element of the grid oxic horizon with about 40 dusts of thickness.For example, core circuit 101 may be a microprocessor, size and voltage need be done farthest and be dwindled.As previously mentioned, the grid oxic horizon breakdown voltage V of these elements _BROXBe approximately 2.4 volts.VDDL be generally 1.8 volts, and REF generally is 0 volt or ground connection for REF.To be lower than breakdown voltage a lot of since be used for the maximum potential of core circuit 101, just need not worry that oxide layer can not collapse.In this specific embodiment, outer member 107 comprises 3.3 volts cmos element, so when REF was 0 volt, VDDH was about 3.3 volts.And, dwindle the P pass element that driving element 105 comprises 0.18 micron, be used for being coupled to 3.3 volts outer member 107.Electric potential transfer circuit 103 operates between about 1.0 volts and 3.3 volts the SDS signal, and INT is about 1.0 volts.In this embodiment, voltage conversion range is about 2.3 volts.In the case, the grid that is integrated in the P pass element that dwindles driving element 105 of IC 109 can not reduced to about below 1 volt, so maximum voltage range is 2.3 volts.Since 2.3 volts are lower than breakdown voltage V _BROX(about 2.4 volts), the almost risk of collapsing with regard to the grid oxic horizon that does not have the P pass element.

Though it should be noted that it is herein, set forth the present invention dwindles the relevant issues of cmos element in order to processing solution with 0.18 micron element and related potential thereof.But identical scheme equally can be applicable to big and less element.This is because the phenomenon of grid oxic horizon collapse is not only relevant with the element manufacture process, and also with the application of element, promptly the voltage important document of the element element that will couple is closely related.Therefore, the present invention is not limited to 0.18 micron element and related potential thereof, and can be applicable to any real technology of making minification and voltage that has.And voltage source signal has different current potentials and polarity, to define any enforceable voltage range of a particular process.For example, REF can be converted to the current potential of non-zero, and the also and then conversion of other voltage source, to make desirable or suitable voltage range.Breakdown voltage is to decide according to processing procedure, application scenarios and relative current potential, dwindles the grid oxic horizon of driving element with protection.

In the aforementioned embodiment, electric potential transfer circuit 103 is to be embodied on the IC 109, and comprises Digital Logic, is fit to drive the conversion logic voltage range of dwindling driving element 105 inputs to provide one.In one embodiment, electric potential transfer circuit 103 comprises 0.18 micron element, and this 0.18 micron element has the grid oxic horizon of about 40 dusts of thickness, and operates on 1.8 volts core voltage source electric potential.Electric potential transfer circuit 103 is to be used for driving dwindling driving element 105, and the latter comprises that operating voltage is promoted to 0.18 micron P pass element of 3.3 volts.These P pass elements produce and are coupled to 3.3 volts of required logic current potentials of outer member 107, are lower than 2.4 volts so electric potential transfer circuit 103 can maintain the voltage range size that puts on the P pass element, to avoid the grid oxic horizon collapse.For example, in one embodiment, electric potential transfer circuit 103 restriction SDS signals avoid reducing to about below 1 volt, make that being across the maximum voltage that dwindles driving element 105 is 2.3 volts.

Fig. 2 is the simplification calcspar of an example embodiment of electric potential transfer circuit 103 of the present invention.In this example, electric potential transfer circuit 103 has two Main Stage, comprises a digital voltage limiter 201 and a digital current potential change over switch 203.Digital voltage limiter 201 is coupled to VDDL and REF, and receives the LDS signal.Digital voltage limiter 201 is in voltage range VDDL-REF, the switching of detecting LDS signal between height and low logic state, and cooperate the switching of LDS signal, the voltage limit signal VLS of a correspondence is switched to digital current potential change over switch 203, to transmit the logical message of LDS signal.Digital voltage limiter 201 can remain on the VLS signal in the one restricted voltage range, and promptly between the current potential of VDDL and INT, wherein the INT current potential is higher than REF.Particularly, a logic state (as logical one) of VLS signal is the current potential that is set in about VDDL, and other opposite logic state (as logical zero) then is set in the current potential of INT, perhaps with situation conversely.

Numeral current potential change over switch 203 comprises a P channel circuit 205, and it can receive the VLS signal with reference to VDDH, and sets the SDS signal.P channel circuit 205 responds the switching of VLS signals and switches the SDS signal, is passed to the logical message with the LDS signal and dwindles driving element 105.P channel circuit 205 can remain on the SDS signal in the voltage range between VDDH and intermediate potential INT.Particularly, a logic state (as logical one) of SDS signal is the current potential that is set in about VDDH, and other opposite logic state (as logical zero) then is set in the current potential of INT, and perhaps situation conversely.As previously mentioned, the INT current potential is to choose with respect to the current potential of VDDH, with the grid oxic horizon collapse of the P pass element of avoiding dwindling driving element 105.Therefore, the SDS signal can transmit the logical message from the LDS signal of core circuit 101, keeps the integrality of the grid that dwindles driving element 105 simultaneously.

In the embodiment shown in Figure 2, digital current potential change over switch 203 is to carry out configuration with a kind of complimentary fashion, and comprises a N channel circuit 207, and it is coupled to P channel circuit 205 via at least one bias voltage node 209.N channel circuit 207 couples and with reference to VDDL and REF, and bias voltage node 209 is maintained sufficiently high current potential, to prevent the elements collapse in the P channel circuit 205.N channel circuit 207 receives the LDS signal, and cooperates the switching of LDS signal to do switching, so that the switching of P channel circuit 205.Generally speaking, the mode Collaboration that N channel circuit 207 and P channel circuit 205 switch with complementation makes the SDS signal can come across whole voltage conversion range between VDDH and INT.

Fig. 3 is the detailed circuit diagram of another example embodiment of electric potential transfer circuit 103 of the present invention.The specific embodiment details of digital voltage limiter 201 and digital current potential change over switch 203 (containing P channel circuit 205 and N channel circuit 207) has further explanation in the drawings.Digital voltage limiter 201 comprises a P channel transistor P1-P6 and an inverter 301.Inverter 301 is in order to produce the LDSB signal, and it is the inversion signal of LDS signal.Being noted that, after B is attached to signal name herein, is negating on the presentation logic, and wherein anti-phase or complementary signal has opposite logic state.The N type well (N well) of P channel transistor P1-P6 is coupled to VDDL.The LDS signal is sent to the grid of P channel transistor P1, P3 and P6 and the input of inverter 301.The LDSB signal then is sent to the grid of P channel transistor P2, P4 and P5.The source electrode of P2, P3, P5 and P6 is coupled to VDDL.The drain electrode of the source electrode of P1 and P2 and P3 is coupled to a contact 303, to form voltage limit signal VLS.The drain electrode of P1 is coupled to REF, and this REF is ground connection or 0 volt in the embodiment of icon.In a similar fashion, the drain electrode of the source electrode of P4 and P5 and P6 is coupled to another contact 305, to form voltage limit signal VLSB.The drain electrode of P4 also is coupled to REF.Note that the VLSB signal is not the inversion signal of VLS signal, but because the running that circuit symmetry and inverter 301 response LDS signals switch is opposite logic state so generally suppose it.

Numeral current potential change over switch 203 comprises P channel transistor P7, P8, P9 and P10, and N channel transistor N1, N2, N3, N4, N5 and N6 (N1-N6).Configuration shown in the figure, P channel circuit 205 comprises transistor P7-P10, and N channel circuit 207 comprises transistor N1, N2, N4 and N5.VDDH is sent to the source electrode of P8 and P10.The drain electrode of P8 is coupled to the grid of P10, the source electrode of P7, the drain electrode of N3 and the grid of N6.The SDS output signal is formed at first output node 307 that is coupled to the P8 drain electrode.The grid of P7 and the source electrode of N3 are coupled to contact 301, to receive the VLS signal.In a similar fashion, the drain electrode of P10 is coupled to the output node 309 of a complementation, and it is coupled to the grid of P8, the source electrode of P9, the drain electrode of N6 and the grid of N3.One reversed-phase output signal SDSB is formed at output node 309.The grid of P9 and the source electrode of N6 are coupled to contact 303, to receive the VLSB signal.The N type well of P channel transistor P7-P10 all is coupled to VDDH.Though dwindle driving element 105 is to be coupled to the SDS signal in preamble, SDS and SDSB signal arbitrary or both all can drive the input that dwindles driving element, and these two output signals are all switched in the voltage conversion range intercropping of VDDH-INT, as hereinafter further as described in.

The drain electrode of P7 and the drain electrode of N2 are to be coupled to a Node B 1.The drain electrode of P9 and the drain electrode of N5 then are coupled to a Node B 2.Node B 1 and B2 reach the bias voltage node 209 of representative graph 2 altogether.The grid of N2 and N5 is coupled to VDDL.The source electrode of N2 is coupled to the drain electrode of N1, and the source electrode of N1 is coupled to REF.The source electrode of N5 couples the drain electrode of N4, and the source electrode of N4 is coupled to REF.The output of inverter 301 is coupled to the grid of N1, and receiving the VLSB signal, the VLS signal is then in order to the grid of driving N 4.

The size of P channel transistor P1 and P4 is respectively compared to P channel transistor P3 and P5 and Yan Shida.Because the relative size of this kind, P1 and P3 respectively with P4 and the P5 running of making a concerted effort, with as voltage divider.P1 and P4 can not pull down to earth terminal (0 volt), and this P channel transistor because of grounded drain can not pull down to 0 volt.When VLS and VLSB signal descended toward 0 volt, the matrix effect of P1 and P4 (body effect) and the electric current that P3 and P5 provided made a concerted effort to make P1 and P4 to begin to close in intermediate potential INT.In this way, VLS and VLSB signal can not drop to below the intermediate potential INT, and wherein the INT current potential is to be decided to the size of P4 to P1 and P5 by P3.With respect to the INT current potential of VDDL and REF current potential, then decide by the size of P1 and P4 (comparing with P1 and P3 respectively).For example, draw high INT, then need improve P3 to P1 and P5 to the size of P4, reduce INT, then reduce this size.The size of P3 and P1 should approximately be equal to the size of P5 and P4, operates in about identical voltage range, though the relative size ratio optionally can have difference with the VLSB signal to keep VLS.

In the running, when the LDS signal was pulled to REF, contact 303 was pulled to the INT current potential.The P3 conducting, P1 then is in faint conducting state, and the electric current that is provided by P3 is determined.The LDSB signal is pulled to VDDL, and P2, P4 and P5 are closed.The P6 conducting, and, the VLSB signal is pulled to the VDDL current potential as same element running of drawing high voltage.In a similar fashion, when the LDS signal was pulled to VDDL, P1, P3 and P6 were closed condition.Inverter 301 draws the LDSB signal toward earthing potential, makes P2 and P5 conducting, and P4 is then along with the conducting faintly by electric current that P5 provided.Therefore, the VLSB current potential is pulled to the INT current potential, and the VLS signal potential then is pulled to the VDDL current potential by P2.In this way, the switching of VLS signal and VLSB signal response LDS signal is switched in INT and VDDL intercropping.

When the LDS signal was electronegative potential, VLS was pulled to the current potential down to INT, and makes the P7 conducting.During the P7 conducting, the SDS signal can be dragged down, and make the P10 conducting.During the P10 conducting, the SDSB signal can be pulled to VDDH, and P8 is closed.When the SDSB signal was drawn high, the N3 conducting was so the SDS signal is reduced to the INT current potential of VLS by N3.Simultaneously, the LDSB signal is a high potential, and the VLSB signal drawn high the current potential to VDDL, and P9 is closed.

When the LDS signal was high potential, VLSB was pulled low to the INT current potential, and makes the P9 conducting.During the P9 conducting, the SDSB signal can be dragged down, and make the P8 conducting.During the P8 conducting, the SDS signal can be pulled to VDDH, and P10 is closed.When the SDS signal was drawn high, the N6 conducting was so the SDSB signal is reduced to the INT current potential of VLSB by N6.Simultaneously, the VLS signal is drawn high the current potential to VDDL, and P7 is closed.In this way, the switching between REF and VDDL current potential of SDS and SDSB signal response LDS and LDSB signal is switched between INT and VDDH current potential.In this complementary configuration, SDS and SDSB signal are switched to opposite logic states each other.In one embodiment, INT is near 1.0 volts, and VDDH is near 3.3 volts, so SDS and SDSB signal swing between 1 and 3.3 volt, the total voltage scope is 2.3 volts.

When the LDS signal is high potential, can make the N4 conducting; N4 is closed.Similarly, when the LDSB signal is high potential, can make the N1 conducting; N1 is closed.N2 and N5 maintain conducting state always, and one of them receives high draining to source voltage VDS by avoiding transistor N1 and N4, to protect N1 and N4 respectively.Under general normal operation, when the N1 conducting, N1 and N5 load sharing, and when the N4 conducting, N4 and N5 load sharing.When P8 conducting (and N1 closes), the combination of N1/N2 needs P7 is closed really.Otherwise, may have the electric current P7 that flows through, it may make the current potential of SDS signal can't reach the VDDH current potential.Similarly, when P10 conducting (and N4 closes), the combination of N4/N5 needs P9 is closed really, so that the SDSB signal reaches VDDH in fact.

When P8 was closed condition, N3 can assist to make the drain electrode of P8 to reduce to the INT current potential.Similarly, when P10 was closed condition, N6 can assist to make the drain electrode of P10 to reduce to the INT current potential.Because transistor N3 and N6 divide other running, SDS and SDSB signal do not reduce to that the INT current potential of setting is also low respectively than VLS and VLSB signal institute.For avoiding oxide layer collapse, under normal operation, N3 and N6 operate in the range of linearity (be VDS＜(VGS-VTH)) and non-saturated region, thus switch to high potential when its grid, its grid to channel voltage always at a safe current potential.As is known to the person skilled in the art, VTH is the critical potential of the grid of N channel transistor to source electrode.The grid of N3 and N6 is substantially INT current potential (as 1 volt), and this is (the fully formed) that is completed into because of its passage.Otherwise if allow N3 and N6 to operate in the saturation region, then its passage will be cut off, and grid is 0 volt, thereby exceed oxide layer collapse current potential.

Though the present invention describes in detail as above with reference to specific preferred embodiment, also might consider the embodiment of other variation.For example, in the aforesaid complementary configuration, also can implement a single output conversion element.And specific current potential and voltage range can be different according to component type or manufacture process.Though the related potential of 0.18 micron element is described in the embodiment of demonstration, and those skilled in the art also can recognize, the present invention can be applicable to less Yu the bigger element of relevant identical or different current potential.In addition, positive logic or negative logic also can be taken into account, and actual voltage value may be the plus or minus value.The invention relates to the associated voltage amount of conversion one any logical value, dwindle on the driving element to avoid excessive voltage to put on.

In addition, the phenomenon of the grid oxic horizon of general MOS type element collapse is not only relevant with the element manufacture process, also with the application of element, comprises that the voltage important document of the element that element will couple is closely related.For example,,, then also can comprise extra sandwich digit switch step, operate on the more outer member of high potential (as 5 volts) to be coupled to if utilize same process though the electric potential transfer circuit 103 in the previous embodiment comprises two stages.

In a word, the above only is preferred embodiment of the present invention, when can not with the scope implemented of qualification the present invention.All equalizations of doing according to claim of the present invention change and modify, and all should still belong in the scope that claims of the present invention contain.

Claims

1. a digital electric potential transducer is characterized in that, in order to driving an input that dwindles driving element, this dwindles driving element and has an output that operates on a high voltage range, and this numeral electric potential transducer comprises:

2. digital electric potential transducer as claimed in claim 1 is characterized in that, this digital voltage limiter comprises a digital potentiometer, and this digital potentiometer has the input of this digital input signals of reception, and the contact of this voltage limit signal of formation.

3. digital electric potential transducer as claimed in claim 2 is characterized in that, this numeral current potential change over switch comprises:

4. digital electric potential transducer as claimed in claim 1 is characterized in that, this digital voltage limiter comprises:

5. digital electric potential transducer as claimed in claim 4 is characterized in that, the size of the 2nd P pass element is greater than a P pass element so that when this digital input signals when this first current potential switches, the 2nd P pass element begins to close.

6. digital electric potential transducer as claimed in claim 4 is characterized in that also comprising:

7. digital electric potential transducer as claimed in claim 1 is characterized in that, this numeral current potential change over switch comprises:

8. digital electric potential transducer as claimed in claim 7 is characterized in that, this numeral current potential change over switch also comprises:

9. digital electric potential transducer is characterized in that including:

10. digital electric potential transducer as claimed in claim 9 is characterized in that, this digital potentiometer comprises:

11. digital electric potential transducer as claimed in claim 10 is characterized in that, this numeral current potential change over switch comprises:

12. digital electric potential transducer as claimed in claim 11, it is characterized in that, this the first, second, third, fourth, the 5th and the 6th P channel transistor all has the N type well that is coupled to this first voltage source, and the 7th, the 8th, the 9th and the tenth P channel transistor all has the N type well that is coupled to this second voltage source.

13. digital electric potential transducer as claimed in claim 11 is characterized in that, this second and the 5th N channel transistor maintains conducting state under normal operation, to share the load of this first and the 4th N channel transistor respectively.

14. digital electric potential transducer as claimed in claim 11 is characterized in that, the 3rd and the 6th N channel transistor operates in other linear zone under normal operation, and inoperation is in the saturation region.

15. an integrated circuit is characterized in that including:

16. integrated circuit as claimed in claim 15 is characterized in that, this numeral electric potential transducer includes:

17. integrated circuit as claimed in claim 16 is characterized in that, this digital voltage limiter includes: