CN1503365A

CN1503365A - Mask type ROM having diode and mfg method thereof

Info

Publication number: CN1503365A
Application number: CNA021527733A
Authority: CN
Inventors: 赖N志; 赖昇志; 龙翔澜; 陈逸舟
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2002-11-27
Filing date: 2002-11-27
Publication date: 2004-06-09
Anticipated expiration: 2022-11-27
Also published as: CN100345299C

Abstract

This invention provides a mask ROM containing a diode and its manufacturing method which defines logic 'O' or logic 'T' in terms of if there is a dielectric layer on the diode and can laminate multiple diode layers to form a high density volumetric tuple.

Description

The mask-type ROM and the manufacture method thereof that contain diode

Technical field

The present invention relates to a kind of mask-type ROM that contains diode, whether particularly a kind of the utilization has dielectric layer to define logic on the diode " 0 " or logic " 1 " mask-type ROM.

Background technology

Nonvolatile memory (nonvolatile memory) can be divided into two kinds.First kind is mask-type ROM (Mask ROM; Mask read only memory), be meant when making internal memory,, promptly to have defined logic just by sequencing (programmed) " 0 " and logical one, just can't rewrite again and gone out the back of factory.Therefore, Mask ROM can do test (testing), so reliability (reliability) is higher.Another kind is programmable internal memory (field programmable memory), is meant making the not sequencing of internal memory fashion, has gone out after the factory and can carry out sequencing according to user's demand.

Traditional Mask ROM is with metal oxide semiconductor transistor (MOS transistor; Metal-oxide-semiconductor transistor) as memory cell (memory unit).The mode of sequencing is to come the critical voltage of adjustment member MOS transistor (threshold voltage) by carrying out ion distribution, to define logic " 0 " and logic " 1 ".

In recent years, the existing Mask ROM of vertical-type PN diode that utilize as memory cell.For example, United States Patent (USP) the 5th, 441 promptly has in No. 907 to disclose the Mask ROM that this kind contains PN vertical-type diode, and its utilization has or not the PN diode to define logic " 0 ", " 1 ".

United States Patent (USP) the 6th, 185 then discloses a kind of internal memory of the PN of containing diode 122 B1 numbers, but it is not Mask ROM, but programmable ROM (OTP ROM once; One time programmableread only memory).In the internal memory that completes, on the PN diode, layer of oxide layer is arranged.Internal memory performed out factory after, define logic again " 0 ", " 1 ", the mode of definition is, oxide layer burnt (breakdown) with high voltage, has locating of burning to be decided to be " 1 ", locating of not burning is decided to be " 0 ".

When oxidated layer thickness is uneven, have problem during definition.

Summary of the invention

Technical problem to be solved by this invention is for providing a kind of mask-type ROM and manufacture method thereof that contains diode, whether it utilizes has dielectric layer to define logic on the diode " 0 " or logic " 1 ", but and the stacked multilayer diode layer, and form highdensity three-dimensional space array.

For achieving the above object, the invention provides provides a kind of mask-type ROM and manufacture method thereof that contains diode, and wherein the mask-type ROM of diode comprises:

The semiconductor substrate;

One insulating barrier was positioned on this semiconductor-based end;

Many first leads in that first direction is provided with are positioned on this insulating barrier;

A plurality of rectilinear diodes are positioned on this first lead;

A plurality of dielectric layers are positioned on the part diode, and the person is defined as logic to have the dielectric layer on the diode " 0 ", the person is defined as logic and do not have the dielectric layer on the diode " and 1 "; And

At many second leads that second direction is provided with, be positioned on this dielectric layer and this diode, this first and second direction is vertical.

According to a specific embodiment of the present invention, the mask-type ROM that the present invention contains diode comprises:

The semiconductor substrate;

One insulating barrier was positioned on this semiconductor-based end; And

At least two-layer memory cell layers is piled up and is arranged on this insulating barrier, and appoints between the two-layer memory cell layers and have a separate layer to insulate, and wherein this each layer memory cell layers comprises:

A plurality of rectilinear diodes are positioned on this first lead;

At many second leads that second direction is provided with, be positioned on this dielectric layer and this diode, this first and second direction is vertical,

Wherein any two adjacent two polar body layers up and down are to be provided with face-to-face with different conductivity types.

The quantity of said memory cells layer can be 2 to 10 layers.Separate layer can be silica.

According to another specific embodiment of the present invention, the mask-type ROM that the present invention contains diode comprises:

The semiconductor substrate;

One insulating barrier was positioned on this semiconductor-based end;

N layer diode layer piles up and is arranged on this insulating barrier, and n is equal to or greater than 2 integer, and every layer diode layer comprises: a plurality of rectilinear diodes; And a plurality of dielectric layers, be positioned on the part diode, the person is defined as logic to have the dielectric layer on the diode " 0 ", the person is defined as logic and do not have the dielectric layer on the diode " 1 "; And

(n+1) layer parallel electrically conductive layer lays respectively between orlop diode layer and the insulating barrier, and on the superiors' diode layer, and between the wantonly two adjacent diode layers, and the direction that is provided with of this (n+1) layer parallel electrically conductive layer is that wantonly two adjacent conductive layers are mutually perpendicular,

Wherein wantonly two adjacent two diode layers up and down are to be provided with face-to-face with conductivity type.

The quantity n of above-mentioned diode layer can be between 2 to 10.

The present invention also provides the manufacture method of the mask-type ROM that contains diode.According to a specific embodiment of the present invention, manufacture method can may further comprise the steps:

In the semiconductor substrate, form an insulating barrier in order, one first conductive layer, one second conductive layer and one the 3rd conductive layer wherein form PN interface or Schottky (Schottky) interface between second conductive layer and the 3rd conductive layer;

Patterning the 3rd conductive layer, second conductive layer and first conductive layer, and form a plurality of first grooves that are provided with at a first direction, first conductive layer is defined as multiple bit lines;

One first insulant is inserted in this first groove;

On the 3rd conductive layer and first insulant, form a dielectric layer comprehensively;

This dielectric layer of patterning, first insulant, the 3rd conductive layer, second conductive layer stops at bit line, and forms a plurality of second grooves that a second direction is provided with of complying with, and form a plurality of diodes that are made of second conductive layer and the 3rd conductive layer, wherein first direction and second direction are orthogonal;

Second insulant is inserted in this second groove, made this dielectric layer of aspect ratio of this second insulant be height, and form a plurality of the 3rd grooves that are provided with in second direction;

This dielectric layer of patterning exposing the 3rd conductive layer of part diode, and forms a plurality of codings opening, defines a plurality of code areas;

Form one the 4th conductive layer, use in the opening with coding to insert the 3rd groove, and form many character lines.

According to another specific embodiment of the present invention, the manufacture method that contains the mask-type ROM of diode can may further comprise the steps:

In the semiconductor substrate, form an insulating barrier in order, one first conductive layer, one second conductive layer, one the 3rd conductive layer and one first dielectric layer wherein form PN interface or Schottky (Schottky) interface between this second conductive layer and the 3rd conductive layer;

This first dielectric layer of patterning to expose the subregion of the 3rd conductive layer, is used opening and form a plurality of first codings, defines a plurality of first code areas;

This first dielectric layer of patterning, the 3rd conductive layer, second conductive layer and first conductive layer, and form a plurality of first grooves that a first direction is provided with of complying with, first conductive layer is defined as many first bit lines,

One first insulant is inserted in this first groove;

Form one the 4th conductive layer comprehensively, and insert this first coding with in the opening;

Form one the 5th conductive layer on the 4th conductive layer in order, the 6th conductive layer and one second dielectric layer wherein form PN interface or Schottky (Schottky) interface between the 5th conductive layer and the 6th conductive layer;

This second dielectric layer of patterning to expose the subregion of the 6th conductive layer, is used opening and form a plurality of second codings, defines a plurality of second code areas;

This second dielectric layer of patterning, the 6th conductive layer, the 5th conductive layer, the 4th conductive layer, first dielectric layer, the 3rd conductive layer, second conductive layer stops at first bit line, and forms a plurality of second grooves that a second direction is provided with of complying with, and the 4th conductive layer is defined as many first character lines, wherein first direction is vertical with second direction;

One second insulant is inserted in this second groove;

Form one the 7th conductive layer comprehensively, and insert this second coding with in the opening;

Form one the 8th conductive layer on the 7th conductive layer in order, one the 9th conductive layer and one the 3rd dielectric layer wherein form PN interface or Schottky (Schottky) interface between the 8th conductive layer and the 9th conductive layer;

Patterning the 3rd dielectric layer to expose the subregion of the 9th conductive layer, is used opening and form a plurality of the 3rd codings, defines a plurality of the 3rd code areas;

Patterning the 3rd dielectric layer, the 9th conductive layer, the 8th conductive layer, the 7th conductive layer, second dielectric layer, the 6th conductive layer, the 5th conductive layer, stop at first character line, and form a plurality of the 3rd grooves that are provided with according to first direction, and the 7th conductive layer is defined as many second bit lines;

One the 3rd insulant is inserted in the 3rd groove;

Patterning the 3rd dielectric layer, the 9th conductive layer, the 8th conductive layer stops at second bit line, and forms a plurality of the 4th grooves that are provided with according to second direction;

The 4th insulant is inserted in the 4th groove, made aspect ratio the 3rd dielectric layer of the 4th insulant be height, and form a plurality of the 5th grooves that are provided with according to second direction; And

The tenth conductive layer is inserted in the 5th groove, and is formed many second character lines,

Wherein the 3rd and the 5th conductive layer has same conductivity, and the 6th and the 8th conductive layer has same conductivity.

Embodiment

Fig. 1 a to Figure 11 shows the processing procedure generalized section that contains the mask-type ROM of diode according to a preferred embodiment of the present invention manufacturing.

See also Fig. 1 a, in semiconductor substrate 110, form an insulating barrier 112, one first conductive layer 120, one second conductive layers 122, the 3rd conductive layer 124 and one first shielding layers 130 in order.Insulating barrier 112 can be silica, aluminium oxide (Al _-2O ₃), silicon nitride (Si ₃N ₄), tantalum oxide (Ta ₂O ₅), barium strontium titanate (BST), hafnium oxide (HfO ₂) or titanium oxide (TiO ₂).For example, insulating barrier 112 can be with chemical vapour deposition technique (CVD; Chemical vapor deposition) formed silica, thickness can be between 500 to 800nm.First conductive layer 120 can be the formed twin crystal silicon of CVD, perhaps can be the formed metal of sputtering method (sputtering), and thickness can be between 200 to 400nm.First shielding layer 130 can be with the formed silicon nitride of CVD method, and thickness can be 50 to 300nm.

Be to form PN interface or Schottky (Schottky) interface between second conductive layer 122 and the 3rd conductive layer 124.For example, second conductive layer 122 can be N type twin crystal silicon, and the formation method can be, with CVD method or electricity slurry assisted CVD method (PECVD; Plasma-enhanced CVD) deposit, then mix with arsenic (As), phosphorus (P) or other N type admixture again, thickness can be 100 to 600nm.The 3rd conductive layer 124 can be P type twin crystal silicon, and the formation method can be, and deposits with CVD method or PECVD method, then mixes with boron (B), gallium (Ga), indium (In) or other P type admixture again, and thickness can be 100 to 400nm.So, form the PN interface between second conductive layer 122 and the 3rd conductive layer 124.Perhaps, second conductive layer 122 can be P type twin crystal silicon, and the 3rd conductive layer 124 can be metal, forms the Schottky interface so therebetween.For convenience of description, second conductive layer 122 all is shown as N (table N type twin crystal silicon) in the drawings, and the 3rd conductive layer 124 all is shown as P (table P type twin crystal silicon) in the drawings.

Then, consult Fig. 1 b, form one first photoresistance PR11 on first shielding layer 130, its pattern is identical with the pattern of the bit line of desire formation in the future.

Then, consult Fig. 1 c, with the first photoresistance PR11 is mask, etching first shielding layer 130, the three conductive layers 124, the second conductive layers 122, with first conductive layer 120, stop at insulating barrier 112, and form a plurality of first groove G11 that a first direction A is provided with that comply with, first conductive layer 120 is defined as multiple bit lines BL.Engraving method can use reactive ion-etching (RIE; Reactive ionetching).

Then, consult Fig. 1 d, remove the first photoresistance PR11, again one first insulant 140 is inserted in the first groove G11.For example, use high density plasma enhanced chemical vapor deposition method (HDPCVD; High densityplasma CVD) forms silica 140 and inserting in the first groove G11.Then, for stopping layer, eat-back (etching back) with first shielding layer 130 for first insulant 140.

Then, consult Fig. 1 e, remove first shielding layer 130, on the 3rd conductive layer 124 and first insulant 140, form a dielectric layer 150 more comprehensively.Then, form one second shielding layer 132 more comprehensively.Dielectric layer 150 can be silica, aluminium oxide (Al _-2O ₃), silicon nitride (Si ₃N ₄), tantalum oxide (Ta ₂O ₅), barium strontium titanate (BST), hafnium oxide (HfO ₂) or titanium oxide (TiO ₂).For example, dielectric layer 150 can be the formed silica of CVD method.Second shielding layer 132 can be the formed silicon nitride of CVD method.

Then, consult Fig. 1 f, form one second photoresistance PR12 on second shielding layer 132, its pattern is identical with the pattern of the character line of desire formation in the future.

Then, consulting Fig. 1 g, is mask with the second photoresistance PR12, etching second shielding layer 132, dielectric layer 150, the first insulants 140, the three conductive layers 124, the second conductive layers 122, stop at bit line BL, and form a plurality of second groove G12 that are provided with according to the B direction, the B direction is for vertical with the A direction.Engraving method can use reactive ion-etching (RIE).So, the 3rd conductive layer 124 and second conductive layer 122 are divided into a plurality of diode D, are shown as the PN diode among the figure, the 3rd conductive layer 124 is P, and second conductive layer 122 is N.

Then, consult Fig. 1 h, remove the second photoresistance PR12, again second insulant 142 is inserted in the second groove G12.For example, can use HDPCVD method cvd silicon oxide 142 to insert in the second groove G12.Then,, eat-back for stopping layer with second shielding layer 132 for second insulant 142.

Then, consult Fig. 1 i, remove second shielding layer 132.So, remove second shielding layer 132 after, can stay a plurality of the 3rd groove G13 that are provided with according to the B direction, and make that the height of second insulant 142 can be than dielectric layer 150 for high.

Then, consult Fig. 1 j, form the 3rd photoresistance PR13,, expose and develop for the 3rd photoresistance PR13, and make the 3rd photoresistance PR13 have pattern again via read-only memory encoding mask (ROMcode mask) Ml.Opening portion on the read-only memory encoding mask M1 is read-only memory code area (ROMcode) 160.

Then, consulting Fig. 1 k, is mask with the 3rd photoresistance PR13, with dielectric layer 150 etchings at 160 places, code area, and exposes the 3rd conductive layer 124 of the code area 160 diode D of place, forms a plurality of codings with openings 162.Etching method can use the RIE method.

Then, consult Fig. 1 l, remove the 3rd photoresistance PR13, form one the 4th conductive layer, use in the opening 162 with coding to insert the 3rd groove G13, and then carry out cmp (CMP; Chemicalmechanical polishing) forms many character line WL.The formation of character line WL does not need to use mask, is to belong to automatic alignment so (self-aligned).So, finish the mask-type ROM that contains diode, it has one deck memory cell layers 10.To the structure that character line WL is constituted, constituted memory cell layers 10 by bit line BL, comprising: according to the multiple bit lines BL of A direction setting; A plurality of rectilinear diode D are positioned on the bit line BL; A plurality of dielectric layers 150 are positioned on the part diode D; And, be positioned on dielectric layer 150 and the diode D according to many character line WL that the B direction is provided with.Have dielectric layer to be defined as logic on the diode D " 0 ", and do not have dielectric layer to be defined as logic on the diode D " 1 ".

In addition, the present invention can also pile up several layers of memory cell layers 10, and forms the three-dimensional space array.For example, Fig. 2 shows the mask-type ROM contain diode D, has two-layer memory cell layers 10, separates with insulation with a separate layer 12 therebetween.This separate layer 12 can be silica, aluminium oxide (Al _-2O ₃), silicon nitride (Si ₃N ₄), tantalum oxide (Ta ₂O ₅), barium strontium titanate (BST), hafnium oxide (HfO ₂) or titanium oxide (TiO ₂).Similarly, have dielectric layer to be defined as logic on the diode D " 0 ", and do not have dielectric layer to be defined as logic on the diode D " 1 ".The identical person with the 1st figure of the 2nd number in the figure represents identical assembly.

Fig. 3 a to Fig. 3 p shows the processing procedure generalized section that contains the mask-type ROM of diode according to another preferred embodiment manufacturing of the present invention.

See also Fig. 3 a, in semiconductor substrate 210, form an insulating barrier 212, one first conductive layer 221, one second conductive layers 222, the 3rd conductive layer 223 and one first dielectric layers 241 in order.Insulating barrier 212 can be silica, aluminium oxide (Al _-2O ₃), silicon nitride (Si ₃N ₄), tantalum oxide (Ta ₂O ₅), barium strontium titanate (BST), hafnium oxide (HfO ₂) or titanium oxide (TiO ₂).For example, insulating barrier 212 can be with the formed silica of CVD method, and thickness can be between 500 to 800nm.First conductive layer 221 can be the formed twin crystal silicon of CVD, perhaps can be the formed metal of sputtering method, and thickness can be between 200 to 400nm.First dielectric layer 241 can be silica, aluminium oxide (Al _-2O ₃), silicon nitride (Si ₃N ₄), tantalum oxide (Ta ₂O ₅), barium strontium titanate (BST), hafnium oxide (HfO ₂) or titanium oxide (TiO ₂).For example, first dielectric layer 241 can be with the formed silica of CVD method, and thickness can be 10 to 300nm.

Be to form PN interface or Schottky (Schottky) interface between second conductive layer 222 and the 3rd conductive layer 223.For example, second conductive layer 222 can be N type twin crystal silicon, and the formation method can be, with CVD method or electricity slurry assisted CVD method (PECVD; Plasma-enhanced CVD) deposit, then mix with arsenic (As), phosphorus (P) or other N type admixture again, thickness can be 100 to 600nm.The 3rd conductive layer 223 can be P type twin crystal silicon, and the formation method can be, and deposits with CVD method or PECVD method, then mixes with boron (B), gallium (Ga), indium (In) or other P type admixture again, and thickness can be 100 to 400nm.So, form the PN interface between second conductive layer 222 and the 3rd conductive layer 223.Perhaps, second conductive layer 222 can be P type twin crystal silicon, and the 3rd conductive layer 223 can be metal, forms the Schottky interface so therebetween.For convenience of description, second conductive layer 222 all is shown as N (table N type twin crystal silicon) in the drawings, and the 3rd conductive layer 223 all is shown as P (table P type twin crystal silicon) in the drawings.

Consult Fig. 3 b, form the first photoresistance PR21,, expose and develop for the first photoresistance PR21, and make the first photoresistance PR21 have pattern again via the first read-only memory encoding mask (ROMcode mask) M21.Opening portion on the first read-only memory encoding mask M21 is read-only memory code area (ROM code) 250.

Then, consulting Fig. 3 c, is mask with the first photoresistance PR21, with first dielectric layer, 241 etchings at 250 places, code area, and exposes the 3rd conductive layer 223 at 250 places, code area, forms a plurality of codings with openings 251.Etching method can use the RIE method.

Then, still consult Fig. 3 c, remove the first photoresistance PR21, form first shielding layer 261, silicon nitride for example, and insert first coding with in the opening 251.Then, form the second photoresistance PR22, its pattern is identical with the bit line pattern of desire formation in the future.

Then, consulting Fig. 3 d, is mask with the second photoresistance PR22, carries out etching (for example RIE), with etching first shielding layer 261, first dielectric layer, 241, the three conductive layers, 223, the second conductive layers 222, with first conductive layer 221, stop at insulating barrier 212, and form a plurality of first groove G21 that are provided with according to the A direction, first conductive layer 221 is defined as many first bit line BL21.Then, one first insulant 271 is inserted in the first groove G21.For example, use the HDPCVD method to insert in the first groove G21 to form silica.Then,, eat-back for stopping layer with first shielding layer 261 for first insulant 271.

Then, consult Fig. 3 e, remove first shielding layer 261, then, form one the 4th conductive layer 224 comprehensively, and insert first coding with in the opening 251.Then, carry out CMP, to polish the 4th conductive layer 224.

Then, consult Fig. 3 f, on the 4th conductive layer 224, form one the 5th conductive layer 225, the 6th conductive layer 226 and one second dielectric layer 242 in order.Be to form PN interface or Schottky interface between the 5th and the 6th

conductive layer

225 and 226, and the conductivity type of the 5th conductive layer 225 and the 3rd conductive layer 224 must be identical.For example, show among the figure that second conductive layer 222 and the 6th conductive layer 226 all are N type twin crystal silicon, the 3rd conductive layer 223 and the 5th conductive layer 225 all are P type twin crystal silicon.Second dielectric layer 242 can be silica, aluminium oxide (Al _-2O ₃), silicon nitride (Si ₃N ₄), tantalum oxide (Ta ₂O ₅), barium strontium titanate (BST), hafnium oxide (HfO ₂) or titanium oxide (TiO ₂).

Then, still consult Fig. 3 f, form the 3rd photoresistance PR23,, expose and develop for the 3rd photoresistance PR23, and make the 3rd photoresistance PR23 have pattern again via the second read-only memory encoding mask (ROM code mask) M22.Opening portion on the second read-only memory encoding mask M22 is read-only memory code area (ROM code) 250.Show among the figure to align with the code area on the first read-only memory encoding mask M21 in the code area on the second read-only memory encoding mask M22, in addition, also can not need alignment, and do arrangement (random) arbitrarily.

Then, consulting Fig. 3 g, is mask with the 3rd photoresistance PR23, with second dielectric layer, 242 etchings at 250 places, code area, and exposes the 6th conductive layer 226 at 250 places, code area, forms a plurality of second codings with openings 252.Etching method can use the RIE method.

Then, still consult Fig. 3 g, remove the 3rd photoresistance PR23, form second shielding layer 262 (for example silicon nitride), and insert second coding with in the opening 252.Then, form the 4th photoresistance PR24, its pattern is identical with the character line pattern that will form in the future.

Then, consulting Fig. 3 h, is mask with the 4th photoresistance PR24, carry out etching (for example RIE), with etching second shielding layer 262, the second dielectric layers 242, the 6th conductive layer 226, the 5th conductive layer 225, the four conductive layers 224, the first dielectric layers 241, the 3rd conductive layer 223, with second conductive layer 222, stop at bit line BL21, and form a plurality of second groove G22 that are provided with by the B direction.So, the 4th conductive layer 224 is divided into many first character line WL21.Simultaneously, a plurality of ground floor diode D21 that constituted by second conductive layer 222 and the 3rd conductive layer 223 have also been formed.

Then, still consult Fig. 3 h, remove the 4th photoresistance PR24, then, one second insulant 272 is inserted in the second groove G22.For example, use the HDPCVD method to form silica 272 to insert in the second groove G22, again with second shielding layer 262 for stopping layer, eat-back silica 272.

Then, consult Fig. 3 i, remove second shielding layer 262, form one the 7th conductive layer 227 more comprehensively, and insert second coding with in the opening 252.Then, polish the 7th conductive layer 227 with the CMP method.

Then, consult Fig. 3 j, on the 7th conductive layer 227, form one the 8th conductive layer, 228, the nine conductive layers 229 and one the 3rd dielectric layer 243 in order.Be to form PN interface or Schottky interface between the 8th and the 9th

conductive layer

228 and 229, and the conductivity type of the 8th conductive layer 228 and the 6th conductive layer 226 must be identical.For example, show among the figure that the 6th conductive layer 226 and the 8th conductive layer 228 all are N type twin crystal silicon, the 9th conductive layer 229 is a P type twin crystal silicon.The 3rd dielectric layer 243 can be silica, aluminium oxide (Al _-2O ₃), silicon nitride (Si ₃N ₄), tantalum oxide (Ta ₂O ₅), barium strontium titanate (BST), hafnium oxide (HfO ₂) or titanium oxide (TiO ₂).

Then, still consult Fig. 3 j, form the 5th photoresistance PR25,, expose and develop for the 5th photoresistance PR25, and make the 5th photoresistance PR25 have pattern again via the 3rd read-only memory encoding mask (ROM code mask) M23.Opening portion on the 3rd read-only memory encoding mask M23 is read-only memory code area (ROM code) 250.Show among the figure to align with the code area on the first read-only memory encoding mask M21 in the code area on the 3rd read-only memory encoding mask M23, in addition, also can not need alignment, and do arrangement (random) arbitrarily.

Then, consulting Fig. 3 k, is mask with the 5th photoresistance PR25, with the 3rd dielectric layer 243 etchings at 250 places, code area, and exposes the 9th twin crystal silicon layer 229 at 250 places, code area, forms a plurality of the 3rd codings with openings 253.Etching method can use the RIE method.

Then, still consult Fig. 3 k, remove the 5th photoresistance PR25, form the 3rd shielding layer 263 (for example silicon nitride), and insert the 3rd coding with in the opening 253.Then, form the 6th photoresistance PR26, its pattern is identical with the bit line pattern of desire formation in the future.

Then, consulting Fig. 3 l, is mask with the 6th photoresistance PR26, carry out etching (as RIE), with etching the 3rd shielding layer 263, the three dielectric layers 243, the 9th conductive layer 229, the 8th conductive layer 228, the seven conductive layers 227, the second dielectric layers 242, the 6th conductive layer 226, with the 5th conductive layer 225, stop at the first character line WL21, and form a plurality of the 3rd groove G23 that are provided with according to the A direction.So, the 7th conductive layer 227 is divided into many second bit line BL22.Simultaneously, a plurality of second layer diode D22 that constituted by the 5th conductive layer 225 and the 6th conductive layer 226 have also been formed.

Then, still consult Figure 31, remove the 6th photoresistance PR26, one the 3rd insulant 273 is inserted in the 3rd groove G23.For example, use the HDPCVD method to form silica 273, to insert in the 3rd groove G23, again with the 3rd shielding layer 263 for stopping layer, eat-back silica 273.

Then, consult Fig. 3 m, remove the 3rd shielding layer 263, then, form one the 4th shielding layer 264 (for example silicon nitride) comprehensively.Then, form one the 7th photoresistance PR27, its pattern is identical with the pattern of the character line that desire forms.

Then, consulting Fig. 3 n, is mask with the 7th photoresistance PR27, carries out etching (for example RIE), with etching the 4th shielding layer 264, the three dielectric layers 243, the nine conductive layers 229, the 8th conductive layer 228 stops at the second bit line BL22, and forms a plurality of the 4th groove G24 that are provided with according to the B direction.So, a plurality of three-layer diode D23 that constituted by the 8th conductive layer 228 and the 9th conductive layer 229 have been formed.

Then, still consult Fig. 3 n, remove the 7th photoresistance PR27, the 4th insulant 274 is inserted in the 4th groove in the G24.For example, can use HDPCVD method cvd silicon oxide 274 to insert in the 4th groove G24.Then,, eat-back for stopping layer with the 4th shielding layer 264 for the 4th insulant 274.

Then, consult Fig. 3 p, remove the 4th shielding layer 264.So, remove the 4th shielding layer 264 after, can stay a plurality of the 5th groove G25 that are provided with according to the B direction, and make that the height of the 4th insulant 274 can be than the 3rd dielectric layer 243 for high.

Then, still consult Fig. 3 p, the tenth conductive layer is inserted in the 5th groove G25, form many second character line WL22 via the CMP grinding.So, finish the mask-type ROM that contains diode, it has three-layer diode D21, D22, and D23.Can find out that by 3p figure dielectric layer 241,242 is arranged on the PN diode, or 243 are defined as logic " 0 ", the person is defined as logic and do not have the dielectric layer on the PN diode " and 1 ".Moreover character line WL21 is shared by up and down two layer diode D21 and D22, bit line BL22 by about two layer diode D22 and D23 shared.

Fig. 4 shows that another contains the mask-type ROM of diode, and structure and the manufacture method of itself and Fig. 3 p are similar, but Fig. 4 only comprises two layer diode D21 and D22.Represent identical assembly with the identical person of Fig. 3 p label among Fig. 4.As seen from Figure 4, this mask-type ROM comprises semiconductor substrate 210; One insulating barrier 212 is positioned at at semiconductor-based the end 210; And two-layer PN diode layer, pile up and be arranged on the insulating barrier 212.Every layer of PN diode layer comprises: a plurality of rectilinear PN diodes, and a plurality of dielectric layer are positioned on the part PN diode.As shown in the figure, ground floor PN diode layer comprises: a plurality of rectilinear PN diode D21, and a plurality of dielectric layer 241 are positioned on the part PN diode D21.Second layer PN diode then comprises: a plurality of rectilinear PN diode D22, and a plurality of dielectric layer 242 are positioned on the part PN diode D22.Label 275,276,277 represent insulant.

Moreover, three layers of parallel electrically conductive layer are arranged among Fig. 4, be respectively bit line BL21, it is between the PN of lower floor diode layer D21 and insulating barrier 212; Character line WL21 is between two-layer PN diode layer; And bit line BL22, be positioned at upper strata PN diode D22 on.The direction that is provided with of bit line BL21 and BL22 is identical, and the direction that is provided with of character line WL21 then is vertical with bit line.Moreover two PN diode layers are to be provided with face-to-face with conductivity type up and down.For example, shown in Figure 4, the 3rd conductive layer 223 of following layer diode D21 and the 5th conductive layer 225 of last layer diode D22 are all the P type.The person is defined as logic to have the dielectric layer on the PN diode " 0 ", the person is defined as logic and do not have the dielectric layer on the PN diode " and 1 ".For example, as shown in FIG., have first dielectric layer to be defined as logic on the PN of the lower floor diode D21 " 0 ", and do not have first dielectric layer to be defined as logic on the PN diode D21 " 1 ".Have second dielectric layer to be defined as logic on the PN diode D22 of upper strata " 0 ", and do not have second dielectric layer to be defined as logic on the PN diode D22 " 1 ".Moreover character line WL21 is by two layer diode D21 and D22 are shared up and down.

Comprehensively above-mentioned, whether the mask-type ROM that the present invention contains diode is to utilize to have dielectric layer to define logic on the diode " 0 " or logic " 1 ", but and the stacked multilayer diode layer, and can form highdensity three-dimensional space array.

Though the present invention discloses as above with preferred embodiment; right its is not in order to restriction the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; change and retouching when doing, thus protection scope of the present invention when with accompanying claim the person of being defined be as the criterion.

For making purpose of the present invention, structural feature and function thereof are had further understanding, conjunction with figs. is described in detail as follows:

Description of drawings

Fig. 1 a to Fig. 1 l shows the schematic perspective view of processing procedure that contains the mask-type ROM of PN diode according to a preferred embodiment of the present invention manufacturing, and it comprises one deck PN diode layer.

Fig. 2 shows the schematic perspective view according to the mask-type ROM that contains the PN diode of a preferred embodiment of the present invention, and it comprises two-layer PN diode layer.

Fig. 3 a to Fig. 3 p shows the schematic perspective view of processing procedure that contains the mask-type ROM of PN diode according to another preferred embodiment manufacturing of the present invention, and it comprises three layers of PN diode layer.

Fig. 4 shows the schematic perspective view according to the mask-type ROM that contains the PN diode of another preferred embodiment of the present invention, and it comprises two-layer PN diode layer.

Wherein, description of reference numerals is as follows:

Among Fig. 1 a to Fig. 1 l and the 2nd figure, the semiconductor-based end of 110--, 112--insulating barrier, 120--first conductive layer, 122--second conductive layer, 124--the 3rd conductive layer, 130--first shielding layer, 132--second shielding layer, PR11--first photoresistance, PR12--second photoresistance, PR13--the 3rd photoresistance, G11--first groove, G12--second groove, G13--the 3rd groove, BL--bit line, 140--first insulant, 142--second insulant, 150--dielectric layer, the D--diode, M1--read-only memory encoding mask, 160--read-only memory code area, 162--coding opening, the WL--character line, the 10--memory cell layers, the 12--insulating barrier

Among Fig. 3 a to Fig. 3 p and the 4th figure, the semiconductor-based end of 210--, the 212--insulating barrier, 221--first conductive layer, 222--second conductive layer, 223--the 3rd conductive layer, 224--the 4th conductive layer, 225--the 5th conductive layer, 226--the 6th conductive layer, 227--the 7th conductive layer, 228--the 8th conductive layer, 229--the 9th conductive layer, 241--first dielectric layer, 242--second dielectric layer, 243--the 3rd dielectric layer, PR21--first photoresistance, PR22--second photoresistance, PR21--the 3rd photoresistance, PR21--the 4th photoresistance, PR25--the 5th photoresistance, PR26--the 6th photoresistance, PR27--the 7th photoresistance, the M21--first read-only memory encoding mask, the M22--second read-only memory encoding mask, M23--the 3rd read-only memory encoding mask, 250--read-only memory code area, the 251--first coding opening, the 252--second coding opening, 253--the 3rd coding opening, 261--first shielding layer, 262--second shielding layer, 263--the 3rd shielding layer, 264--the 4th shielding layer, G21--first groove, G22--second groove, G23--the 3rd groove, G24--the 4th groove, G25--the 5th groove, BL21--first bit line, BL22--second bit line, 271--first insulant, 272--second insulant, 273--the 3rd insulant, 274--the 4th insulant, 275,276, the 277--insulant, WL21--first character line, WL22--second character line, D21--ground floor PN diode, D22--second layer PN diode, the 3rd layer of PN diode of D23--.

Embodiment

Purpose of the present invention is for providing a kind of mask-type ROM and manufacture method thereof that contains diode, whether it is to utilize to have dielectric layer to define logic on the diode " 0 " or logic " 1 ", but and the stacked multilayer diode layer, and form highdensity three-dimensional space array.

For reaching purpose of the present invention, the mask-type ROM that the present invention contains diode comprises:

The semiconductor substrate;

One insulating barrier was positioned on this semiconductor-based end;

A plurality of rectilinear diodes are positioned on this first lead;

The semiconductor substrate;

One insulating barrier was positioned on this semiconductor-based end; And

At least two-layer memory cell layers is piled up and is arranged on this insulating barrier, and appoints between the two-layer memory cell layers and a separate layer is arranged to insulate, and wherein this each layer memory cell layers comprises:

A plurality of rectilinear diodes are positioned on this first lead;

Another specific embodiment according to the present invention, the mask-type ROM that the present invention contains diode comprises:

The semiconductor substrate;

One insulating barrier was positioned on this semiconductor-based end;

The quantity n of above-mentioned diode layer can be between 2 to 10.

One first insulant is inserted in this first groove;

Second insulant is inserted in this second groove, made this dielectric layer of aspect ratio of this second insulant be height, and form a plurality of the 3rd grooves that are provided with according to second direction;

One first insulant is inserted in this first groove;

One second insulant is inserted in this second groove;

One the 3rd insulant is inserted in the 3rd groove;

Embodiment

Fig. 1 a to Fig. 1 l shows the processing procedure generalized section that contains the mask-type ROM of diode according to a preferred embodiment of the present invention manufacturing.

Form PN interface or Schottky (Schottky) interface between second conductive layer 122 and the 3rd conductive layer 124.For example, second conductive layer 122 can be N type twin crystal silicon, and the formation method can be, with CVD method or electricity slurry assisted CVD method (PECVD; Plasma-enhanced CVD) deposit, then mix with arsenic (As), phosphorus (P) or other N type admixture again, thickness can be 100 to 600nm.The 3rd conductive layer 124 can be P type twin crystal silicon, and the formation method can be, and deposits with CVD method or PECVD method, then mixes with boron (B), gallium (Ga), indium (In) or other P type admixture again, and thickness can be 100 to 400nm.So, form the PN interface between second conductive layer 122 and the 3rd conductive layer 124.Perhaps, second conductive layer 122 can be P type twin crystal silicon, and the 3rd conductive layer 124 can be metal, forms the Schottky interface so therebetween.For convenience of description, second conductive layer 122 all is shown as N (table N type twin crystal silicon) in the drawings, and the 3rd conductive layer 124 all is shown as P (table P type twin crystal silicon) in the drawings.

Then, consult Fig. 1 j, form the 3rd photoresistance PR13,, expose and develop for the 3rd photoresistance PR13, and make the 3rd photoresistance PR13 have pattern again via read-only memory encoding mask (ROMcode mask) M1.Opening portion on the read-only memory encoding mask M1 is read-only memory code area (ROMcode) 160.

Then, consult Fig. 1 l, remove the 3rd photoresistance PR13, form one the 4th conductive layer, use in the opening 162 with coding to insert the 3rd groove G13, and then carry out cmp (CMP; Chemicalmechanical polishing) forms many character line WL.The formation of character line WL does not need to use mask, is to belong to automatic alignment so (self-aligned).So, finish the mask-type ROM that contains diode, it has one deck memory cell layers 10.To the structure that character line WL is constituted, constituted memory cell layers 10 by bit line BL, comprising: at the multiple bit lines BL of A direction setting; A plurality of rectilinear diode D are positioned on the bit line BL; A plurality of dielectric layers 150 are positioned on the part diode D; And, be positioned on dielectric layer 150 and the diode D at many character line WL that the B direction is provided with.Have dielectric layer to be defined as logic on the diode D " 0 ", and do not have dielectric layer to be defined as logic on the diode D " 1 ".

In addition, all right stacked multilayer memory cell layers 10 of the present invention, and form the three-dimensional space array.For example, the 2nd figure shows the mask-type ROM contain diode D, has two-layer memory cell layers 10, separates with insulation with a separate layer 12 therebetween.This separate layer 12 can be silica, aluminium oxide (Al _-2O ₃), silicon nitride (Si ₃N ₄), tantalum oxide (Ta ₂O ₅), barium strontium titanate (BST), hafnium oxide (HfO ₂) or titanium oxide (TiO ₂).Similarly, have dielectric layer to be defined as logic on the diode D " 0 ", and do not have dielectric layer to be defined as logic on the diode D " 1 ".The identical person with the 1st figure of the 2nd number in the figure represents identical assembly.

Fig. 3 a to Fig. 3 p shows that according to the present invention another preferred embodiment manufacturing contains the processing procedure generalized section of the mask-type ROM of diode.

Consult Fig. 3 b, form the first photoresistance PR21,, expose and develop for the first photoresistance PR21, and make the first photoresistance PR21 have pattern again through the first read-only memory encoding mask (ROM codemask) M21.Opening portion on the first read-only memory encoding mask M21 is read-only memory code area (ROMcode) 250.

Then, still consult Fig. 3 c, remove the first photoresistance PR21, form first shielding layer 261, silicon nitride for example, and insert first coding with in the opening 251.Then, form the second photoresistance PR22, its pattern is identical with the bit line pattern that forms in the future.

conductive layer

Then, still consult Fig. 3 g, remove the 3rd photoresistance PR23, form second shielding layer 262 (for example silicon nitride), and insert second coding with in the opening 252.Then, form the 4th photoresistance PR24, its pattern is identical with the character line pattern that forms in the future.

Then, consulting Fig. 3 h, is mask with the 4th photoresistance PR24, carry out etching (for example RIE), with etching second shielding layer 262, the second dielectric layers 242, the 6th conductive layer 226, the 5th conductive layer 225, the four conductive layers 224, the first dielectric layers 241, the 3rd conductive layer 223, with second conductive layer 222, stop at bit line BL21, and form a plurality of second groove G22 that are provided with according to the B direction.So, the 4th conductive layer 224 is divided into many first character line WL21.Simultaneously, a plurality of ground floor diode D21 that constituted by second conductive layer 222 and the 3rd conductive layer 223 have also been formed.

conductive layer

Then, still consult Fig. 3 k, remove the 5th photoresistance PR25, form the 3rd shielding layer 263 (for example silicon nitride), and insert the 3rd coding with in the opening 253.Then, form the 6th photoresistance PR26, its pattern is identical with the bit line pattern that forms in the future.

Then, consulting Figure 31, is mask with the 6th photoresistance PR26, carry out etching (as RIE), with etching the 3rd shielding layer 263, the three dielectric layers 243, the 9th conductive layer 229, the 8th conductive layer 228, the seven conductive layers 227, the second dielectric layers 242, the 6th conductive layer 226, with the 5th conductive layer 225, stop at the first character line WL21, and form a plurality of the 3rd groove G23 that are provided with according to the A direction.So, the 7th conductive layer 227 is divided into many second bit line BL22.Simultaneously, a plurality of second layer diode D22 that constituted by the 5th conductive layer 225 and the 6th conductive layer 226 have also been formed.

Fig. 4 shows that another contains the mask-type ROM of diode, and structure and the manufacture method of itself and 3p figure are similar, but the 4th figure only comprises two layer diode D21 and D22.Identical person with the 3p figure grade represents identical assembly among the 4th figure.Can find out that by the 4th figure this mask-type ROM comprises semiconductor substrate 210; One insulating barrier 212 is positioned at at semiconductor-based the end 210; And two-layer PN diode layer, pile up and be arranged on the insulating barrier 212.Every layer of PN diode layer comprises: a plurality of rectilinear PN diodes, and a plurality of dielectric layer are positioned on the part PN diode.As shown in the figure, ground floor PN diode layer comprises: a plurality of rectilinear PN diode D21, and a plurality of dielectric layer 241 are positioned on the part PN diode D21.Second layer PN diode then comprises: a plurality of rectilinear PN diode D22, and a plurality of dielectric layer 242 are positioned on the part PN diode D22.Label 275,276,277 represent insulant.

Moreover, three layers of parallel electrically conductive layer are arranged among Fig. 4, be respectively bit line BL21, it is between the PN of lower floor diode layer D21 and insulating barrier 212; Character line WL21 is between two-layer PN diode layer; And bit line BL22, be positioned at upper strata PN diode D22 on.The direction that is provided with of bit line BL21 and BL22 is identical, and the direction that is provided with of character line WL21 then is vertical with bit line.Moreover two PN diode layers are to be provided with face-to-face with conductivity type up and down.For example, shown in the 4th figure, the 3rd conductive layer 223 of following layer diode D21 and the 5th conductive layer 225 of last layer diode D22 are all the P type.The person is defined as logic to have the dielectric layer on the PN diode " 0 ", the person is defined as logic and do not have the dielectric layer on the PN diode " and 1 ".For example, as shown in FIG., have first dielectric layer to be defined as logic on the PN of the lower floor diode D21 " 0 ", and do not have first dielectric layer to be defined as logic on the PN diode D21 " 1 ".Have second dielectric layer to be defined as logic on the PN diode D22 of upper strata " 0 ", and do not have second dielectric layer to be defined as logic on the PN diode D22 " 1 ".Moreover character line WL21 is by two layer diode D21 and D22 are shared up and down.

Though the present invention discloses as above with preferred embodiment; right its is not in order to restriction the present invention, any those who are familiar with this art, without departing from the spirit and scope of the present invention; can do change and retouching, so protection scope of the present invention should the claimed scope of claims be as the criterion.

Claims

1. mask-type ROM that contains diode is characterized in that:

The semiconductor substrate;

One insulating barrier was positioned on this semiconductor-based end;

A plurality of rectilinear diodes are positioned on this first lead;

A plurality of dielectric layers are positioned on the part diode, have dielectric layer to be defined as logic on the diode " 0 ", the person is defined as logic and do not have the dielectric layer on the diode " and 1 "; And

According to many second leads that second direction is provided with, be positioned on this dielectric layer and this diode, this first and second direction is vertical.

2. as the 1st described mask-type ROM that contains diode of claim, wherein this diode is the PN diode.

3. as the 2nd described mask-type ROM that contains diode of claim, wherein this PN diode is constituted by two twin crystal silicon layers of different conductivity types.

4. as the 1st described mask-type ROM that contains diode of claim, wherein this insulating barrier is silica, aluminium oxide (Al _-2O ₃), silicon nitride (Si ₃N ₄), tantalum oxide (Ta ₂O ₅), barium strontium titanate (BST), hafnium oxide (HfO ₂) or titanium oxide (TiO ₂).

5. as the 1st described mask-type ROM that contains diode of claim, wherein this first lead and second lead are respectively bit line and character line.

6. as the 1st described mask-type ROM that contains diode of claim, wherein this dielectric layer is silica, aluminium oxide (Al _-2O ₃), silicon nitride (Si ₃N ₄), tantalum oxide (Ta ₂O ₅), barium strontium titanate (BST), hafnium oxide (HfO ₂) or titanium oxide (TiO ₂).

7. as the 1st described mask-type ROM that contains diode of claim, it comprises:

The semiconductor substrate;

One insulating barrier was positioned on this semiconductor-based end; And

Many first leads according to first direction is provided with are positioned on this insulating barrier;

A plurality of rectilinear diodes are positioned on this first lead;

According to many second leads that second direction is provided with, be positioned on this dielectric layer and this diode, this first and second direction is vertical,

Wherein wantonly two adjacent two polar body layers up and down are to be provided with face-to-face with different conductivity types.

8. as the 7th described mask-type ROM that contains diode of claim, it comprises 2 to 10 layers of memory cell layers.

9. as the 7th described mask-type ROM that contains diode of claim, wherein this separate layer is silica, aluminium oxide (Al _-2O ₃), silicon nitride (Si ₃N ₄), tantalum oxide (Ta ₂O ₅), barium strontium titanate (BST), hafnium oxide (HfO ₂) or titanium oxide (TiO ₂).

10. as the 1st described mask-type ROM that contains diode of claim, it comprises:

The semiconductor substrate;

One insulating barrier was positioned on this semiconductor-based end;

11. as the 10th described mask-type ROM that contains diode of claim, wherein n is between 2 to 10.

12. a manufacture method that contains the mask-type ROM of diode, it may further comprise the steps:

Patterning the 3rd conductive layer, second conductive layer and first conductive layer, and form a plurality of first grooves that a first direction is provided with of complying with, first conductive layer is defined as multiple bit lines;

One first insulant is inserted in this first groove;

13. as the 12nd described manufacture method that contains the mask-type ROM of diode of claim, wherein this diode is the PN diode.

14. as the 13rd described manufacture method that contains the mask-type ROM of diode of claim, wherein this PN diode is constituted by two twin crystal silicon layers of different conductivity types.

15. as the 12nd described mask-type ROM that contains diode of claim, wherein this dielectric layer is silica, aluminium oxide (Al _-2O ₃), silicon nitride (Si ₃N ₄), tantalum oxide (Ta ₂O ₅), barium strontium titanate (BST), hafnium oxide (HfO ₂) or titanium oxide (TiO ₂).

16. a manufacture method that contains the mask-type ROM of diode, it may further comprise the steps:

One first insulant is inserted in this first groove;

One second insulant is inserted in this second groove;

One the 3rd insulant is inserted in the 3rd groove;

17. as the 16th described manufacture method that contains the mask-type ROM of diode of claim, wherein this second, third, the twin crystal silicon layer of the 5th, the 6th, the 8th and the 9th conductive layer for mixing.

18. as the 17th described manufacture method that contains the mask-type ROM of diode of claim, wherein this second, the 6th and the 8th conductive layer has same conductivity, the 3rd, the 5th and the 9th conductive layer has same conductivity.

19. as the 16th described mask-type ROM that contains diode of claim, wherein this first, second and the 3rd dielectric layer be silica, aluminium oxide (Al _-2O ₃), silicon nitride (Si ₃N ₄), tantalum oxide (Ta ₂O ₅), barium strontium titanate (BST), hafnium oxide (HfO ₂) or titanium oxide (TiO ₂).