CN1499723A - Level converter unit of using base bias - Google Patents
Level converter unit of using base bias Download PDFInfo
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- CN1499723A CN1499723A CNA021500002A CN02150000A CN1499723A CN 1499723 A CN1499723 A CN 1499723A CN A021500002 A CNA021500002 A CN A021500002A CN 02150000 A CN02150000 A CN 02150000A CN 1499723 A CN1499723 A CN 1499723A
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Abstract
Level converter unit suitable to LCD made from thin film transistors includes a changeover circuit for converting an inputting voltage level to an output voltage level. The changeover circuit includes a first transistor, a second transistor, a first biasing circuit and a second biasing circuit. The first biasing circuit applicable to base bias of first transistor includes an input end and an output end. The second biasing circuit applicable to base bias of second transistor includes an input end and an output end. Output end of the first biasing circuit is connected to the base electrode of the first transistor. Output end of the second biasing circuit is connected to the base electrode of the second transistor. The biasing circuit provides bias for base electrode of transistor at input end and adjusts critical voltage of transistor at input end in order to reach targets of high speed, saving power and lowering input voltage.
Description
(1) technical field
The relevant a kind of level translator of the present invention, relevant specifically a kind of level translator that is used for Thin Film Transistor-LCD.
(2) background technology
Thin Film Transistor-LCD needs a kind of level translator, converts an input voltage to a higher output voltage, for each assembly of driving display.Owing to use thin-film transistor (TFT) processing procedure, its transistorized critical voltage value is greater than traditional complementary metal oxide semiconductors (CMOS) (CMOS) processing procedure, therefore testing circuit of needs detects the critical voltage of thin-film transistor, can't operate as normal to avoid the low excessively level translator that causes of input voltage.
Fig. 1 is a known level translator, and as shown in the figure, the basic framework of level translator comprises a change-over circuit 32, first testing circuit 27 and one second testing circuit 29.Change-over circuit 32 comprises a pair of input transistors (input transistor): the first transistor 2 and transistor seconds 4, and a pair of load transistor (load transistor): the 3rd transistor 6 and the 4th transistor 8.First testing circuit 27 comprises one the 5th transistor 10, a first input end 18 and one first current source 14.Second testing circuit 29 comprises one the 6th transistor 12, second input 20 and one second current source 16.The input signal of the first input end 18 and second input 20 is a pair of complementary signal.The 5th transistor 10 and the 6th transistor 12 are the critical voltages that are used for detecting the first transistor 2 and transistor seconds 4, guarantee that the first transistor 2 and transistor seconds 4 all operate in suitable operation interval, to finish the task of level conversion.
Fig. 2 is another known level translator, and basic framework is identical with Fig. 1 person, and difference is in the mode of connection of the grid of the 3rd transistor 6 and the 4th transistor 8.Fig. 3 is another known level translator, and basic framework is also identical with Fig. 1 person, and difference is in much more known one the 7th transistor 13 in Fig. 3, and by the 7th transistor 13, this kind level translator does not just need second input 20 still can work normally.
Because the data volume of required by electronic product processing now increases, the operating frequency of each inter-module also must and then improve, but the first transistor 2 in the above-mentioned known example and transistor seconds 4 all are in conducting state at any time, have had a strong impact on the speed of known level translator.Simultaneously, because the mode of connection of the 5th transistor 10 and the 6th transistor 12, make its function as diode, therefore known level translator have two DC path by current source (first current source 14 and second current source 16) after testing transistor (the 5th transistor 10 and the 6th transistor 12) to earth terminal, produce unnecessary electrical source consumption.
(3) summary of the invention
The objective of the invention is to provide a kind of level translator that is applied to high speed, the low-voltage input of Thin Film Transistor-LCD and reduces electrical source consumption for the shortcoming that overcomes known level translator.
Level translator of the present invention is to be used for Thin Film Transistor-LCD, is characterized in, comprise: a change-over circuit, in order to convert an input voltage level to an output-voltage levels, it comprises: a first transistor comprises one source pole, a drain electrode, a grid and a base stage; And a transistor seconds, comprise one source pole, a drain electrode, a grid and a base stage; One first bias circuit in order to this base bias to this first transistor, comprises an input and an output; And one second bias circuit, in order to this base bias, comprise an input and an output to this transistor seconds; Wherein, this output of this first bias circuit is connected in this base stage of this first transistor, and this output of this second bias circuit is connected in this base stage of this transistor seconds.
Level translator of the present invention is used for Thin Film Transistor-LCD, and it comprises a change-over circuit and two bias circuits.Change-over circuit has two input transistors and two load transistors, is used for converting incoming level to output level.Bias circuit has an input and an output, input is connected in the input of change-over circuit, output is connected in the base stage (body) of input transistors, can adjust the critical voltage of input transistors according to the height of incoming signal level, make under its situation that can work in environment at a high speed and low-voltage input.Because bias circuit is static logic circuit (static-logic circuit), also can reduce the direct current loss of this level translator simultaneously.
(4) description of drawings
Fig. 1 is the circuit diagram of a known example;
Fig. 2 is the circuit diagram of another known example;
Fig. 3 is the circuit diagram of another known example;
Fig. 4 is the circuit diagram of first embodiment of the invention;
Fig. 5 is the circuit diagram of second embodiment of the invention;
Fig. 6 is the circuit diagram of third embodiment of the invention.
(5) embodiment
The present invention is a kind of level translator, be to be used for Thin Film Transistor-LCD, one input voltage value can be converted to a higher output voltage values, it comprises one group of bias circuit, be used for input transistors is carried out bias voltage, use the critical voltage value of adjusting input transistors, make this kind level translator can work in the environment of low-voltage, high frequency, and save the direct current loss.
The critical voltage value of thin-film transistor (thin film transistor) can be represented by following formula:
Wherein, γ and Φ
fBe manufacture of semiconductor parameter, V
SBBe the voltage difference of source electrode (source) with base stage, V
Th0Be V
SBCritical voltage value during=0V, V
ThBe actual critical voltage value.Learn have dual mode can reduce the critical voltage of thin-film transistor from above formula, one is control manufacture of semiconductor parameter γ and Φ
f, a voltage difference V for control source electrode and base stage
SBYet, the critical voltage that will improve thin-film transistor from manufacture of semiconductor is unusual difficulty, therefore, the invention provides a kind of bias circuit, be used for the size of control TFT critical voltage value, its critical voltage value can be changed along with the change of input signal.
Level translator of the present invention comprises a change-over circuit, one first bias circuit and one second bias circuit.Change-over circuit is to be used for converting an input voltage level to an output-voltage levels, comprise two input transistors and two load transistors, input transistors is a n channel thin-film transistor (n-channelTFT), comprise one source pole, drain electrode (drain), a grid (gate) and a base stage, load transistor is p channel thin-film transistor (p-channel TFT), comprises one source pole, a drain electrode and a grid.First bias circuit and second bias circuit are used for respectively the base stage of two input transistors is carried out bias voltage, and its output is connected in the base stage of input transistors, to adjust the critical voltage value of input transistors.
Fig. 4 is the first embodiment of the present invention, as shown in the figure, change-over circuit 32 comprises the first transistor 2, transistor seconds 4, the 3rd transistor 6 and the 4th transistor 8, the input 34 of first bias circuit is connected in the grid of first input end 18 and the first transistor 2, output 36 is connected in the base stage of the first transistor 2, the input 38 of second bias circuit is connected in the grid of second input 20 and transistor seconds 4, output 40 is connected in the base stage of transistor seconds 4, the source ground of the first transistor 2 and transistor seconds 4, the drain electrode of the first transistor 2 is connected in the drain electrode of the 3rd transistor 6, the drain electrode of transistor seconds 4 is connected in the drain electrode of the 4th transistor 8, the grid of the 3rd transistor 6 is connected in the drain electrode of the 3rd transistor 6, the grid of the 4th transistor 8 is connected in the grid of the 3rd transistor 6, the source electrode of the 3rd transistor 6 and the 4th transistor 8 is connected in a power supply 30, the drain electrode of the 4th transistor 8 is first output 22, is used for exporting its output-voltage levels.Wherein, the input signal of the first input end 18 and second input 20 is complimentary to one another.
When the signal of first input end 18 is high levle (as 5V), when promptly the signal of second input 20 is low level (as 0V), signal is by first bias circuit 26 and second bias circuit 28, export the base stage of the first transistor 2 and transistor seconds 4 to, make the base voltage of the first transistor 2 improve and the base voltage reduction of transistor seconds 4.According to above-mentioned formula, the critical voltage of the first transistor 2 can descend (for example reducing to 2V) from 3.5V, the critical voltage of transistor seconds 4 can rise (for example rising to 3.5V) from 2V, therefore the grid voltage of the first transistor 2 is higher than the grid voltage subcritical voltage of critical voltage and transistor seconds 4, make the first transistor 2 conductings and transistor seconds 4 close, the function of change-over circuit 32 is just like an amplifier (amplifier) at this moment, and the output signal of first output 22 will be amplified the input signal (for example output signal is 12V) of its first input end 18.Opposite, when the signal of first input end 18 is a low level, when promptly the signal of second input 20 is high levle, the critical voltage of the first transistor 2 improves and the critical voltage of transistor seconds 4 reduces, make the first transistor 2 close and transistor seconds 4 conductings, this moment, the voltage of first output 22 was pulled to low level (identical with the signal of first input end 18).From the above, the input signal homophase of the output signal of first output 22 and first input end 18 and amplify a special ratios.
When the signal of first input end 18 was high levle, the base voltage of the first transistor 2 also was required to be high levle, and when the signal of first input end 18 was low level, the base voltage of the first transistor 2 also was required to be low level.Therefore, first bias circuit 26 can utilize a buffer (buffer) or two inverters (inverter) serial connection to finish.In like manner second bias circuit 28 also can be a buffer or two inverter serial connections as can be known.But the structure of bias circuit is not limited in above-mentioned two kinds, and any static logic circuit of reaching said function all can be suitable for.
Fig. 5 is the second embodiment of the present invention, its structure is roughly identical with the first embodiment of fig. 4, difference is in the drain electrode that is connected in the 4th transistor 8 in the grid of the 3rd transistor 6, and the grid of the 4th transistor 8 is connected in the drain electrode of the 3rd transistor 6, makes its circuit that second output 24 be arranged.Fig. 6 is the third embodiment of the present invention, its structure is roughly identical with first embodiment, unique difference is in the output 40 that all is connected in second bias circuit in the grid of transistor seconds 4 and base stage, and the input 38 of second bias circuit is connected to first input end 18, so connection does not just need second input 20, and this circuit is applicable to the device that a kind of input signal is only arranged.The signal condition of second embodiment and the 3rd embodiment and Operations Analyst and first embodiment are as good as, so do not give unnecessary details.
Level translator of the present invention is to utilize above-mentioned bias circuit to change the critical voltage of input transistors, its critical voltage can be adjusted to some extent along with the input signal height, therefore level translator of the present invention is not subjected to the restriction of low-voltage input, simultaneously because low-voltage means that the speed that signal level is switched can be faster, therefore also can work under the environment of high frequency, and because its bias circuit is a static logic circuit, so no direct current loss can be saved power supply.
Claims (12)
1. a level translator is to be used for Thin Film Transistor-LCD, it is characterized in that, comprises:
One change-over circuit in order to convert an input voltage level to an output-voltage levels, comprises:
One the first transistor comprises one source pole, a drain electrode, a grid and a base stage; And
One transistor seconds comprises one source pole, a drain electrode, a grid and a base stage;
One first bias circuit in order to this base bias to this first transistor, comprises an input and an output; And
One second bias circuit in order to this base bias to this transistor seconds, comprises an input and an output;
Wherein, this output of this first bias circuit is connected in this base stage of this first transistor, and this output of this second bias circuit is connected in this base stage of this transistor seconds.
2. level translator as claimed in claim 1 is characterized in that, this first transistor and this transistor seconds are a n channel thin-film transistor.
3. level translator as claimed in claim 2 is characterized in that, this change-over circuit comprises:
One first input end is in order to import this input voltage level;
One second input is in order to this input voltage level of input inversion;
One the 3rd transistor is to be a p channel thin-film transistor, comprises one source pole, a drain electrode and a grid; And
One the 4th transistor is to be a p channel thin-film transistor, comprises one source pole, a drain electrode and a grid;
Wherein, this input of this first bias circuit is connected in this grid of this first transistor, this input of this second bias circuit is connected in this grid of this transistor seconds, this source ground of this first transistor and this transistor seconds, this grid of this first transistor is connected in this first input end, this drain electrode of this first transistor is connected in the 3rd transistorized this drain electrode, this grid of this transistor seconds is connected in this second input, this drain electrode of this transistor seconds is connected in the 4th transistorized this drain electrode, the 3rd transistorized this grid is connected in the 3rd transistorized this drain electrode, the 4th transistorized this grid is connected in the 3rd transistorized this grid, the 3rd transistor and the 4th transistorized this source electrode are connected in a power supply, the 4th transistorized this output-voltage levels of output that should drain.
4. level translator as claimed in claim 2 is characterized in that, this change-over circuit comprises:
One first input end is in order to import this input voltage level;
One second input is in order to this input voltage level of input inversion;
One the 3rd transistor is to be a p channel thin-film transistor, comprises one source pole, a drain electrode and a grid; And
One the 4th transistor is to be a p channel thin-film transistor, comprises one source pole, a drain electrode and a grid;
Wherein, this input of this first bias circuit is connected in this grid of this first transistor, this input of this second bias circuit is connected in this grid of this transistor seconds, this source ground of this first transistor and this transistor seconds, this grid of this first transistor is connected in this first input end, this drain electrode of this first transistor is connected in the 3rd transistorized this drain electrode, this grid of this transistor seconds is connected in this second input, this drain electrode of this transistor seconds is connected in the 4th transistorized this drain electrode, the 3rd transistorized this grid is connected in the 4th transistorized this drain electrode, the 4th transistorized this grid is connected in the 3rd transistorized this drain electrode, the 3rd transistor and the 4th transistorized this source electrode are connected in a power supply, the 4th transistorized this output-voltage levels of output that should drain.
5. level translator as claimed in claim 2 is characterized in that, this change-over circuit comprises:
One input is in order to import this input voltage level;
One the 3rd transistor is to be a p channel thin-film transistor, comprises one source pole, a drain electrode and a grid; And
One the 4th transistor is to be a p channel thin-film transistor, comprises one source pole, a drain electrode and a grid;
Wherein, this input of this first bias circuit and this second bias circuit is connected in this grid of this first transistor, this source ground of this first transistor and this transistor seconds, this grid of this first transistor is connected in this input, this drain electrode of this first transistor is connected in the 3rd transistorized this drain electrode, this grid of this transistor seconds is connected in this base stage of this transistor seconds, this drain electrode of this transistor seconds is connected in the 4th transistorized this drain electrode, the 3rd transistorized this grid is connected in the 3rd transistorized this drain electrode, the 4th transistorized this grid is connected in the 3rd transistorized this grid, the 3rd transistor and the 4th transistorized this source electrode are connected in a power supply, the 4th transistorized this output-voltage levels of output that should drain.
6. as claim 3,4 or 5 described level translators, it is characterized in that this first bias circuit comprises an inverter.
7. as claim 3,4 or 5 described level translators, it is characterized in that this second bias circuit comprises an inverter.
8. a level translator is to be used for Thin Film Transistor-LCD, comprises:
One change-over circuit in order to convert an input voltage level to an output-voltage levels, comprises:
One first input end is in order to import this input voltage level;
One second input is in order to this input voltage level of input inversion;
One the first transistor is to be a n channel thin-film transistor, comprises one source pole, a drain electrode, a grid and a base stage;
One transistor seconds is to be a n channel thin-film transistor, comprises one source pole, a drain electrode, a grid and a base stage;
One the 3rd transistor is to be a p channel thin-film transistor, comprises one source pole, a drain electrode and a grid; And
One the 4th transistor is to be a p channel thin-film transistor, comprises one source pole, a drain electrode and a grid;
One first bias circuit in order to this base bias to this first transistor, comprises an input and an output; And
One second bias circuit in order to this base bias to this transistor seconds, comprises an input and an output;
Wherein, this input of this first bias circuit is connected in this grid of this first transistor, this input of this second bias circuit is connected in this grid of this transistor seconds, this output of this first bias circuit is connected in this base stage of this first transistor, this output of this second bias circuit is connected in this base stage of this transistor seconds, this grid of this first transistor is connected in this first input end, and this grid of this transistor seconds is connected in this second input.
9. level translator as claimed in claim 8, it is characterized in that, this source ground of this first transistor and this transistor seconds, this drain electrode of this first transistor is connected in the 3rd transistorized this drain electrode, this drain electrode of this transistor seconds is connected in the 4th transistorized this drain electrode, the 3rd transistorized this grid is connected in the 3rd transistorized this drain electrode, the 4th transistorized this grid is connected in the 3rd transistorized this grid, the 3rd transistor and the 4th transistorized this source electrode are connected in a power supply, the 4th transistorized this output-voltage levels of output that should drain.
10. level translator as claimed in claim 8, it is characterized in that, this source ground of this first transistor and this transistor seconds, this drain electrode of this first transistor is connected in the 3rd transistorized this drain electrode, this drain electrode of this transistor seconds is connected in the 4th transistorized this drain electrode, the 3rd transistorized this grid is connected in the 4th transistorized this drain electrode, the 4th transistorized this grid is connected in the 3rd transistorized this drain electrode, the 3rd transistor and the 4th transistorized this source electrode are connected in a power supply, the 4th transistorized this output-voltage levels of output that should drain.
11., it is characterized in that this first bias circuit comprises an inverter as claim 9 or 10 described level translators.
12., it is characterized in that this second bias circuit comprises an inverter as claim 9 or 10 described level translators.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021500002A CN100492910C (en) | 2002-11-06 | 2002-11-06 | Level converter using base bias |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021500002A CN100492910C (en) | 2002-11-06 | 2002-11-06 | Level converter using base bias |
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| CN1499723A true CN1499723A (en) | 2004-05-26 |
| CN100492910C CN100492910C (en) | 2009-05-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB021500002A Expired - Fee Related CN100492910C (en) | 2002-11-06 | 2002-11-06 | Level converter using base bias |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101075419B (en) * | 2006-05-19 | 2010-06-02 | 株式会社日立显示器 | Image display device |
| CN101383609B (en) * | 2007-09-07 | 2011-03-23 | 东部高科股份有限公司 | Voltage level shifter circuit |
| CN101154941B (en) * | 2006-09-27 | 2011-09-28 | 奇美电子股份有限公司 | Level shifter with reduced power consumption |
| CN103580670A (en) * | 2012-07-25 | 2014-02-12 | 联咏科技股份有限公司 | Dynamic control level shift circuit |
| CN108449081A (en) * | 2015-05-29 | 2018-08-24 | 华为技术有限公司 | A kind of level shifting circuit and device |
-
2002
- 2002-11-06 CN CNB021500002A patent/CN100492910C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101075419B (en) * | 2006-05-19 | 2010-06-02 | 株式会社日立显示器 | Image display device |
| CN101154941B (en) * | 2006-09-27 | 2011-09-28 | 奇美电子股份有限公司 | Level shifter with reduced power consumption |
| CN101383609B (en) * | 2007-09-07 | 2011-03-23 | 东部高科股份有限公司 | Voltage level shifter circuit |
| CN103580670A (en) * | 2012-07-25 | 2014-02-12 | 联咏科技股份有限公司 | Dynamic control level shift circuit |
| CN103580670B (en) * | 2012-07-25 | 2016-08-03 | 联咏科技股份有限公司 | Dynamic control level shift circuit |
| CN108449081A (en) * | 2015-05-29 | 2018-08-24 | 华为技术有限公司 | A kind of level shifting circuit and device |
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| Publication number | Publication date |
|---|---|
| CN100492910C (en) | 2009-05-27 |
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