CN1498052A - Method and system for driving CCFL - Google Patents

Abstract

To efficiently and cost-effectively produce a light source, a CCFL circuit can include a PMOS transistor, first and second NMOS transistors, and a high turns ratio transformer. The transformer can include a primary coil having a center tap, thereby forming first and second primary windings, as well as a secondary coil. The PMOS transistor can be connected to the center tap for driving the transformer. The first and second NMOS transistors can be connected to the first and second primary windings, respectively. Of importance, the first primary winding is tightly coupled to the second primary winding, whereas the first and second primary windings are loosely coupled to the secondary coil.

Description

Drive the method and system of CCFL

Background of invention

Invention field

The present invention relates to use high voltage sine wave drive CCFL (cold-cathode fluorescence lamp) to produce efficient height, light source that cost benefit is good.This light source can be used for, but is not limited to, the back-lighting (backlighting) during notebook, flat-panel monitor and PDA(Personal Digital Assistant) etc. are used.

The discussion of correlation technique

Fluorescent lamp is employed more and more.These application comprise the back-lighting that is used for many consumer goods, and these consumer goods comprise, for example, and notebook, flat-panel monitor and PDA(Personal Digital Assistant).A kind of fluorescent lamp of general type is cold-cathode fluorescence lamp (CCFL).CCFL fluorescent tube air inclusion, it is ionized so that produce and uses required light.

In standard operation, the CCFL fluorescent tube usually needs 600 volts sinusoidal wave and with several milliamperes electric current operation.But voltage can be up to 2000 volts to be used for making initial (or igniting) of CCFL fluorescent tube of its contained gas ionization.When initial, the CCFL fluorescent tube looks like and opens circuit, i.e. the impedance of CCFL stops all electric currents.But behind gas ionization, this impedance reduces, and electric current begins to flow in the CCFL fluorescent tube.

In common embodiment, the CCFL fluorescent tube is driven by High " Q " Circuit, wherein, Q be called the quality of circuit and by the induction reactance of resonant circuit and capacitive reactance divided by resistance measurement.This High " Q " Circuit generally includes other capacitor and inductor, and they have poorly increased the quantity of parts in the system.Therefore, the CCFL circuit has been produced a kind of needs, promptly under the situation that still realizes at least 85% efficient, made extra number of components minimum.

Summary of the invention

According to characteristics of the present invention, the CCFL circuit can comprise PMOS transistor, first and second nmos pass transistors and high turn ratio transformer.This transformer can comprise and the have centre cap primary coil of (center tap) forms the first and second elementary windings thus, and single secondary coil.The PMOS transistor drain can be connected to battery.The drain electrode of first and second nmos pass transistors can be connected respectively to an end of the first and second elementary windings.The source electrode of this first and second nmos pass transistor can be connected to voltage source V SS.

Importantly, the first elementary winding tightly with the second elementary winding coupled.But the first and second elementary windings loosely are coupled with secondary coil, produce effective leakage inductance thus.Particularly, this lax coupling produces effective leakage inductance, and it can be expressed as the series inductance in the secondary coil.In one embodiment, the primary and secondary turn ratio be about 100 and primary inductance be about 200 microhenrys.

Because the leakage inductance of transformer, the voltage of drain electrode place of first and second nmos pass transistors may transition (ringto) arrive the value (for example, doubling cell voltage) that significantly surpasses ideal value.In order to limit the scope of transition transient voltage (ringing voltage), the CCFL system can comprise the buffer circuit (snubbing circuit) of the transistorized source electrode of drain electrode, PMOS that is connected to nmos pass transistor and the one the second elementary windings.

This buffer circuit can comprise first and second diodes, capacitor and resistor.In one embodiment, the input of first diode can be connected to an end of the first elementary winding, and the input of second diode can be connected to an end of the second elementary winding, and the output of first and second diodes can be connected to common node.Resistor and capacitor can be parallel between common node and the battery.

In buffer circuit, capacitor, resistor and diode are configured to keep nominal voltage (nominal voltage) in common node.In one embodiment, this nominal voltage is the twice of cell voltage approximately.But, if a voltage that has above this nominal voltage in the drain electrode of first and second nmos pass transistors, the then first and second diode forward bias voltages and allow transition can (ringing energy) to come to charge to capacitor.This resistor can divide lets out (bleed off) extra transition energy, prevents that thus the voltage of common node from increasing above nominal voltage.

According to another aspect of the present invention, in the CCFL circuit, provide and be used to survey superpotential detection circuit.Importantly, the high voltage end of the resistance of detection circuit and capacitive element and CCFL fluorescent tube separates.Make resistance and capacitive element be subjected to such high voltage can reduce electric current and energy, lower efficiency real undesirable thus by these parts.

Detection circuit can comprise the integrator that receives the CCFL circuit output signal.This integrator produces DC signal COMP, thereby the time average voltage fundamental sum reference voltage from the output signal of CCFL circuit is equated.Advantageously, the COMP signal is without undergoing high voltage, and usually can significant change during normal circuit operation.For example, even during the cycle of weakening (dimming cycle), the rising of COMP signal also is level and smooth and relative noiseless with descending.But if produce arc discharge (arcing), then the COMP signal becomes unstable when circuit makes great efforts to keep regulating.

First diode of the input that detector circuit can also comprise first capacitor with first terminals that are connected to integrator output, have second terminals that are connected to first capacitor and second diode with output of second terminals that are connected to first capacitor.Detector circuit can also comprise the pnp transistor, and input and collector electrode that output, the emitter that its base stage is connected to first diode is connected to second diode are connected to voltage source V SS.First resistor can be connected between the output and voltage source V SS of first diode.Second capacitor can be connected between the output and voltage source V SS of first diode.Second resistor can be connected between the source electrode and voltage source V DD of NPN transistor.In this structure, the transistorized emitter of pnp can provide to be illustrated in whether produce superpotential signal in the CCFL circuit.In one embodiment, second capacitor and second resistor are flip-flop transition cycle (trigger transition period) constant settling time of the output signal of CCFL circuit.

According to another characteristics of the present invention, provide the method for in the CCFL circuit, surveying overvoltage condition.The transistor that provides configuration to produce the detectable signal of expression overvoltage condition can be provided this method.This transistor can use integrator and CCFL circuit to separate.Can provide first circuit to come at the transistorized base stage pumping of pnp (pumping up) voltage.Can provide second circuit at the transistorized base stage drain voltage of pnp.If the output signal of integrator moves brokenly, then extraction can overcome leakage, has increased the voltage and the detectable signal of transistor driving terminals thus.In one embodiment, this aspect can also be included as constant settling time in flip-flop transition cycle of the output signal of CCFL circuit.

According to another characteristics of the present invention, provide another detection circuit of in the CCFL circuit, surveying overvoltage condition.This detection circuit can comprise the PCB track (trace) within 7 to 15 mils (mil) of the high voltage connector that is formed at the CCFL circuit.This PCB track provides the expression detectable signal whether overvoltage condition exists.

According to another characteristics of the present invention, provide the CCFL system that is used to drive the first and second CCFL fluorescent tubes.This CCFL system can comprise PMOS transistor, first and second nmos pass transistors and high turn ratio transformer.This transformer comprises primary coil, and it has the centre cap that forms the first elementary winding and the second elementary winding, and secondary coil, and it has first secondary winding and second subprime winding.In one embodiment, the PMOS transistor drain is connected to centre cap and the transistorized source electrode of PMOS is connected to battery.The drain electrode of first nmos pass transistor is connected to the first elementary winding, and the drain electrode of second nmos pass transistor is connected to an end of the second elementary winding, and the source electrode of first and second nmos pass transistors is connected to voltage source V SS.

Importantly, the first elementary winding tightly with the second elementary winding coupled, and the first and second elementary windings loosely with secondary coil coupling, produce effective leakage inductance thus.The one CCFL fluorescent tube can be coupling between first secondary winding and the voltage source V SS, and the 2nd CCFL fluorescent tube can be coupling between second subprime winding and the voltage source V SS.

Advantageously, because equate (as long as the parasitic capacitance path of two fluorescent tubes is roughly the same) substantially, so only need a feedback loop that is connected to a CCFL fluorescent tube can determine by each CCFL lamp tube current by the first and second CCFL lamp tube current.

In one embodiment, the CCFL system comprises that also at least one first resistor is connected between a CCFL fluorescent tube and the voltage source V SS, and second resistor is connected between the 2nd CCFL fluorescent tube and the voltage source V SS.The size of adjusting first resistor and second resistor provides essentially identical resistance, guarantees that thus the impedance of the first and second CCFL fluorescent tubes is basic identical.

In another embodiment, wherein transformer of this applications exploiting drives two CCFL, and the secondary coil of CCFL system comprises the connection between first and second secondary winding.This connection is positioned at the centre of first and second secondary winding approximately.This connection provides the voltage of cardinal principle with voltage source V SS place.Opposite, an end of first and second secondary winding provides big positive voltage and big negative voltage respectively.Because keep near VSS during normal running, the method that this connection is provided convenience is surveyed overvoltage.If a CCFL is in disconnection (or some disconnection), then the voltage in the secondary winding no longer balance and two secondary winding in name a person for a particular job different with ground connection.Be easy to survey this condition with resistance voltage divider (divider) and comparator.Because the mid point of two secondary winding is usually near VSS, so consumption energy seldom.

The CCFL system that is used to drive the first, second, third and the 4th CCFL fluorescent tube is provided.This CCFL system comprises the PMOS transistor and first and second nmos pass transistors.This CCFL system also comprises the first high turn ratio transformer, and it can comprise having centre tapped first primary coil, forms the first elementary winding and the second elementary winding.This first high number of turn transformer can also have first secondary coil, and it comprises first secondary winding and second subprime winding.The CCFL system can also comprise the second high turn ratio transformer, and it can comprise having second centre tapped second primary coil, forms the 3rd elementary winding and the 4th elementary winding.The second high turn ratio transformer can have the second subprime coil, and it comprises level winding and the 4th secondary winding for the third time.

The PMOS transistor drain is connected to first and second centre caps, and the transistorized source electrode of PMOS is connected to battery.The drain electrode of first nmos pass transistor is connected to an end of the first elementary winding and an end of the 3rd elementary winding.The drain electrode of second nmos pass transistor is connected to an end of the second elementary winding and an end of the 4th elementary winding.The source electrode of first and second nmos pass transistors is connected to voltage source V SS.

The first elementary winding tightly with the second elementary winding coupled.The 3rd elementary winding tightly with the 4th elementary winding coupled.The first and second elementary windings loosely are coupled with first secondary coil.The third and fourth elementary winding loosely is coupled with the second subprime coil.The one CCFL fluorescent tube is coupling between first secondary winding and the voltage source V SS.The 2nd CCFL fluorescent tube is coupling between second subprime winding and the voltage source V SS.The 3rd CCFL fluorescent tube is coupling in for the third time between level winding and the voltage source V SS.The 4th CCFL fluorescent tube is coupling between the 4th secondary winding and the voltage source V SS.First is connected with the 4th secondary winding.Second with for the third time the level winding be connected.

In one embodiment, the CCFL system can also comprise with the first, second, third and the 4th CCFL fluorescent tube in the current sense network of a coupling.In another embodiment, the CCFL system can also comprise with the second subprime winding and for the third time the level winding coupled faulty circuit.This faulty circuit can comprise first diode and and second diode of second resistive divider coupling of first resistive divider, second resistive divider and the coupling of first resistive divider.Can connect first and second diodes and provide the logical "or" function to fault-sensing circuit.

The method of the malfunction of detection system is provided.This system can comprise transformer, a CCFL fluorescent tube and the 2nd CCFL fluorescent tube with primary coil and secondary coil.This method can be included in creates tap in the secondary coil, thereby forms first secondary winding and second subprime winding.The one CCFL fluorescent tube can be connected to an end of first secondary winding.The 2nd CCFL fluorescent tube can be connected to an end of second subprime winding.Malfunction can be determined by the voltage of sensing tap place.

In one embodiment, determine that in tap place voltage comprises distribution and adjusts voltage.Distribute voltage can comprise the size of adjusting resistive divider, thereby under normal operating condition, the voltage of adjustment is less than the first predetermined threshold voltage, and during fault condition, the voltage of adjustment is higher than the second predetermined threshold voltage.

Another CCFL system that is used to drive the first, second, third and the 4th CCFL fluorescent tube is provided.This CCFL system also comprises the PMOS transistor and first and second nmos pass transistors.This CCFL system also comprises single high turn ratio transformer.This transformer comprises having the centre tapped primary coil that forms the first elementary winding and the second elementary winding.This transformer also comprises secondary coil, and it has first secondary winding, second subprime winding, level winding and the 4th secondary winding for the third time.

The PMOS transistor drain is connected to centre cap, and the transistorized source electrode of PMOS is connected to battery.The drain electrode of first nmos pass transistor is connected to an end of the first elementary winding, and the drain electrode of second nmos pass transistor is connected to an end of the second elementary winding, and the source electrode of first and second nmos pass transistors is connected to voltage source V SS.The first elementary winding tightly with the second elementary winding coupled, and the first and second elementary windings loosely are coupled with the first, second, third and the 4th secondary coil.

The one CCFL fluorescent tube is coupling between the end and voltage source V SS of first secondary winding.The 2nd CCFL fluorescent tube is coupling between the end and voltage source V SS of second subprime winding.The 3rd CCFL fluorescent tube is coupling in for the third time between the end and voltage source V SS of level winding.The 4th CCFL fluorescent tube is coupling between the end and voltage source V SS of the 4th secondary winding.Notice that the other end of first and second secondary winding connects.Similarly, the other end of third and fourth secondary winding connects.As the situation with two independent transformers, being connected to each other of secondary winding provides easily method to survey the overvoltage fault.In one embodiment, the circuit sensing network can with a coupling in the first, second, third and the 4th CCFL fluorescent tube.

The another kind of CCFL that is used to drive the first, second, third and the 4th CCFL fluorescent tube also is provided system.This CCFL system also comprises the PMOS transistor and first and second nmos pass transistors.This CCFL also comprises single high turn ratio transformer.This transformer comprises having the first centre tapped primary coil, forms the first elementary winding and the second elementary winding.This transformer also comprises second centre cap, forms the 3rd elementary winding and the 4th elementary winding.This transformer also comprises secondary coil, and it has first secondary winding, second subprime winding, level winding and the 4th secondary winding for the third time.

The PMOS transistor drain is connected to first and second centre caps, and the transistorized source electrode of PMOS is connected to battery.The drain electrode of first nmos pass transistor is connected to an end of the first elementary winding and an end of the 3rd elementary winding.The drain electrode of second nmos pass transistor is connected to an end of the second elementary winding and an end of the 4th elementary winding.The source electrode of first and second nmos pass transistors is connected to voltage source V SS.The first elementary winding tightly with the second elementary winding coupled, the 3rd elementary winding tightly with the 4th elementary winding coupled, the first and second elementary windings loosely are coupled with first and second secondary coils, and the third and fourth elementary winding loosely is coupled with third and fourth secondary winding.

In this CCFL system, the one CCFL fluorescent tube is coupling between the end and voltage source V SS of first secondary winding, the 2nd CCFL fluorescent tube is coupling between the end and voltage source V SS of second subprime winding, the 3rd CCFL fluorescent tube is coupling in for the third time between the end and voltage source V SS of level winding, and the 4th CCFL fluorescent tube is coupling between the end and voltage source V SS of the 4th secondary winding.The other end of first and second secondary winding connects.Similarly, the other end of third and fourth secondary winding connects.As situation before, the method that an end of the secondary winding that links together is provided convenience is surveyed the overvoltage fault.Determine that in the situation (4 fluorescent tubes) of single transformer the method for overvoltage fault is similar to the fault-finding method of the situation (also being 4 fluorescent tubes) of 2 transformers substantially.In one embodiment, the current sense network can with a coupling in the first, second, third and the 4th CCFL fluorescent tube.

The method that realizes transformer also is provided.Transformer has zone line, first end and second end.Method is included in zone line low AC voltage is provided, and provides the first high AC voltage with first phase place at first end, and provides the second high AC voltage with second phase place at second end.In one embodiment, low AC voltage is VSS.In another embodiment, first phase place is positive and second phase place is born.First end can comprise first winding and second winding that the output of first homophase is provided, and second end can comprise the tertiary winding and the 4th winding that the output of second homophase is provided.Importantly, the phase place of the phase place of first homophase output and the output of second homophase is an out-phase.

Summary of drawings

Fig. 1 illustrates the CCFL circuit, and it comprises outside PMOS transistor, two outside nmos pass transistors and has the high turn ratio transformer of centre tapped primary coil and single secondary coil.

Fig. 2 illustrates the small-signal model of Fig. 1 transformer.

Fig. 3 illustrates the Utopian gate driving waveform of Fig. 1 CCFL circuit.

Fig. 4,5 and 6 illustrates the various waveforms that produce in the CCFL circuit working by Fig. 1.

Fig. 7 A illustrates the equal transformer and the load circuit model of the first area that is used for the CCFL circuit working.

Fig. 7 B illustrates the equal transformer and the load circuit model of the second area that is used for the CCFL circuit working.

Fig. 7 C illustrates the equal transformer and the load circuit model in the 3rd zone that is used for the CCFL circuit working.

Fig. 7 D illustrates equal transformer of four-range and the load circuit model that is used for the CCFL circuit working.

Fig. 8 A illustrates according to the system that the present invention includes the CCFL circuit.

Fig. 8 B illustrates an example of the additional circuit that is used to produce the CE signal.

Fig. 8 C illustrates a line map of the system that is used for Fig. 8 A.

Fig. 9 illustrates another embodiment of the portion C CFL system that comprises buffer circuit.

Figure 10 illustrates the detail drawing of voltage-controlled oscillator (VCO).

Figure 11 illustrates the rough schematic view of fault and control logic.

Figure 12 illustrates and can be used for surveying harmless (non-invasive) circuit of the superpotential typical case who offers the CCFL circuit.

Figure 13 illustrates the preferred arc discharge path that can be used for surveying and closing the CCFL circuit when arc discharge.

Figure 14 illustrates the circuit that can drive two series connection CCFL fluorescent tubes.

Figure 15 illustrate Figure 14 modification the geometry of transformer.

Figure 16 A illustrates the technology that is used to drive 4 CCFL fluorescent tubes.

Figure 16 B illustrates the sensing circuit that is used for the coupling of the CCFL structure of Figure 16 A.This sensing circuit comprises two diodes, and they are coupled and carry out OR function, thereby forms synthetic OVP signal.

Figure 16 C illustrates another embodiment, wherein can form two primary coils and 4 secondary coils on a transformer core.

Figure 16 D illustrates the exemplary physics realization of the schematic diagram shown in Figure 16 C.

Figure 16 E illustrates another embodiment, wherein can form primary coil and a plurality of secondary coil of two amalgamations (split) on a transformer core.

Figure 16 F illustrates the exemplary physics realization of the schematic diagram shown in Figure 16 E.

Figure 16 G illustrates the method that is used to survey the overvoltage fault on the transformer with 4 secondary winding.

Figure 17 illustrates the parasitic capacitance path of the CCFL fluorescent tube among Figure 14.

Embodiment

According to characteristics of the present invention, can use the transformer-LC accumulator that drives by several low power metal oxide semiconductor field effect transistors to make up and produce the required high voltage of CCFL work.For example, Fig. 1 illustrates CCFL circuit 100, and it comprises outside PMOS transistor 101, two outside nmos pass transistors 102 and 103 and high turn ratio transformer 104 with centre tapped primary coil and single secondary coil.Each elementary winding tightly with another elementary winding coupled, but loosely be coupled with secondary coil.Should lax coupling produce effective leakage inductance, it can be expressed as the series inductance in the secondary coil.The primary and secondary turn ratio is about 100.The general value of primary inductance is about 200 microhenrys.

Fig. 2 illustrates the small-signal model 200 of transformer 104, and wherein model 200 comprises primary inductance L _p, turn ratio 1: N and leakage inductance L _LeakWith the parasitic shunt capacitance C that strides across secondary coil _ParallelAccording to characteristics of the present invention, can advantageously strengthen leakage inductance and come and little electric capacity (for example, parasitic capacitance, C _Parallel) resonance, eliminated demand thus to the extra prior art parts (such as inductance and/or electric capacity) of the elementary winding that is connected to transformer.

Fig. 3 illustrates the ideal grid drive waveforms of CCFL circuit 100.With reference to figure 1-3, shown in waveform 302 and 303, the duty cycle signal with 50% (duty cycle signal) difference is driving N MOS transistor 102 and 103 out of phase.The frequency of NMOS drive signal will be the frequency that drives CCFL fluorescent tube 105.Drive PMOS transistor 101 with the pulse-width signal that doubles the NMOS102/103 driving signal frequency (PWM).In this case, if nmos pass transistor 102 and PMOS transistor 101 are for opening, then nmos pass transistor 103 is for closing, and 107 sides that are connected to the primary coil of nmos pass transistor 102 are driven into ground, and cell voltage (as being provided by battery 106) is provided mid point 109.Opposite, 108 sides that are connected to the primary coil of nmos pass transistor 103 are driven to the cell voltage of twice.Electric current raises in 107 sides, transfers energy to the secondary coil of transformer 104 thus.This energy is stored in leakage inductance L _LeakIn.Notice leakage inductance L _LeakIn transformer 104 and CCFL load (not shown), resonate with the parasitic capacitance (not shown).

When PMOS transistor 101 was closed, the voltage of mid point 109 was got back to ground connection, as being in nmos pass transistor 103 drain electrodes that double cell voltage originally.By half period, nmos pass transistor 102 (unlatching) is closed and nmos pass transistor 103 (closing) unlatching.In this point, PMOS transistor 101 is opened once more, allows electric current to raise in 108 sides of elementary winding thus.Energy in the elementary winding is passed to secondary winding and is stored in leakage inductance L once more _LeakIn, but have opposite polarity specifically.

Therefore, the duty cycle of PMOS transistor 101 is controlled at the energy that is delivered to secondary coil in the transformer 104 from primary coil.Note, CCFL circuit 100 can be constantly and PMOS transistor 101 work together (i.e. 100% duty cycle), though in this case energy with irregular.

The efficient of CCFL circuit 100 is still very high, even have the second other MOS transistor (that is, nmos pass transistor 102 or nmos pass transistor 103) in circuit pathways.The I of extra MOS transistor square of (I-squared) loss is negligible.For example, consider 6 watts of application load that operate at 10 Fu Dianchidianyachu.To transistorized power (P) loss be with 50 milliohm resistance (R) and 600 milliamperes of drain currents (I):

P=I * I * R=600 * 600 * 0.05=18 milliwatt

The switching loss that also must consider nmos pass transistor 102 and 103 is determined the efficient of CCFL circuit 100.But these switching losses are more obvious than I square of loss hardly.For example, at transistorized power loss be with 10 volts of drain voltages (V) variation, 50 gate drive signal rise time nanosecond (tau) and 10 microsecond cycles (T):

P=1/3 * I * V * (tau/T)=1/3 * 600 * 10 * (50/10)=10 milliwatt

It should be noted that because there is not the primary side capacitor, so do not produce capacitor ESR loss.Therefore, when the I quadratic sum switching loss considered simultaneously in the nmos pass transistor, CCFL circuit 100 is easy to reach about 85% efficient.But 104 relevant losses can obviously surpass I quadratic sum switching loss with transformer.Therefore, the transformer of discussing with reference to figure 4-6 in more detail helps most significantly efficient to reduce.Unfortunately, transformer loss is identical for most current circuit topologys.

Fig. 4,5 and 6 illustrates the various waveforms that produced at work by CCFL circuit 100.Particularly, Fig. 4,5 and 6 illustrates the supposition circuit working and is respectively the waveform that is produced under the situation of 9 volts, 13 volts and 21 volts at input (battery) voltage.These duty cycle that illustrate the CCFL circuit are along with cell voltage is increased to 21 volts and stably descend from 9 volts.

Track 401,402 and 403 among each figure illustrates the gate driving waveform at transistor 101,102 and 103 respectively.In one embodiment, the gate driving drive waveform of transistor 101 rises up to cell voltage but only drops under the cell voltage about 7.5 volts.It should be noted that track 401 will drive the PMOS transistor in preferred embodiment, thus when track 404 PMOS device when low be Gao Shiwei " pass " for " opening " works as track 404.The situation of the NMOS just in time situation with PMOS is opposite, thus when track 402 when high then its nmos pass transistor be " opening ", and when track 402 be when hanging down, its transistor is " pass ".Track 404 (among Fig. 4-6) illustrates the voltage that the mid point 109 (and drain electrode of PMOS transistor 101) of elementary winding is located.This waveform can be characterized by the duty cycle of variation from being grounding to the pulse of cell voltage.When mid point 109 is driven into when high, represented as track 406, electric current increases by PMOS transistor 101 (notices that electric current is also by the increase (that is a side that, has the nmos pass transistor of conducting) in 107/108 side.When PMOS transistor 101 is closed, then return in the initial back that sharply descends and drop to 0 by this transistorized electric current.

Track 405 illustrates the voltage (that is, be connected on the line of elementary winding of transformer 104 voltage) (noticing that the track of pair nmos transistor 103 is same, but has moved on the time) of drain electrode place of nmos pass transistor 102.Track 407 illustrates the electric current by nmos pass transistor, and it equals the electric current in the PMOS transistor 101 for the time portion (for example, referring to area I) of PMOS transistor 101 conductings.When in the elementary winding of current direction, energy is passed to secondary winding and is stored in leakage inductance L _LeakIn (and any parasitic capacitance on the secondary winding).Notice that the electric capacity when nmos pass transistor is closed in the nmos pass transistor approaches 0, thereby expression CCFL circuit 100 is driven near its resonance frequency.Though this embodiment does not directly detect 0 current point, switching frequency can be revised so that satisfy 0 current condition.

In case PMOS transistor 101 is finished an ON/OFF circulation, then along with alternative transistor turns, it repeats once more.Shown in track 408, this complementary operation produce in the input of load (for example, the CCFL fluorescent tube 105) symmetry, sinusoidal waveform approx.

The operation of CCFL circuit 100 can be divided into 4 zones (I, II, III and IV) shown in Fig. 4-6.Fig. 7 A illustrates suitable transformer and the load circuit model 700 (I) that is used for area I.In area I, the part 701B of elementary winding connects by battery 705, increases the electric current in the part 701B thus and transfers energy to secondary winding 702.Another part 701A of elementary winding remains on and doubles cell voltage, and promptly therefore the substrate diode of nmos pass transistor (substrate diode) 708 reverses biased also do not have electric current to flow through part 701A.

Fig. 7 B illustrates equal transformer and the load circuit model 700 (II) that is used for area I I.In area I I, battery 705 and elementary winding 701 disconnect.In this structure, electric current flows through the part 701A and the 701B of elementary winding 701.But the beginning electric current descends very soon, returns with the slow speed of rising electric current subsequently and drops to 0.Initial decline is effective variation according to when the leakage inductance of electric current when a part of elementary winding is transferred to two parts, thereby changes the number of turn on the core effectively.

Fig. 7 C illustrates equal transformer and the load current model 700 (III) that is used for area I II.In area I II, the part 701A of elementary winding connects by battery 705, increases electric current in the part 701A (but along with the side of area I in the opposite direction) thus and transfers energy to secondary winding 702.Another part 701B of elementary winding remains on the twice cell voltage, and promptly therefore substrate diode 708 reverses biased of nmos pass transistor also do not have electric current to flow through in part 701B.Therefore, area I II is putting upside down of area I.

Fig. 7 D illustrates equal transformer and the load current model 700 (IV) that is used for area I V.In area I V, battery 705 and elementary winding 701 disconnect.In this structure, electric current flows through the part 701A and the 701B of elementary winding 701.But it is very fast that the beginning electric current descends, and returns with the speed slower than rising electric current subsequently and drop to 0.Initial decline also is owing to when effective variation of the leakage inductance of electric current during from a part to two of elementary winding part, change the number of turn on the core thus effectively.Area I V is putting upside down of area I I.

When duty cycle changed with cell voltage, whole resonance frequency also can change.For example, with reference to the track 407 of figure 4 and 6, the gradient (i.e. 21 volts of operations) among Fig. 6 in the area I is steeper than (i.e. 9 volts of operations) among Fig. 4.This result can expect, because the voltage of elementary winding is higher.On the contrary, the gradient of the track 407 in area I I and the IV is basic identical between operating at 9 volts and 21 volts.This result also can expect, because identical for the voltage of these phase transformer terminals, and irrelevant with cell voltage.Note,, then be used for 9 volts desirable driving frequencies of operating and be used for 21 volts identical if track is linear fully.But, as shown in the area I, 9 volts operating period track be non-linear, but curve to 0 electric current.Track in 21 volts of operating period area I is strict linear.Therefore, it is slower than being used for 21 volts of desirable driving frequencies of operating to be used for 9 volts of desirable driving frequencies of operating.Therefore, carry out switch in order to keep transistor near 0 electric current the time, switching frequency must increase with the increase of cell voltage.As long as between RDELTA stitch and Vbatt, connect a resistor, then when Vbatt increases, will increase oscillator frequency.The resistance value of resistor and maximum Vbatt voltage are determined the scope of polarizer frequency.

System overview

Fig. 8 A illustrates according to system 800 of the present invention.System 800 comprises CCFL circuit 801, and it comprises the parts about CCFL circuit 101 (Fig. 1).CCFL circuit 801 and the operation that comprises the system 800 of CCFL circuit 801 will be described in further detail now.CCFL circuit 801 comprises PMOS transistor 803, and it is connected between the mid point of elementary winding of cell voltage 802 and transformer 814.The source electrode of PMOS transistor 803 is also connected to the capacitor 815 as the AC bypass of battery.The drain electrode of PMOS transistor 803 is also connected to diode 818, and it is coupled with voltage VSS (for example, ground connection) conversely.Diode 818 is not strict necessary for the work of circuit, but increase sometimes transition is minimized.The elementary winding of transformer 814 is connected to the drain electrode (wherein, nmos pass transistor 804 and 816 source electrode are connected to ground) of nmos pass transistor 804 and 816.The secondary winding of transformer 814 is coupling between the input of ground connection and CCFL fluorescent tube 805.CCFL circuit 801 also comprises output and diode 806 between the resistor 807 that is connected CCFL805 and output and the diode between the ground connection 809 that is connected CCFL fluorescent tube 805.

According to the present invention, the electric current by CCFL801 is controlled by the combination of the frequency of the duty cycle of drive waveforms (being the waveform of driving transistors 803) and drive waveforms.In one embodiment, system 800 comprises first controll block that is connected to node N3, and it provides DC signal COMP positive terminal to comparator 853.The duty cycle of the first controll block controlling and driving waveform.Especially, first controll block induction CCFL electric current is with its internal benchmark (internal reference) integration and adjust this duty cycle and obtain desirable power mutually.

System 800 also comprises second controll block, and it provides signal RAMP (sawtooth waveform) negative terminals to comparator 853.The output signal of comparator 853, promptly pwm signal (pulsewidth adjustment waveform) is provided for output driver 880, and it provides clock signal OUTA, OUTAB and OUTC to transistor 803,804 and 816 conversely respectively.(promptly arriving the drive waveforms of CCFL circuit 801).The frequency shift that second controll block can be used for drive waveforms is the function of cell voltage.When the voltage of battery 802 increased, oscillator frequency also increased.When cell voltage changed, this can make circuit working near its resonance frequency.

System 800 also comprises the 3rd controll block, and it is by making the lamp ON/OFF adjust the brightness of CCFL fluorescent tube 805 in the duty cycle that changes.In this embodiment, the BRIGHT voltage that provides of user can with mild rising) signal is relatively to produce the CHOP signal.This CHOP signal is provided for fault and control logic 870, and they produce the NORM signal that is input to output driver 880 conversely.

First controll block

As mentioned above, can on circuit 813, respond to circuit 813 and node N3 coupling by the electric current of CCFL805.According to characteristics of the present invention, the voltage on the circuit 813 can drive the input of integrator 820.Especially, integrator 820 is by the voltage on resistor 821 receiving liness 813, and wherein the negative pole end of resistor 821 and error amplifier 823 is coupled.In one embodiment, resistor 821 provides 10 kilohms resistance.Error amplifier 823 is compared with this voltage with at the reference voltage V R1 that its noninverting terminals received.

In one embodiment, reference voltage V R1 is from the stable benchmark of temperature and power supply (such as, bandgap reference) is produced by resistive divider.Also can use other known technologies that are used to provide reference voltage V R1.In one embodiment, reference voltage V R1 can be between 0.5 volt and 3.0 volts.Notice that reference voltage V R1 is big more, the average voltage of resistor 821 is big more.On the contrary, if reference voltage V R1 is too little, then error amplifier skew (offset) and other non-ideal factors will become obvious.Therefore, in one embodiment, reference voltage V R1 can be 2.5V.

Capacitor 82 provides the electric capacity of 1 microfarad in one embodiment, is coupled to the negative pole end and the output of error amplifier 823, forms integrator 820 thus.The purpose of integrator 820 is to produce DC signal COMP, thereby makes the time average voltage at node N4 equal reference voltage V R1 substantially.

Clamp circuit (clamping circuit) 840 can limit the increase of COMP signal.In one embodiment, clamp circuit 840 comprises error amplifier 842, and it is provided to output signal the grid of transistor 841.Transistor 841 (a kind of n transistor npn npn) is coupled and the electrode input end of its drain electrode and error amplifier 842 and the output coupling of integrator 820 its source electrode and VSS.Error amplifier 842 also comprises negative input, terminals of it and current source 843 and capacitor 844 (another terminals and VSS coupling) coupling.In this structure, clamp circuit 840 allows the COMP signal to increase to the fast speed of capacitor 844 chargings unlike current source 843.Therefore, clamp circuit 840 prevents that COMP signal (and so pwm signal) from arriving its full-power mode immediately, allows CFL805 to start lentamente thus.Make power be increased to the life-span that CCFL805 can advantageously prolong the miscellaneous part of its life-span and CCFL circuit 801 gradually.

Second controll block

The frequency of the oscillator of VCO 850 is determined the driving signal frequency at the grid of PMOS transistor 803.In this embodiment, the user can set minimum oscillator frequency with resistor 852, wherein

Oscillator frequency (hertz)=2.8E9/ resistance 852 (ohm)

Detailed VCO 850 shown in Figure 10.In this embodiment, VCO 850 comprises the current source that the user adjusts, and it comprises error amplifier 1001, resistor 852 and nmos pass transistor 1002.Error amplifier 1001 is configured to receive reference voltage V R3 and at the signal at the source electrode place of nmos pass transistor 1002.Error amplifier 1001 offers its output signal the grid of nmos pass transistor 1002.In this structure, electric current equals the resistance of reference voltage V R3 divided by resistor 852.In one embodiment, reference voltage V R3 is about 1.5 volts.

Subsequently, this electric current uses PMOS transistor 1003 and 1004 mirrors (mirrored) to capacitor 1005.This electric current gives capacitor 1005 chargings, increases the voltage at node N11 place thus.Especially, voltage is elevated to the predetermined voltage of being determined by error amplifier 1007, boosted voltage and reference voltage V R4 on this error amplifier 1007 receiving node N11.In one embodiment, reference voltage V R4 can be about 3.0 volts, also the predetermined boosted voltage on the node N11 is set at 3.0 volts thus.When the voltage on the node N4 reached predetermined voltage, error amplifier 1007 exported off switch 1006 with signal, made capacitor 1005 discharge into VSS (for example, ground) thus.Therefore, in this structure, capacitor 1005, error amplifier 1007 and switch 1006 form the standard relaxation oscillator.Note, use the output of inverter 1009 and 1010 buffer error amplifiers 1007 that clock signal clk is provided.Notice that further at the rising signal that node N11 produces, promptly signal RAMP can be used for creating pwm signal (referring to the comparator among Fig. 8 A 853).

In one embodiment, distributing switch 1008, PMOS transistor 1011 and error amplifier 873 can be used for some electric currents are increased to node N11, increase the frequency of RAMP signal thus.In this embodiment, error amplifier 873 connects with unified gain (unity gain), output is equaled substantially the constant voltage of reference voltage V R2.In one embodiment, reference voltage V R2 is about 1.25 volts.

When voltage Vbatt increases, more current flows through resistor 851 and enter distributing switch 1008.With the increase of the resistor 851 control generator frequencies of battery 802 coupling, as the function of cell voltage (Vbatt).In one embodiment, resistor 851 has 200 kilo-ohms resistance.The pass is:

Δ frequency (hertz)=3.44E8* (Vbatt-VR2)/resistance 851

In one embodiment, divided by the factor 50, the magnitude of current of guaranteeing thus to be increased on the node N11 Already in is quite little with electric current for distributing switch 1008.Because oscillator frequency can adjust upward when cell voltage increases, preferably can make the harmonic distortion minimum of output waveform.

The 3rd controll block

The 3rd controll block is adjusted brightness by making lamp open and close at the duty cycle place that changes.In this was described, " weakening the cycle " was meant the complete cycle that comprises " opening " and " pass " two states.Weaken the last of cycle at each, the COMP stitch is dragged down.In the beginning in the new cycle of weakening, the COMP signal is attempted quick increase, but by pincers on the voltage of (clamp) SSV (soft start voltage) stitch.Weaken the switching rate that the last capacitor that discharges 844 of cycle is set the voltage at SSV stitch places at each, and the maximum anodal switching rate of COMP stitch.

In one embodiment, ramp generator 860 can produce the slow boosted voltage (being sawtooth waveform) by small capacitor 861 restrictions.In one embodiment, capacitor 861 has the electric capacity of about 0.015 microfarad.Comparator 862 can be compared this boosted voltage with the BRIGHT signal, for example customer-furnished dc voltage, and it is proportional with required brightness.According to comparative result, the variable duty cycle factor signal CHOP of comparator 862 outputs.Importantly, the CHOP signal can make output driver 880 shutdown switches, thus by the OUTA signal is drawn high and make it to stop.In order to make the slow dissipation of energy in the LC storage capacitor and not produce high voltage, signal OUTAPB and OUTC continue switch.When the voltage at BRIGHT stitch place increased, the duty cycle (and brightness of CCFL fluorescent tube 805) that weakens the cycle increased.

Weaken the frequency in cycle and set by the value of capacitor 861, and and it is proportional by the electric current of resistor 852 (it sets the minimum frequency of operation of VCO 850) setting.Capacitor 861 is set at 0.01 microfarad, and resistor 852 is set at 47.5 kilo-ohms, and VSS is set at ground connection has produced about 100 hertz period frequency that weakens.This frequency should change on the contrary with the value of capacitor 861.

Brightness can also be by replacing resistor 807 (and 808) to control with variable resistance.In this case, thus the BRIGHT stitch should move VDD to CCFL811 is moved with 100% duty cycle.Notice that this structure can cause low intensive flicker, but the embodiment of other functions and use resistor 807 is suitable.

Start-up operation

In one embodiment, the SSC signal can produce by alternative current source.Particularly, two current sources, one is 1 microampere, another is 150 microamperes, can optionally be connected to the SSC end of fault and control logic 870 and terminals of capacitor 871.Capacitor 871 another terminals are connected to VSS.In one embodiment, capacitor 871 has the low electric capacity of 0.022 microfarad.

During " cold " start-up operation of CCFL805, promptly follow the startup behind the predetermined amount of time that CCFL805 is in the pass closely, fault and control logic 870 produce active signal (active signal) FIRST, select thus than the current source of low value (promptly, 1 microampere, in this embodiment).On the contrary, in subsequently " heat " between the starting period, promptly less than the startup in the time of predetermined amount of time, fault and control logic 870 produce non-active signal FIRST, select the current source (promptly 150 microamperes) of high value thus.In this mode, the capacitor 871 spent time ratio warm start of charging during cold start-up is long.When fault-sensing circuit can't use, the oblique ascension (ramp) that is produced by the SSC stitch was used for the determining time.If should " blanking " not at interval because false sense (misperceived) fault, weaken cycle period electric capacity at each and will close enduringly.This operates in the description of fault electric capacity more complete explanation.

The typical circuit design

Fig. 8 C illustrates a circuit design of the system 800 that is used for Fig. 8 A.It should be noted that like numerals will represents like.As shown in Fig. 8 C, other parts can be included in the system 800.Particularly, other parts can comprise, for example resistor 826, pnp transistor 827, and capacitor 824,828 and 829.In one embodiment, the capacitor 824 with 1 microfarad electric capacity is used for regulating the reference voltage (3.3 volts in one embodiment) in the chip.Capacitor 828, load (pull-up) resistance 826 and pnp transistor 827 form linear regulator, and it can provide VDD supply voltage (being 5 volts in one embodiment) from battery 802.In one embodiment, resistor 826 can provide 2 kilo-ohms resistance, and capacitor 828 can provide the electric capacity of 4.7 microfarads, and pnp transistor 827 can provide 0.6 volt base-emitter voltage.

Capacitor 828 can be used as by-pass capacitor in this embodiment, and it is provided for the AC electric current of the peak value of switch external mos field effect transistor (mosfet) 803,804 and 816 effectively to driver portion 880.In one embodiment, capacitor 829 can provide the electric capacity of 4.7 microfarads.Frame of broken lines 825 expressions parts wherein can be produced on the chip.

The CCFL circuit operation

With reference to figure 8A, the mid point of the elementary winding of PMOS transistor 803 driving transformers 814.The signal that offers the grid of PMOS transistor 803 is pulse-width modulation (PWM) signal, and its control enters the electric current of elementary winding, and further controls the electric current that enters in the CCFL fluorescent tube 805.The voltage that is provided by battery 802 can be provided the drive signal of PMOS transistor 803 on the way, and drops to predetermined voltage (predetermined voltage can pincers under cell voltage about 7.5 volts) in one embodiment. Nmos pass transistor 804 and 816 alternatively is connected to voltage VSS with the exterior node of elementary winding.These transistors are by half driving with the frequency of the drive signal that offers PMOS transistor 803 of the square wave of 50% duty cycle.

Alternative embodiment

Fig. 9 illustrates another embodiment of a CCFL system part.Similar elements label among Fig. 8 A, the 8C and 9 is identical.The embodiment of Fig. 9 B comprises " buffering " circuit, and it comprises capacitor 902, resistor 903, diode 904 and diode 905.It operates in title and describes for the part of " being used for making the minimized circuit of transition ".The embodiment of Fig. 9 also comprises the circuit relevant with the CE stitch, and promptly many users find by opening and closing switch 911 resistor 910, switch 911 and the capacitor 912 of switch CCFL easily.The embodiment that it should be noted that Fig. 9 does not comprise capacitor 822, has increased the boosted voltage at SSV stitch place thus significantly.

In the embodiment of Fig. 8 A, resistor 810 and 811 can be used for detecting the overvoltage at the hot side of CCFL.The embodiment of Fig. 9 replaces resistor 810 and 811 with the another kind of voltage divider that comprises resistor 921,922 and 923.These resistors remain on lower and can forbid the OVP function substantially than under voltage threshold value (250 millivolts) high state than OVP threshold value (3 volts) by the current potential with OVP stitch place.

The embodiment of Fig. 9 also comprises and comprises resistor 925 and 926 and the adjustable resistance distributor of capacitor 927.These parts can by than the driving frequency of transformer slowly Duo but the brightness (referring to Fig. 8 A) that makes 811 pulses of CCFL fluorescent tube open and close under the fast frequency of the frequency that can survey than people's eyes to adjust CCFL fluorescent tube 811.For example, if the driving frequency of CCFL805 is 50 KHz, then weakening frequency can be the 150-200 hertz.

Supply voltage

According to an embodiment, the voltage source (3 lithium ion batteries that provide in the common notebook) between the 7-24 volt can be provided battery 802.Majority circuit in the system 800 can be with conventional voltage, and for example 5 volts, work.For this reason, PNP transistor 827 can be used for providing stable vdd voltage from battery 802.Especially, PNP stitch (referring to Fig. 8 C) drives the base stage of PNP transistor 827, and the VDD stitch is the VDD power supply that enters chip.In one embodiment, the capacitor of 4.7 microfarads can be walked around the VDD power supply and arrive ground connection.In this structure, if outside VDD power supply can get, then PNP transistor 827 can be unnecessary and PNP stitch can float (float).

When chip enable signal (CE) very low (for example, less than 0.4 volt), then chip enters 0 current status.In one embodiment, the PNP stitch can place high impedance status, vdd voltage is dropped to 0 volt thus.Can be at the induced inside vdd voltage, thus switching circuit is not opened, and unless vdd voltage is bigger than the first predetermined threshold voltage (for example, 4.5 volts), and internal reference (for example, 3.3 volts) is accurately and effectively.Circuit in the reference block is used for determining whether benchmark adjusts (close to regulation).Can not adjust in case determined benchmark, then reference voltage can be used for determining whether VDD surpasses specific threshold voltage, for example 4.5 volts.In one embodiment, in case reached predetermined threshold, switching circuit will move up to vdd voltage less than the second predetermined threshold voltage (for example, 3.5 volts).

Output driver

In one embodiment, OUTAPB and OUTC stitch are the output of standard CMOS driver.On the contrary, in preferred embodiment, the OUTA driver is drawn high cell voltage, and for example maximum 24 volts, but inner pincers is in 8 volts of cell voltage.For each signal transition of PMOS transistor 803, OUTA attenuator (pad) will be at short notice (for example, about 100 nanoseconds) minimizing/acquisition (sink/source) electric currents (for example about 500 milliamperes).After the initial burst (burst) of electric current, electric current is got back to (scaled back) (when being 1 milliampere and acquisition (sourcing) when for example, reducing (sinking) is 12 milliamperes) in proportion.This technology makes border transition fast, and whole power dissipation minimum.

Error protection

According to another characteristics of the present invention, fault condition detection can be provided by the undesirable voltage relevant with CCFL fluorescent tube 805 that is provided.When meeting with any one malfunction, the CCFL circuit is lockable.In this point, give to reset or the energising of circulation CE stitch can return to normal running with CCFL circuit 801.

The identification of first fault condition detection offers the overvoltage of CCFL fluorescent tube 805.In the system 800 of present embodiment, resistor 811 and 810 is coupling between node N6 and the VSS, forms voltage driver thus.In this structure, the node N5 between the resistor 811 and 810 provides and the proportional OVP signal of the voltage of CCFL805.Node N5 is connected to fault and control logic 870 by line 812.If OVP signal (and then CCFL voltage) is too high, then in fact the moving signal of long-term job that is produced by fault and control logic 870 can close CCFL circuit 801 and prevent to produce potential precarious position.In other words, if the voltage at node N6 place too high (for example, 3 volts), then fault and control logic 870 will be closed chip, no matter current which kind of mode of operation that is in.

The identification of second fault condition detection offers the under voltage of CCFL fluorescent tube 805.Especially, fault and control logic 870 can also detect at node N6 whether under voltage is arranged.Second fault condition detection can be used for guaranteeing that the input voltage of CCFL fluorescent tube 805 is upward surpassing predetermined voltage level by week basis (cycle-by-cycle basis).In one embodiment, for the predetermined amount of time after cold or the warm start, fault and control logic 870 are partly forbidden.Alternatively, when the SSC rising is lower than 3 volts (it produces in startup or at each place that begins that weakens the cycle usually), this protection is forbidden.(notice that the SSC after the energising (or CE enables) that resets raises and can raise than startup subsequently slow 150 times.) after startup, if (for example 4 times) continuous clock of specific quantity in the cycle OVP stitch then can discern this fault once by predetermined (for example, 250 millivolts) threshold value.In this mode, fault and control logic 870 can prevent that (spurious) under voltage causes unnecessary closing because single looks genuine.After partly forbidding the time, fault and control logic 870 can start once more fully.

The 3rd fault condition detection can be used for monitoring the electric current by CCFL fluorescent tube 805.Especially, for monitor current, can detect voltage at node N4 place.In one embodiment, the trigger voltage of node N4 is 250 millivolts.Fault and control logic 870 receive the CSDET signal from node N4.Therefore, fault and control logic 870 can be searched under-voltage state (fluorescent tube undercurrent) at node N4.Equally, weaken the special time period of all after dates, this fault detect can be under an embargo (be similar to node N6 under voltage detect) for each.In one embodiment, in fault and control logic 870 generation faults and before closing chip, fault and control logic 870 must receive 4 continuous under voltage operation cycles at node N4.Alternatively, when the SSC rising was lower than 3 volts, this protection can be under an embargo.

Note, in one embodiment, the resistive divider (referring again to the resistor 922 and 923 among Fig. 9) that comprises resistor 810 and 811 can be driven into the OVP stitch and surpass 250 millivolts but be lower than 3 volts voltage, forbid two fault condition detection relevant (that is, node N6 mistake and under-voltage state) thus effectively with the voltage that is provided to CCFL fluorescent tube 805.(noticing that in another embodiment, the capacitive divider (not shown) can be used for implementing and the voltage divider identical functions).Importantly, and can survey the open circuit fault usually by the 3rd relevant malfunction of the electric current of CCFL fluorescent tube 805, it can be used for some application.

Figure 11 illustrates a simple schematic diagram of fault and control logic 870.If the VDD power supply can be adjusted (within regulation), circuit produces signal VDDOK.If the VDD power supply can not be adjusted, then VDDOK is a logic zero signal, thus the logical one signal is offered the terminals R that resets of S-R trigger and inverter 1101.This logical one signal makes the Qbar output make the logical zero that outputs to of inverter 1101 to logical one.This logic zero signal is propagated the gate of passing through subsequently as the NORM signal.The NORM signal of logical zero makes output driver 880 (Fig. 8 A) invalid, if the VDD power supply is nonadjustable thus, then prevents 801 work of CCFL circuit.Weaken at burst mode during " pass " part in cycle, and when chip was under an embargo, if malfunction produces, then NORM was low.As previously mentioned, for the burst mode brilliance control, CHOP signal (being produced by comparator 862) stops the work of CCFL circuit 801.

The CLK signal is the clock output from VCO 850.The CLK signal is provided for the time basis of the door driving of external fet (similar PMOS transistor 803).The OVP signal (referring to Fig. 8 A) that produces at the node N5 place of CCFL circuit 801 is provided for two comparators, the comparator 1103 that promptly is used for determining superpotential comparator 1102 and is used for determining under voltage.The CSDET signal that node N4 place produces is provided for the comparator 1104 that is used to monitor the CCFL electric current.As previously mentioned, if predetermined times appears in these states, then under voltage and undercurrent state can trigger fault.Therefore, 2 digit counters can be coupled to the output of comparator 1103 and 1104, are convenient to the counting of continuous under voltage and undercurrent state thus.

The SSC signal, the voltage by capacitor control that promptly can get in system 800 raises and reference voltage (being 3.3 volts in this case) is provided for comparator 1105.In this structure, very low by the BLANK signal of comparator 1105 outputs when the SSC signal is lower than 3.3 volts, forbidden two fault detects relevant thus effectively with 2 digit counters.Therefore, the SSC signal can be used for forbidding providing time delay between two fault-finding detection periods.Notice that the output signal FIRST of fault and control logic 870 is very high during first after the opening power weakens the cycle, make the SSC stitch obtain (source) thus than still less electric current on the Burst Period subsequently.Weaken the beginning in cycle at each, SSC 0 volt initial and be elevated to the VDD power supply linearly, still, first after the energising raises than rising subsequently slow 150 times.

Fault and control logic 870 are gone back receiving chip and are enabled CE signal (on the line 872 of Fig. 8 A), and it produces the opening and closing of power supply reset condition and CCFL.Fig. 8 B illustrates the example of the circuit that is used to produce the CE signal.Especially, battery 802 and resistor 891 (resistance that for example, has 1 megohm) are used switch 893 optionally to be coupled to line 892.Switch 893 can be opened by the switch (all not shown) of microprocessor or user's control.Have between 894 connections online 892 of Zener diode characteristics (for example 3 volts nominal puncture voltage) device and the VSS, thus the voltage on the restraining line 892 after switch 893 is opened.Make the CE signal carry out the transition to height, have and the effect identical that reset of powering faulty circuit from low.Notice that among Figure 11, CE signal and VDDOK signal drive inputs that are used for making in two input NAND doors that rest-set flip-flop resets respectively in faulty circuit.When CE when low, its effect is low as VDDOK.It makes the Qbar of " first " trigger reset to " 1 ", and this expression is to start first after the power supply again to weaken the cycle behind deenergization in current cycle of weakening.It also resets to " 1 " with the Qbar of " NORM " trigger, and this represents that all faults have all been removed and operate as normal can continue.

Arc detection circuitry

Usually, when the impedance of load surpassed predeterminated level, overvoltage condition produced.Especially, if impedance is too high, then the electric current in CSDET stitch place sensing will drop under its threshold value, and circuit 801 will be closed.But, when CCFL fluorescent tube 805 and remaining bad contact of circuit, promptly when the connector of CCFL fluorescent tube 805 does not insert fully, produced another problem.

In this case, to such an extent as to it is easy to skip 1 mm clearance in the air by the voltage of transformer 814 generations height like this.Unfortunately, CCFL fluorescent tube 805 will still be worked under this state, produce electric arc between the connector of opening.If connector and CCFL fluorescent tube 805 disconnect enough distances (1 centimetre), then electric arc will not be problem.If it is connector correctly connects, then no problem equally.But (or in high voltage channel Anywhere) has very little gap in the connector, then can produce electric arc, produces the high temperature that is harmful to thus CCFL circuit 801 in.Therefore, the overvoltage condition that is produced by electric arc should as far as possible promptly detect, and when detecting, circuit should be closed.

As mentioned above, can survey overvoltage condition by working voltage (or electric capacity) distributor, it is connected to the secondary winding and the CCFL fluorescent tube 805 of transformer 814.Unfortunately, this distributor can change the AC characteristic of CCFL fluorescent tube 805, and therefore changes its resonance frequency.In addition, by increasing parts, distributor makes PC plate complex circuit designs.

Therefore, according to one embodiment of the present of invention shown in Figure 12, can provide non-invasive circuit 1200 to survey overvoltage.In this embodiment, as described with reference to figure 8A, resistor 821, capacitor 822 and error amplifier 823 are provided for proper integral and the FEEDBACK CONTROL (wherein, the same parts label among Fig. 8 A and 12 is identical) of CCFL805.The output of error amplifier 823 is COMP signals.

Advantageously, circuit 1200 can produce the OVP signal, has eliminated the needs to resistor 810 and 811 (Fig. 8 A) thus.Importantly, the high voltage end of the resistance of circuit 1200 and capacitive element and CCFL fluorescent tube 805 (being node N6) separates.Make resistance and capacitive element be exposed to so high voltage and understand the electric current and the energy that reduce undesirablely, lower efficiency thus by these parts.In addition, the high voltage at node N6 place can influence impedance, makes voltage detection become difficult thus.

N6 is opposite with node, and at the normal circuit duration of work, the COMP signal is without undergoing high voltage and common not obvious change.For example, even during the cycle of weakening, the rising of COMP signal and decline are level and smooth and do not have relative noise.But if produced electric arc, then when circuit made great efforts to keep rule, it is unstable that the COMP signal becomes.

Therefore, the detection of this instability of COMP signal performance can be used for shut-off circuit.In Figure 12, the COMP signal can be coupled to diode 1206 and 1207 by capacitor 1202.Diode 1206 and 1207 extracts voltages in the base stages of pnp transistor 1205, and the base voltage of the lower transistor 1205 of resistor 1203 trends.If the COMP signal moves erratically, then diode 1206 and 1207 extraction action can overcome the leakage effect of resistor 1203, and the voltage of the base stage of transistor 1205 and emitter will increase.The voltage at node N15 place can be provided for the OVP stitch in the CCFL system, is illustrated in whether there is overvoltage condition in the CCFL circuit thus.

The parts of circuit 1200 are worked in following mode.Receive the quick transition (for example, similar millisecond) of COMP signal by capacitor 1202.Anodal transition arrives the base stage of pnp transistor 1205 by transistor 1207.When pnp transistor 1205 the voltage at base stage place when increasing, the voltage at its emitter place also increases (it is by resistor 1208 and voltage VDD coupling).Diode 1207 hinders the negative pole transition, but at this transition period, diode 1206 will be conducted into capacitor 1202 by resistor 1208 from VDD.In the anodal transition of the next one, capacitor 1202 chargings and preparation are supplied into electric current the base stage of pnp transistor 1205.In this embodiment, resistor 1203 and capacitor 1204 are set up the time constant that is used for " fast " section transit time.At quick transition period, the voltage at the emitter place of pnp transistor 1205 will finally be increased to a bit, and at this point, it will disconnect the OVP threshold value of (trip) chip, close CCFL circuit 801 (Fig. 8 A) thus.

Survey between active stage and another method of shut-off circuit is to use preferred arc path at electric arc.For example, in an embodiment shown in Figure 13, PCB track 1310 can be very near (for example, in the 7-15mils) high voltage connector 1301 in CCFL fluorescent tube 805.In this structure, if CCFL fluorescent tube 805 does not use connector 1301 and 1302 (the 1302nd, to the low-voltage connector of CCFL fluorescent tube 805) suitably to place, the high voltage that then is applied on the connector 1301 will select jump gaps 1320 to arrive PCB track 1310, increase the voltage on the OVP stitch thus.Surpass preestablished limit (for example, 3 volts) when this voltage increases, then CCFL circuit 801 is closed.

Can realize different operating characteristic by the gap 1320 on the change PC plate and by the solder mask that disconnects on the zone between preferred electric arc node 1310 and the connector 1301.When make between node 1310 and the connector 1301 preferred arc gap 1320 more hour, the voltage that produces electric arc is also littler, because when two distance between electrodes reduce, the electric field between two electrodes of this of arc path increases (supposing that the potential difference between two electrodes is constant).Notice because to the gap 1320 of connector 1301 air as its dielectric, so the dielectric that air also usefulness is acted on preferred arc path is favourable.

Be used to make the circuit of transition minimum

Because the leakage inductance (Fig. 8 A) of transformer 814, the voltage of drain electrode place of nmos pass transistor 804 and 816 potentially the transition transition to than the higher value of ideal value (for example, twice cell voltage).In order to limit the extension of transition transient voltage, the CCFL system can comprise buffer circuit 913, as shown in Figure 9.In buffer circuit 913, capacitor 902, resistor 903 and diode 904 and 905 are configured to keep nominal voltage at its shared node N10.In one embodiment, this nominal voltage is the twice cell voltage approximately.But, if a transition transition in the drain electrode of nmos pass transistor 804/816 surpasses this voltage, then diode 904 and 905 forward biases and allow transition charge for capacitor 902.Resistor 903 is emitted extra transition energy, and preventing thus increases above nominal voltage at the voltage of common points N10.This extra power dissipation is:

P(dissipated)＝Vbatt ²/Resistance(903)

For example, suppose that it is 15 volts that resistor 903 has 3.9 kilo-ohms resistance and cell voltage, then the power dissipation of buffer circuit 913 will be 1% of 58 milliwatts or a total approximately input power.Therefore, the value of resistor 903 can be optimized application-specific and make the dissipation power minimum.

Notice that the amount of transition is the majorant of operating frequency.Therefore, be used for and advantageously select suitable resistance, thereby make the resonance frequency of oscillator frequency near transformer LC network for resistor 852.

A plurality of lamp tube drive circuits

Current LCD monitor needs a plurality of CCFL fluorescent tubes to provide it to use required high-strength light.Unfortunately, do not advocate,, and accelerate the fluorescent tube fault subsequently because the difference of the load characteristic of fluorescent tube can cause very big not the matching of lamp current with single bigger transformer fluorescent tube in parallel simply.Alternatively, in the application, single controller, single transformer can be used for each CCFL fluorescent tube; But it is surprisingly high that the cost of such application will become very soon.

Figure 14 illustrates circuit 1400, and it can drive the CCFL fluorescent tube (being CCFL fluorescent tube 805 and 1401) of two series connection, but has avoided above defective.Because CCFL fluorescent tube 805 and 1401 is connected, their electric current is basic identical.Notice that in actual applications, parasitic capacitance can cause lamp current inequality, dash (underscoring) thus down and make the approaching as far as possible needs of sneak path.

In circuit 1400, topological fundamental sum is used for the identical of CCFL system 800 (referring to Fig. 8 A).For example, consistent in PMOS transistor 803 and nmos pass transistor 804 and 816 structure and operation and the CCFL system 800.In addition, be used for determining the consistent of the feedback loop of the electric current by CCFL fluorescent tube 805 and CCFL system 800.Notice that feedback loop only needs to be coupled to CCFL fluorescent tube 805 because, as previously mentioned, as long as the parasitic capacitance path to two fluorescent tubes about equally, then the electric current in the CCFL fluorescent tube 1401 should with regular fluorescent tube, i.e. electric current unanimity in the CCFL fluorescent tube 805.Resistor 1402 can be adjusted the resistance sum that size equals resistor 807 and 808 substantially, guarantees that thus the impedance of CCFL fluorescent tube 805 and 1401 equates.

Illustrate in greater detail the geometry of the transformer 1410 of modification among Figure 15.In this geometry, the connection 1504 between two secondary winding 1501 and 1503 remains on low-voltage, for example, and ground.Opposite, alternatively be big cathode voltage and big cathode voltage (for example ,+600 volt with-600 volts) from the voltages of secondary winding 1501 and 1502 outputs.

In one embodiment, the mid point of connection 1504 between about secondary winding 1501 and 1503.As long as the load in the output of secondary winding 1501 and 1503 is equal substantially, then this structure has been eliminated the possibility that produces electric arc between elementary winding 1502 and secondary winding 1501 and 1503.In addition, the ceiling voltage on the secondary winding produces far as far as possible each other, has also reduced the electric arc danger in transformer thus.

Node 1504 is ideal positions of surveying the incipient fault state, and this malfunction produces by the fluorescent tube that lacks in the high voltage channel that produces electric arc or the connection (marginal connection) at edge.Send a telegraph equal normal running greatly for the CCFL load, the voltage at node 1504 places keeps closely.When produce fault (lack or destroy such as CCFL) in a secondary path, the voltage at node 1504 places will depart from ground connection widely.Voltage by by suitable resistive divider 1410 and adjustment diode 1411 (all illustrating in Figure 14) probe node 1504 places can detect potential risk of disturbance before the infringement to parts produces.The resistive divider voltage of adjusting can be directly connected to the OVP stitch (Fig. 8 C) of control IC 825.Resistive divider 1410 must adjust size in case the adjustment voltage of output place that makes diode 1411 in normal working conditions less than predetermined threshold at the comparator at the OVP of control IC 825 node place.In addition, resistive divider 1410 also must be adjusted size, thereby during nonserviceabling, the predetermined threshold voltage height of the comparator at the OVP stitch place of the voltage ratio control IC 825 of output place of diode 1411.In one embodiment, predetermined threshold is 3 volts.When the voltage rising at OVP stitch place is made on the predetermined threshold, as described in the discussion of front in faulty circuit, chip is closed.

Figure 16 A illustrates to be used to drive from 2 fluorescent tubes and extends to the constructed of 4 CCFL fluorescent tubes 1601,1602,1603 and 805.In this embodiment, a control IC is used for driving two transformers 1604 and 1605, and wherein transformer 1604 drives CCFL fluorescent tube 1601 and 1602, and transformer 1605 drives CCFL fluorescent tube 1603 and 805.Notice that transformer 1604 is that cross-couplings equates the right electric current of 4 fluorescent tubes by series connection with secondary connection of 1605.The right most of energy right with being delivered to another serially connected lamp tubes of energy is identical because complementary fluorescent tube, is delivered to serially connected lamp tubes to sharing same transformer core.If CCFL is similar each other and two transformers are also similar each other, then can basically identical by the lamp current of each fluorescent tube.Importantly, Control current is only surveyed by CCFL, and therefore to have only a control chip be necessary.

Figure 16 B illustrates the sensing circuit 1610 of the CCFL structure that is used to be coupled to Figure 16 A.Sensing circuit 1610 comprises that two resistive divider and coupling form two diodes of OR function, form complicated OVP signal thus.

Figure 16 C illustrates another embodiment, and wherein two primary coils 1629 and 1630 and 4 secondary coils 1625,1626,1627 and 1628 can be formed on the transformer core 1631.In this structure, transformer has zone line, first end and second end.Advantageously, can in zone line, provide low AC voltage (for example, VSS), can provide the first high AC voltage, can provide the second high AC voltage with second phase place at second end at first end with first phase place.Notice that the mid point of second winding is positioned at zone line.The AC voltage at one end place of the AC voltage of mid point and transformer is compared the low of nature.In one embodiment, first phase place is positive, and second phase place is born.First end can comprise first secondary winding and the second subprime winding that the output of first homophase is provided, but second end can comprise level winding and the 4th secondary winding for the third time that the output of second homophase is provided.Importantly, the phase place out-phase of the phase place of first homophase output and the output of second homophase.

Figure 16 D illustrates the exemplary physics realization of the schematic diagram shown in Figure 16 C.This structure provides lower cost and lower parts number.Notice that sensing circuit such as sensing circuit 1610, can be positioned at the common point (as the situation that two transformers are arranged) of two secondary winding.

Figure 16 E illustrates another embodiment, the primary coil 1641/1642 of wherein two amalgamations and 1643/1644 and secondary coil 1625,1626,1627 and 1628 can be formed on the transformer core 1631.The primary coil 1641/1642 and 1643/1644 of noticing amalgamation can provide than higher first grade coupled of independent primary coil.Figure 16 F illustrates the exemplary physics realization of the schematic diagram shown in Figure 16 E.Close-coupled on this is elementary advantageously makes transition minimize.Figure 16 G illustrates the sensing circuit 1660 of the CCFL structure that is used to be coupled to Figure 16 E.Sensing circuit 1660 comprises that two resistive divider and coupling form two diodes of OR function, form complicated OVP signal thus.

Figure 17 illustrates the parasitic capacitance path 1701 and 1702 of CCFL fluorescent tube 805 and 1401 respectively.Usually, owing to be coupled in (by parasitic capacitance path 1701 and 1702) with ground level, can loss by the electric current of CCFL fluorescent tube 805 and 1401.Therefore, for electric current (exemplary values) 6 milliamperes of the arrival at sensing resistor 807 places, must be at the electric current (promptly being connected to the end of transformer 1410) of the other end of CCFL fluorescent tube 805 above 6 milliamperes.Importantly, if parasitic capacitance path 1601 is different with 1702, then the whole lamp current in the CCFL fluorescent tube 805 and 1401 is all with different.Overtime (over time) and under this condition, CCFL fluorescent tube 805 and 1401 will dissimilate.Especially, because overcurrent, its light output is difference or a fluorescent tube even be driven into too early destruction obviously.Advantageously, according to one embodiment of present invention, the parasitic capacitance electric current can mate by place two CCFL fluorescent tubes 805 and 1401 in the same way on identical ground level.

Note, stated as with some parts of various numerals and have exemplary resistance or electric capacity.But the those skilled in the art in the present technique field are appreciated that in other embodiment, and these parts can have other and be worth and change performance output.Therefore, the invention is not restricted to the value of the embodiment that disclosed.

Claims (33)

1. a CCFL circuit is characterized in that, comprising:

The PMOS transistor;

First and second nmos pass transistors; And

High turn ratio transformer, wherein said transformer comprise having centre tapped primary coil, form the first and second elementary windings, and single secondary coil,

Wherein the PMOS transistor drain is connected to described centre cap, and the transistorized source electrode of described PMOS is connected to battery,

Wherein the drain electrode of first nmos pass transistor is connected to an end of the first elementary winding, and the drain electrode of second nmos pass transistor is connected to an end of the second elementary winding, and the source electrode of described first and second nmos pass transistors is connected to voltage source V SS,

The wherein said first elementary winding closely with the described second elementary winding coupled, and the wherein said first and second elementary windings loosely with the coupling of described secondary coil, produce effective leakage inductance thus; And

The CCFL fluorescent tube, wherein secondary coil is connected between voltage source V SS and the CCFL fluorescent tube.

2. CCFL circuit as claimed in claim 1 is characterized in that, also comprises:

Diode, it has the input that is connected to voltage source V SS and is connected to the centre tapped output of primary coil.

3. CCFL circuit as claimed in claim 1 is characterized in that the primary and secondary turn ratio is about 100.

4. CCFL circuit as claimed in claim 1 is characterized in that, primary inductance in about 150 microhenrys between 250 microhenrys.

5. CCFL circuit as claimed in claim 1 is characterized in that, also comprises:

Buffer circuit, it is connected to the transistorized element of drain electrode, PMOS and first and second elementary winding of nmos pass transistor.

6. CCFL circuit as claimed in claim 5, it is characterized in that, described buffer circuit comprises first and second diodes, capacitor and resistor, the input of first diode is connected to an end of the first elementary winding, the input of second diode is connected to an end of the second elementary winding, and the output of first and second diodes is connected to node, and described resistor and described capacitor are connected in parallel between described node and the described battery.

7. one kind is used for surveying superpotential detection circuit at the CCFL circuit, it is characterized in that described detection circuit comprises:

Receive the integrator of CCFL circuit output signal, described integrator is used to produce DC signal COMP, thereby the time average voltage fundamental sum reference voltage of output signal is equated;

First capacitor, it has first terminals that are connected to integrator output;

First diode, it has the input of second terminals that are connected to first capacitor;

Second diode, it has the output of second terminals that are connected to first capacitor;

The pnp transistor, it has the base stage of the output that is connected to first diode, the emitter of input that is connected to second diode and the collector electrode that is connected to voltage source V SS;

First resistor, it is connected between the output and voltage source V SS of first diode;

Second capacitor, it is connected between the output and voltage source V SS of first diode; And

Second resistor, it is connected between transistorized emitter of pnp and the voltage source V DD;

Wherein the transistorized emitter of pnp provides and is illustrated in the signal that whether produces overvoltage condition in the CCFL circuit.

8. detection circuit as claimed in claim 7 is characterized in that, constant settling time in flip-flop transition cycle of the output signal that described second capacitor and described second resistor are the CCFL circuit.

9. method of surveying overvoltage condition in the CCFL circuit is characterized in that described method comprises:

Provide configuration to produce the transistor of the detectable signal of expression overvoltage condition;

Use integrator that described transistor and CCFL circuit are separated;

Be provided for extracting first circuit of voltage in the transistorized base stage of pnp;

Be provided for second circuit at the transistorized base stage drain voltage of pnp,

If wherein the output signal of integrator moves brokenly, then extraction can overcome leakage, has increased the voltage and the detectable signal of transistor driving terminals thus.

10. method as claimed in claim 9 is characterized in that also being included as constant settling time in flip-flop transition cycle of the output signal of CCFL circuit.

11. be used for surveying the detection circuit of overvoltage condition, it is characterized in that described detection circuit comprises at the CCFL circuit:

The PCB track, it is formed within the 7-15mils (mil) of the high voltage connector of CCFL circuit, and described PCB track provides alternative arc path, and it can produce the detectable signal whether expression exists overvoltage condition.

12. be used to drive the CCFL system of the first and second CCFL fluorescent tubes, it is characterized in that described CCFL system comprises:

The PMOS transistor;

First and second nmos pass transistors; And

High turn ratio transformer, wherein said transformer comprises primary coil, and it has the centre cap that forms the first elementary winding and the second elementary winding, and secondary coil, and it has second centre cap that forms first secondary winding and second subprime winding,

Wherein the PMOS transistor drain is connected to described first centre cap and the transistorized source electrode of PMOS is connected to battery,

Wherein the drain electrode of first nmos pass transistor is connected to an end of the first elementary winding, and the drain electrode of second nmos pass transistor is connected to an end of the second elementary winding, and the source electrode of first and second nmos pass transistors is connected to voltage source V SS,

Wherein the first elementary winding closely with the second elementary winding coupled, and wherein the first and second elementary windings loosely with secondary coil coupling, produce effective leakage inductance thus, and

Normal work period wherein, second centre cap remains on the voltage near voltage source V SS;

The one CCFL fluorescent tube can be coupling between first secondary winding and the voltage source V SS; And

The 2nd CCFL fluorescent tube can be coupling between second subprime winding and the voltage source V SS.

13. CCFL as claimed in claim 12 system is characterized in that, also comprises feedback control loop, it is used for determining only by a CCFL lamp tube current.

14. CCFL as claimed in claim 12 system is characterized in that, also comprises

At least the first resistor, it is connected between a CCFL fluorescent tube and the voltage source V SS; And

Second resistor, it is connected between the 2nd CCFL fluorescent tube and the voltage source V SS,

Wherein at least the first resistor and second resistor provide essentially identical resistance, guarantee that thus the impedance of the first and second CCFL fluorescent tubes is basic identical.

15. CCFL as claimed in claim 12 system is characterized in that an end of first and second secondary winding provides big cathode voltage and big cathode voltage respectively.

16. CCFL as claimed in claim 15 system is characterized in that second centre cap places half place of pact between first and second secondary winding.

17. CCFL as claimed in claim 15 system is characterized in that, if produce fault, then second centre cap provides the voltage different with voltage source V SS.

18. CCFL as claimed in claim 17 system is characterized in that, also comprises:

Resistive divider, it is connected to second centre cap; And

Diode, it is connected to resistive divider.

19. be used to drive the CCFL system of the first, second, third and the 4th CCFL fluorescent tube, it is characterized in that described CCFL system comprises:

The PMOS transistor;

First and second nmos pass transistors;

The first high turn ratio transformer, wherein the first high turn ratio transformer comprises having centre tapped first primary coil, forms the first elementary winding and the second elementary winding and first secondary coil, it has first secondary winding and second subprime winding;

The second high turn ratio transformer, the wherein said second high turn ratio transformer comprise having second centre tapped second primary coil, form the 3rd elementary winding and the 4th elementary winding and second subprime coil, and it has level winding and the 4th secondary winding for the third time,

Wherein the PMOS transistor drain is connected to first and second centre caps, and the transistorized source electrode of PMOS is connected to battery,

Wherein the drain electrode of first nmos pass transistor is connected to an end of the first elementary winding and an end of the 3rd elementary winding, the drain electrode of second nmos pass transistor is connected to an end of the second elementary winding and an end of the 4th elementary winding, and the source electrode of first and second nmos pass transistors is connected to voltage source V SS

Wherein the first elementary winding tightly with the second elementary winding coupled, and the 3rd elementary winding tightly with the 4th elementary winding coupled, and wherein the first and second elementary windings loosely are coupled with first secondary coil, and the third and fourth elementary winding loosely is coupled with the second subprime coil, produces effective leakage inductance thus;

The one CCFL fluorescent tube is coupling between first secondary winding and the voltage source V SS;

The 2nd CCFL fluorescent tube is coupling between second subprime winding and the voltage source V SS;

The 3rd CCFL fluorescent tube is coupling in for the third time between level winding and the voltage source V SS; And

The 4th CCFL fluorescent tube is coupling between the 4th secondary winding and the voltage source V SS,

Wherein first is connected with the 4th secondary winding and out of phase twines each other, and

Second with for the third time the level winding is connected and each other out of phase the winding.

20. CCFL as claimed in claim 19 system is characterized in that, also comprises the current sense network, a coupling in it and the first, second, third and the 4th CCFL fluorescent tube.

21. CCFL as claimed in claim 20 system is characterized in that, also comprises faulty circuit, he and second subprime winding and level winding coupled for the third time.

22. CCFL as claimed in claim 21 system is characterized in that described faulty circuit comprises:

First resistive divider;

Second resistive divider;

First diode, it and first resistive divider are coupled; And

Second diode, it and second resistive divider are coupled, and wherein connecting first and second diodes provides the logical "or" function for fault-sensing circuit.

23. the method for the malfunction of a detection system, described system comprise transformer, a CCFL fluorescent tube and the 2nd CCFL fluorescent tube with primary coil and secondary coil, it is characterized in that described method comprises:

In secondary coil, set up tap, thereby form first secondary winding and second subprime winding;

The one CCFL fluorescent tube is connected to an end of first secondary winding;

The 2nd CCFL fluorescent tube is connected to an end of second subprime winding; And

Determine the voltage of tap place.

24. method as claimed in claim 23 is characterized in that, determines that in tap place the step of voltage comprises distribution and adjusts voltage.

25. method as claimed in claim 24 is characterized in that, described distribution voltage comprises the size of adjusting resistive divider, thereby makes:

Under normal operating condition, adjust voltage less than the first predetermined threshold voltage; And

During nonserviceabling, adjust voltage and be higher than the second predetermined threshold voltage.

26. be used to drive the CCFL system of the first, second, third and the 4th CCFL fluorescent tube, it is characterized in that described CCFL system comprises:

The PMOS transistor;

First and second nmos pass transistors;

High turn ratio transformer, wherein said high turn ratio transformer comprises:

Have centre tapped primary coil, it forms the first elementary winding and the second elementary winding;

Secondary coil, it has first secondary winding, second subprime winding, level winding and the 4th secondary winding for the third time;

Wherein the PMOS transistor drain is connected to centre cap, and the transistorized source electrode of PMOS is connected to battery,

Wherein the drain electrode of first nmos pass transistor is connected to an end of the first elementary winding, and the drain electrode of second nmos pass transistor is connected to an end of the second elementary winding, and the source electrode of first and second nmos pass transistors is connected to voltage source V SS,

Wherein the first elementary winding tightly with the second elementary winding coupled, and wherein the first and second elementary windings loosely with the first, second, third and the 4th secondary coil coupling, produce effective leakage inductance thus;

The one CCFL fluorescent tube is coupling between the end and voltage source V SS of first secondary winding;

The 2nd CCFL fluorescent tube is coupling between the end and voltage source V SS of second subprime winding;

The 3rd CCFL fluorescent tube is coupling in for the third time between the end and voltage source V SS of level winding; And

The 4th CCFL fluorescent tube is coupling between the end and voltage source V SS of the 4th secondary winding,

Wherein the other end of first and second secondary winding connects and out of phase twines each other, and

Wherein the other end of third and fourth secondary winding connects and out of phase twines each other.

27. CCFL as claimed in claim 26 system is characterized in that, also comprises the current sense network, a coupling in it and the first, second, third and the 4th CCFL fluorescent tube.

28. be used to drive the CCFL system of the first, second, third and the 4th CCFL fluorescent tube, it is characterized in that described CCFL system comprises:

The PMOS transistor;

First and second nmos pass transistors;

High turn ratio transformer, wherein said high turn ratio transformer comprises:

Primary coil, it has first centre cap that forms the first elementary winding and the second elementary winding and second centre cap that forms the 3rd elementary winding and the 4th elementary winding;

Secondary coil, it has first secondary winding, second subprime winding, level winding and the 4th secondary winding for the third time;

Wherein the PMOS transistor drain is connected to first and second centre caps, and the transistorized source electrode of PMOS is connected to battery,

Wherein the drain electrode of first nmos pass transistor is connected to an end of the first elementary winding and an end of the 3rd elementary winding, the drain electrode of second nmos pass transistor is connected to an end of the second elementary winding and an end of the 4th elementary winding, and the source electrode of first and second nmos pass transistors is connected to voltage source V SS

Wherein the first elementary winding tightly with the second elementary winding coupled, the 3rd elementary winding tightly with the 4th elementary winding coupled, the first and second elementary windings loosely are coupled with first and second secondary coils, and the third and fourth elementary winding loosely is coupled with third and fourth secondary winding, produces effective leakage inductance thus;

The one CCFL fluorescent tube is coupling between the end and voltage source V SS of first secondary winding;

The 2nd CCFL fluorescent tube is coupling between the end and voltage source V SS of second subprime winding;

The 3rd CCFL fluorescent tube is coupling in for the third time between the end and voltage source V SS of level winding; And

The 4th CCFL fluorescent tube is coupling between the end and voltage source V SS of the 4th secondary winding,

Wherein the other end of first and second secondary winding connects and out of phase twines each other, and

Wherein the other end of third and fourth secondary winding connects and out of phase twines each other.

29. CCFL as claimed in claim 28 system is characterized in that, also comprises the current sense network, a coupling in it and the first, second, third and the 4th CCFL fluorescent tube.

30. a method that realizes transformer, described transformer have zone line, first end and second end, described method is characterized in that, comprising:

Provide low AC voltage at zone line;

The first high AC voltage with first phase place is provided at first end;

The second high AC voltage with second phase place is provided at second end; And

The mid point of secondary winding is placed nearly zone line place, wherein compare inevitable on the low side with the first and second high AC voltages at the AC of mid point voltage.

31. method as claimed in claim 30 is characterized in that, described low AC voltage is VSS.

32. method as claimed in claim 30 is characterized in that, described first phase place is positive and second phase place is born.

33. method as claimed in claim 30, it is characterized in that, described first end comprises first winding and second winding that the output of first homophase is provided, described second end comprises the tertiary winding and the 4th winding that the output of second homophase is provided, and the phase place of the phase place of described first homophase output and the output of second homophase is an out-phase.

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