CN1497603A - Magnetic random access storage and its data write method - Google Patents

Abstract

In an MRAM having main and sub-structures, selecting transistors are arranged so as to meet the arrangement order of main word lines, sub-word lines and the selecting transistors. The selecting transistor is driven to cause a snap back phenomenon to occur. As a result, data can be written to a memory cell using a substrate current, not a channel current. Moreover, a data may be written into a selected memory cell by discharge the charge which is charged in the main and sub word lines corresponding to the memory cell.

Description

Magnetic RAM and method for writing data thereof

Technical field

The present invention relates to a kind of magnetic RAM (MRAM) and method for writing data thereof.

Background technology

In recent years, because MRAM has superintegrated magnetic material as storage unit on substrate, and MRAM has non-volatile characteristic, high speed operation and the anti-repeatability of magnetic recording, therefore, expected MRAM as storer of future generation.

Fig. 7 A and 7B are used separately as the basic structure of the storage unit of explaining MRAM and the skeleton view of operation.

Shown in Fig. 7 A, mram cell comprises: make and have latch layer 12 (pinned layer), the insulation course 13 of fixing direction of magnetization and the data storage layer of being made by ferromagnetic film 14 by ferromagnetic film.This mram cell is arranged on down between distribution (lower wiring) 11 and the last distribution (upper wiring) 15.

Fig. 7 B is used for explaining the skeleton view that writes data into storage unit shown in Fig. 7 A and the operation of sense data from the storage unit shown in Fig. 7 A.

Carry out the storage of data by utilizing " magnetoresistance ", wherein, the direction of magnetization of the state (corresponding to data " 0 ") of " parallel " and latch layer 12 and data storage layer 14 is mutually between the state of " antiparallel " (corresponding to data " 1 ") mutually in the direction of magnetization of latch layer 12 and data storage layer 14 for the resistance of dielectric film, and the amount with 30% to 40% changes.By making scheduled current pass through the external magnetic field of last distribution 15 and 11 generations of following distribution, change the direction of magnetization of data storage layer 14, thereby store such as binary data.

Be used for from the operation of storage unit sense data as follows: predetermined potential difference (PD) is applied between distribution 15 and the following distribution 11, so that produce tunnel current 16.This tunnel current 16 passes latch layer 12, insulation course 13 and data storage layer 14, so that it flows to distribution 15 from following distribution 11.Thereby, can be from storage unit sense data.That is to say, when the direction of magnetization of two ferromagnetic layers 12 that insulation course 13 is clipped in the middle and 14 is that be parallel to each other or mutual when antiparallel, because tunnel magneto-resistance effect changes the magnetic resistance value of insulation course 13.Then, detect this variation in electric current, thereby the data that will store read into the outside in storage unit.

Fig. 8 is used for explaining when the storage unit shown in Fig. 7 A and the 7B is arranged in array the synoptic diagram of the write operation of MRAM.

At this moment, will be described at the situation that writes data into storage unit MC.When wanting to write data into storage unit MC, make predetermined current (write current C1 and C2) flow through word line W112 and bit line B152 selectively, thereby by utilizing the resultant magnetic field M12 that obtains synthesize in the magnetic field (magnetic field M1 and M2) of induction around distribution, the magnetic domain of the data storage layer of storage unit MC is controlled in one direction.Thereby, realized writing data into the operation of storage unit MC.

On the other hand, for opposite data (inverted data) are stored among the storage unit MC, with respect to the situation that writes data into the operation of storage unit MC described above, selectively to flow through one of them of word line W112 and bit line B152, the direction of for example bit line B152 of electric current carried out oppositely.Therefore, change 180 degree, can make the direction of resultant magnetic field M12 change 90 degree, thereby can make the direction of the magnetic domain in the data storage layer of storage unit MC reverse by force by the direction that makes magnetic field M2.As a result, by utilizing the external magnetic field, can realize " parallel " and " antiparallel " of the magnetic domain direction of latch layer and data storage layer.

As mentioned above, in the mram memory cell array, the electric current of storage unit that is positioned at the intersection point of selected word line and bit line to flowing through detects, so that judge store status.Yet if the scale of memory cell array self increases, the wiring resistance of word line and bit line and distribution electric capacity also correspondingly increase.As a result, when sense data from storage unit, the detected current value that flows through diminishes, and perhaps the operating lag when sense data therefrom increases.

Especially, owing to storage unit is made of the thick dielectric film of the about 2nm (nanometer) that is clipped in two-layer ferromagnetic film, therefore, for the principal ingredient of distribution electric capacity, because the electric capacity that the storage unit that is connected with distribution forms is greater than the electric capacity of distribution self.Thereby if the quantity of the storage unit that is connected with distribution increases, then wired electric Rongcheng ratio ground increases.

For fear of such problem, the measure that classic method adopts is: for example, for wiring resistance is provided with the upper limit, thereby the current level when making from storage unit sense data can be less than predetermined value, increase for fear of distribution electric capacity, length to distribution limits, so that limited the scale of memory cell array, or the like.

Yet,, must increase the scale of memory cell array along with the increase of the capacity of MRAM.Therefore, this problem becomes more and more important.

In order to solve such problem, proposed to cut apart the suggestion of memory cell array.

Fig. 9 schematically shows such configuration, and Fig. 9 is the circuit diagram that the sub-memory cell array that is made of to SWm and sub-bit-line SB1 to SBn sub-word line SW1 is shown.

The sub-word line SW1 that constitutes sub-memory cell array selects transistor WT1 to WTm by sub-word line respectively to SWm, and W1 is connected to Wm with main word line.Sub-bit-line SB1 selects transistor BT1 to BTn by sub-bit-line respectively to SBn, and B1 is connected to Bn with main bit line.In this manner, memory cell array is configured to the form (with reference to such as JP2002-170379A (Fig. 1)) of the hierarchy of main bit line and main word line and sub-bit-line and sub-word line.

As mentioned above, MRAM has the high-performance that rewrites and read such as at a high speed.Yet, on the other hand, because when planning to write data, make the electric current corresponding distribution of flowing through, so that produce induced field, therefore, each storage unit need sizable write current, i.e. several milliamperes write current.If when adopting the method that traditional memory cell array is divided into piece to avoid the problems referred to above, may run into the following problem that will describe.As mentioned above, cell array cut apart the employing hierarchy, this hierarchy has the main bit line that covers the whole unit array distribution and main word line and the only sub-bit-line and the sub-word line of distribution each piece (subelement array) in.Then, need common MOS transistor as switching device, so that main bit line and main word line are transferred on sub-bit-line and the sub-word line.In by each piece of cutting apart acquisition, form such switching device, so that respectively main bit line and main word line are switched on sub-bit-line and the sub-word line.In MRAM, the electric current when writing data is corresponding, need have the ability that the electric current that makes several milliamperes of level flows through as the MOS transistor of switching device.As is known, MOS transistor can make the electric current with the amplitude that is inversely proportional to its length (L) with width (W) ratio of grid flow through.Therefore, if determined the length breadth ratio of grid, and, then will therefrom determine the length of needed gate electrode and the absolute value of width inevitably for to have determined certain design conditions as the MOS transistor of switching device.Usually, W need be arranged in about scope of 10 to 50 with the ratio of L, so that several milliamperes electric current is flow through.Therefore, for example, have the MOS transistor device that L is 0.2 μ m if want to form, then W is necessary for 2 to 10 μ m.

Summary of the invention

Consider above-described problem, therefore, the objective of the invention is to propose a kind of magnetic storage (MRAM) with storage unit of use tunnel magnetoresistance element (TMR element) formation, this can realize novel array structure, operation and more small floor plan.

According to one aspect of the present invention, a kind of MRAM has been proposed, comprising: first distribution makes write current flow according to a direction by it; Select transistor, it is arranged on the downstream of the write current of first distribution; And a plurality of mram cells, it is set at upstream side with respect to the transistorized position of selection that is arranged in first distribution.The other end of mram cell is connected with second distribution, by wherein said second distribution electric current is flowed according to both direction.First distribution be not by transistor and with the first main wiring direct-connected first sub-distribution; Second distribution is the second sub-distribution that connects by transistor AND gate second main wiring.First and second main wirings are respectively main bit line and main word line, and the first and second sub-distributions are respectively sub-bit-line and sub-word line.

More particularly, with respect to will only being arranged on the traditional arrangement (with reference to figure 9) of the end of sub-memory cell array as the MOS transistor switching transistor of the switching device of memory cell array, according to the present invention, will arrange on the contrary as the MOS switching transistor of switching device.Then, main bit line directly is connected mutually with sub-word line with sub-bit-line or main word line.Switching transistor is arranged, so that satisfy putting in order of mutual main bit line, sub-bit-line and switching transistor of connecting.Since can the current conductive state of switching transistor be controlled by the electric current of the element of these series connection of flowing through, therefore, can the chooser memory cell array.In addition, different according to the present invention with above description about prior art, in the operation of switching transistor, do not utilize according to the width of grid and the channel current of length, and adopted the electric current (substrate current) that flows to Semiconductor substrate from drain diffusion layer.Can will be applied to so-called snap back (snap back) electric current that flows through in the drain electrode as described substrate current by being near the voltage breakdown voltage.In other words, the principle of work when making transistor turns has been utilized the junction breakdown of drain electrode or the electric current that flows according to the direction from the substrate that drains, and with because whether irrelevant the existence that the raceway groove of the grid of common MOS transistor forms is.

As mentioned above, in the present invention,, therefore, prevent that write current is subjected to selecting the control of transistorized channel current because the transistor that will select is arranged on the downstream of distribution.More particularly, in the present invention, do not use the channel current of switching transistor, and be to use substrate current.Therefore, can make big electric current flow through less transistor area, and have nothing to do with the width W of raceway groove and the ratio of length L.As a result, according to the present invention, can reduce the area of memory cell array.

In addition, in the present invention, normal D.C. (direct current) current stabilization ground is flow through.As an alternative, stored charge in the electrostatic capacitance of main bit line, and by making the switching transistor conducting, suddenly the electric charge of wherein accumulation is discharged according to the form of discharge current.Then, can write data in the storage unit by utilizing discharge current.

In the present invention, make predetermined write current flow through respectively word line and bit line, so that around word line and bit line, induce magnetic field, thereby, binary data 0 or 1 is stored in storage unit on the intersection point between word line and the bit line according to the magnetic field of induction.

Storage unit of the present invention is the memory element that is made of the magnetoresistive element with at least three layers, wherein said three layers comprise: first and second magnetic thin films and be clipped in dielectric film between first and second magnetic thin films, this memory element is used for according to the variation of the tunnel resistor in the insulation course, therein stores binary data 0 or 1.At this moment, the variation of the tunnel resistor in the dielectric film depends on because the variation of magnitude of external magnetic field, and the direction of magnetization of first and second ferromagnetic thin films is parallel to each other, or antiparallel mutually.

It is MOS transistor (for example n type) that word line of the present invention is selected transistor and bit line selection transistor, and these transistorized gate electrodes are connected with the bit line select signal line with the word line selection signal line respectively, so that according to word line selection signal and bit line select signal it is controlled.MRAM of the present invention can have by the shared write circuit of a plurality of sub-memory cell arrays and read circuit.What comparatively need is to have to make switching transistor become the synchronous assembly (unit) of the moment of conducting, thereby makes electric current flow through simultaneously word line and bit line.What comparatively need is to adopt the drain diffusion layer of switching transistor to have the structure of quite low voltage breakdown.

According to the present invention, a kind of method for writing data that is used to comprise the MRAM of TMR unit is provided, wherein,, write data in the TMR unit of a correspondence by using the snap back electric current.

According to the present invention, a kind of method for writing data that is used to comprise the MRAM of TMR unit has been proposed, may further comprise the steps: stored charge in one of them electrostatic capacitance of word line and bit line; And the form according to discharge current is discharged to the electric charge that accumulates, so that by using discharge current, write data into one of them of TMR unit.

Description of drawings

Fig. 1 is the circuit diagram that illustrates according to the MRAM of the first embodiment of the present invention;

Fig. 2 is the figure of the operation of schematically illustrated selection transistor WT shown in Figure 1;

Fig. 3 is the graphical representation that is used for explaining the write current of device shown in Figure 1;

Fig. 4 is the circuit diagram that illustrates according to the MRAM of the second embodiment of the present invention;

Fig. 5 is the circuit diagram that illustrates according to the MRAM of the third embodiment of the present invention;

Fig. 6 is the circuit diagram that illustrates according to the MRAM of the fourth embodiment of the present invention;

Fig. 7 A and 7B are the skeleton views that is used for explaining the structure and the storage operation thereof of mram cell;

Fig. 8 is used for explaining the synoptic diagram that data is write the method for mram cell;

Fig. 9 is the circuit diagram that traditional mram cell array is shown.

Embodiment

Fig. 1 is the circuit that illustrates according to the sub-memory cell array SMA1 of the MRAM of first embodiment of the invention.

Sub-memory cell array SMA1 comprises: many main word line W1 to Wm (m: be equal to, or greater than 2 natural number) and many main bit line B1 to Bn (n: be equal to, or greater than 2 natural number).Main word line W1 distributes according to the mode of intersecting in main bit line B1 to Bn to Wm.

Sub-word line SW1 to SWm according to distributing to the parallel mode of WM with main word line W1 respectively.Sub-word line SW1 connects to Wn with corresponding main word line W1 respectively to the end of SWm, and the other end be used for selecting the word line of a word line to select an end (corresponding drain terminal) connection of transistor WT1 to WTm in sub-memory cell array.Word line selects transistor WT1 to be connected with the first word line selection wire WSL1 to all grids of WTm.When wanting, the word line selection signal that is activated is offered word line selection wire WSL1 with the data write storage unit.Word line selects transistor WT1 to be connected with ground wire to the every other end of WTm.In addition, sub-word line SW1 to other ends of SWm respectively with read the corresponding end of transistor RT1 and connect to RTm.Reading transistor RT1 is connected with sensor amplifier SA1 to the every other end of RTm.Be provided and read reading signal wire RSL1 and reading transistor RT1 each in the RTm grid and be connected of signal.

Sub-bit-line SB1 to SBn according to distributing to the parallel mode of Bn with main bit line B1 respectively.Sub-bit-line SB1 to the end of SBn by the bit line selection transistor BT1 that is used for selecting a bit lines in sub-memory cell array to BTn, connect to BTn with corresponding main bit line BT1 respectively.Bit line selection transistor BT1 is connected with the first bit line selection wire BSL1 to all grids of BTn.When planning during sense data, the bit line select signal that is activated to be offered bit line selection wire BSL1 the data write storage unit and from storage unit.Sub-bit-line SB1 is connected with write circuit K1 to the every other end of SBn.Write circuit K1 comprises: the first group transistor KD1 to KDn and the second group transistor KE1 to KEn.Write control line D0 according to first, the first group transistor KD1 is controlled to KDn, wherein, when writing data and become such as level " 1 ", activate this and first write control line D0, and first write control line D0 and provide first to write data controlling signal to this.Write control line E0 according to second, the second group transistor KE1 is controlled to KEn, wherein, when writing data and become such as level " 0 ", activation second writes control line E0, and writes control line E0 to second and provide second to write data controlling signal.

Word line selects transistor WT1 to be made of MOS transistor respectively to BTn to WTn and bit line selection transistor BT1.

The operation of cell array of the present invention is described below with reference to Fig. 1.In this case, will be described at the situation of the storage unit C11 that writes data into the first sub-memory cell array SMA1.

At first, select word line W1, will select signal to be input to the first word line selection wire WSL1 then, so that make word line select transistor WT1 conducting.Other all main word line W2 except the word line W1 that selects do not have selected to Wm.As a result, selected the sub-word line SW1 that is connected with main word line W1.Then, by using, make the write current main word line W1 that flows through such as the constant current source (not shown).Write current, flows to word line and selects transistor WT1 by sub-word line SW1 from main word line W1.Simultaneously, select main bit line B1, will select signal to be input to the first bit line selection wire BSL1 then, so that make bit line selection transistor BT1 conducting.All main bit line B2 of except main bit line B1 other do not have selected to Bn.As a result, selected the sub-bit-line SB1 that is connected with main bit line B1.On the other hand, in write circuit K1,, make transistor KE1 be in conducting state, and make transistor KD1 be in not conducting state by the signal of suitable introducing.If in this state, the write current that provides from the constant current source (not shown) main bit line B1 that flows through is provided, then make write current from main bit line B1 by bit line selection transistor BT1, flow to sub-bit-line SB1.On the other hand, when will the data different being written to storage unit C11, making transistor KE1 be in not conducting state, and make transistor KD1 be in conducting state with aforementioned data.As a result, make write current pass through bit line selection transistor BT1, flow to main bit line B1 from sub-bit-line SB1.

When wanting to write data into storage unit, make several milliamperes the electric current word line of flowing through select the transistor of the correspondence of transistor WT1 in the WTm.In this case,, do not utilize the channel current a of common MOS transistor, and utilized the electric current b (with reference to figure 2) that from drain electrode, promptly flows to substrate with the terminal that sub-word line SW1 connects to the corresponding sub-word line the SWM for this electric current.

Fig. 3 shows the characteristic of such substrate current.

Fig. 3 illustrates the drain voltage (V) (abscissa axis) of MOS transistor and the characteristic curve of the relation between its drain current (A) (axis of ordinates), wherein grid voltage is used as the parameter in 0V arrives the 7V scope.From these characteristic curvees, can appreciate that when drain voltage to remain when low, the channel current of MOS transistor is flow through, and when drain voltage becomes big, substrate current is flow through.Can find: when grid voltage uprises,, also be easy to occur this phenomenon even drain voltage is relatively low.This phenomenon is become so-called snap back (snap back) phenomenon.Because following process, this snap back phenomenon has appearred, that is, and by high voltage is applied in the drain electrode,

1) near drain electrode impact ionization has appearred,

2) make the hole flow into substrate,

3) make the biasing of source electrode and substrate forward ground,

4) make a large amount of electronics flow to substrate from source electrode, and

5) near drain electrode, impact ionization further occurs,, thereby provide the positive feedback state so that the hole flows into substrate.

In brief, in the snap back phenomenon, make the parasitical bipolar transistor conducting of have source electrode (emitter), substrate (base stage) and drain electrode (collector), make source electrode arrive drain break down, thereby reduce drain voltage and show negative resistance.In this phenomenon, along with shortening of grid length, the voltage of generation further reduces.And, if this phenomenon then makes the current direction substrate.Yet, because this electric current is not the electric current of raceway groove of common MOS transistor of flowing through,, big electric current is flow through even under the situation of minitransistor, and not proportional with the ratio of channel width and channel length.For this reason, when the present invention being applied to when being used to select the transistor of word line or bit line,, bigger electric current is flow through even MOS transistor has the layout of quite little area.

For example, when planning to write data into storage unit C11, appear among the transistor WT1 of selection in order to make the snap back phenomenon, according to characteristic shown in Figure 3, will the voltage in 4.2 to 7.0V (volt) scope for example voltage 4.2V be applied to main word line W1 so that write current therefrom flows through.Simultaneously, with predetermined voltage for example the voltage of 4.2V also be applied to main bit line B1.Above-mentioned voltage is applied to word line selection wire WSL1 and bit line selection wire BSL1 respectively with the form of pulse, so that electric current therefrom flows through.

Do not have selecteed other word lines to be connected with ground, perhaps be applied in the voltage that the snap back phenomenon is occurred, thereby write current is therefrom flow through with bit line.As shown in Figure 3, for example, greater than 0V but less than the voltage of 4.2V corresponding to the voltage that the snap back phenomenon is occurred.Usually, because the withstand voltage 1.5V that is approximately of TMR element, when the voltage of main word line that is applied to selection and main bit line was 4.2V, preferably will be applied to the voltage in the 3.7V scope at 2.7V did not have selecteed word line and bit line.This voltage is " voltage that the snap back phenomenon is occurred ".Because related electric current does not reach the needed level of magnetic reversal (magnetic inversion), then can in the TMR element, not occur disturbing, therefore, such voltage can be set.

Up to the present,, be described at the method that writes data into the storage unit C11 on the intersection point between sub-word line SW1 and the sub-bit-line SB1.

When from storage unit for example during the storage unit C11 sense data of the first sub-memory cell array SMA1, only select main bit line B1 so that apply to it and to read voltage, and do not select other main bit lines except main bit line B1.

Make and read electric current and read and select transistor RT1 from flow through sub-bit-line SB1, storage unit C11, sub-word line SW1 and word line of the main bit line B1 that selects.Then, will read electric current and offer sensor amplifier SA1, thereby it will be detected.

Fig. 4 is the circuit diagram that illustrates according to the MRAM of the second embodiment of the present invention.

Fig. 4 illustrates the memory cell array of the MRAM of the present invention that wherein is arranged with a plurality of sub-memory cell arrays shown in Figure 1.In the present embodiment, arrange, and wherein only show subelement array SMA1 to SMA3 according to matrix antithetical phrase memory cell array.In order to be reduced at the description of this omission to the details aspect of sub-memory cell array SMA1 shown in Figure 1.

Sub-memory cell array SMA1 and sub-memory cell array SMA2 have common main word line W1 to Wn.Sub-memory cell array SMA2 comprises: main bit line Bh is to Bj (h, j: be equal to, or greater than 2 natural number, n＜h, h＜j); The sub-bit-line SB21 that distributes accordingly to Bj with main bit line Bh is to SB2n; The sub-word line SW21 that distributes accordingly to Wm with main word line W1 is to SW2m; And, be arranged in the storage unit of sub-word line SW21 on to SW2m and sub-bit-line SB21 to the intersection point between the SB2n.That is to say that sub-word line SW11 and SW21 have common main word line W1.Therefore, the storage unit C11 of sub-memory cell array SMA1 has common main word line W1 to the storage unit C1h of C1n and sub-memory cell array SMA2 to C1j.And sub-memory cell array SMA2 also comprises: select transistor BT2h to BT2j, it is controlled, so that make its conducting by bit line selection wire BSL1; Select transistor WT21 to WT2m, it is controlled, when wanting to write data into storage unit, make its conducting by the word line selection wire WLS2 that is activated with box lunch; And read line selection wire RSL2, when wanting from storage unit sense data, activate this read line selection wire RSL2.In addition, similar to sub-memory cell array SMA1, sub-memory cell array SMA2 also comprises write circuit K2.

Sub-memory cell array SMA1 and sub-memory cell array SMA3 have common main bit line B1 to Bn.Sub-memory cell array SMA3 comprises: main word line Wg is to Wk (g, k: be equal to, or greater than 2 natural number, m＜g, g＜k); The sub-word line SW3g that distributes accordingly to Wk with main word line Wg is to SW3k; The sub-bit-line SB31 that distributes accordingly to Bn with main bit line B1 is to SB3n; And be arranged on the storage unit of sub-word line SW3g on to SW3k and sub-bit-line SB31 to the intersection point between the SB3n.And sub-memory cell array SMA3 comprises: select transistor BT31 to BT3n, it is controlled, so that make its conducting by bit line selection wire BSL2; Select transistor WT3g to WT3k, it is controlled, when wanting to write data into storage unit, make its conducting by the word line selection wire WSL1 that is activated with box lunch; And read selection wire RSL1, when wanting from storage unit reading of data, activate this and read selection wire RSL1.

To be described at the operation of the storage unit C11 that writes data into sub-memory cell array SMA1 below.

Select main word line W1, and to the first word line selection wire WSL1 input select signal, so that word line is selected transistor WT11 conducting.Other main word lines W2 except main word line W1 does not have selected to Wm.Non-selected signal is input in other word line selection wires except the first word line selection wire WSL1 each, so that connected word line selects transistor to reach not conducting state.As a result, only with sub-word line that main word line W1 links to each other in chooser word line SW11.Then, when making write current flow through main word line W1, then make write current flow to the sub-word line SW11 of selection, and selected word line is selected transistor WT11 from the main word line W1 that selects.On the other hand, meanwhile, select main bit line B1, and will select signal to be input to the first bit line selection wire BSL1, so that bit line selection transistor BT11 conducting.Other main bit lines except main bit line B1 do not have selected.And, non-selected signal is input to each bar in other bit line selection wires except the first bit line selection wire BSL1, so that connected bit line selection transistor reaches not conducting state.As a result, only with sub-bit-line that main bit line B1 is connected in selected sub-bit-line SB11.Then, when making write current flow through main bit line B1, make this write current flow to selected sub-bit-line SB11 and selected bit line selection transistor BT11 then from the main bit line W1 that selects.

As a result, make data be written to storage unit C11 on the intersection point between sub-word line SW11 and the sub-bit-line SB11.

For sense data from storage unit, when the data of storing among the storage unit C11 that wants to read out in such as the first sub-storage array SMA1, only select such as sub-bit-line B1, read voltage so that apply to it.Other main bit lines except main bit line B1 do not have selected.Simultaneously, select the first word line selection wire WSL1, other word line selection wires except the first word line selection wire WSL1 do not have selected.

Make read electric current from the main bit line B1 that selects by sub-bit-line SB11, flow to storage unit C11 and sub-word line SW11.Then, by reading transistor RT11 and sense wire SL1, will read electric current and offer sensor amplifier SA1.

When wanting to write data into storage unit, make several milliamperes the electric current word line of flowing through select transistor WT11 to WT1m, WT21 to WT2m and the selection transistor of the correspondence of WT3g in the WT3k.Therefore,, do not utilize the channel current of common MOS transistor for this electric current, but utilized from drain electrode, promptly with sub-word line SW11 to SW1m, SW21 to SW2m and the terminal of SW3g corresponding sub-word line connection to the SW3k flow to electric current on the substrate.

Fig. 5 is the schematic block diagram according to the MRAM of the third embodiment of the present invention, wherein is arranged with a plurality of sub-memory cell arrays as shown in Figure 4.

In the drawings, sub-memory cell array SMA1 arranges according to the mode of matrix (matrix) to SMA4.

X demoder/write circuit X1 is arranged on the left end of sub-memory cell array SMA1.X demoder/write circuit X1 is used for according to X address XADD, drives the main word line W1 that is connected jointly with sub-memory cell array SMA1 and SMA2 to Wm.X demoder/write circuit X2 is arranged on the left end of sub-memory cell array SMA3.X demoder/write circuit X2 is used for according to X address XADD, drives the main word line Wg that is connected jointly with sub-memory cell array SMA3 and SMA4 to Wk.

Y demoder/write circuit Y1 is arranged on the upper end of sub-memory cell array SMA1.Y demoder/write circuit Y1 is used for according to Y address YADD, drives the main bit line B1 that is connected jointly with sub-memory cell array SMA1 and SMA3 to Bn.Y demoder/write circuit Y2 is arranged on the upper end of sub-memory cell array SMA2.Y demoder/write circuit Y2 is used for according to Y address YADD, drives the main bit line Bh that is connected jointly with sub-memory cell array SMA2 and SMA4 to Bj.

Sensor amplifier SMA1 is arranged on the right-hand member of sub-memory cell array SMA2.To be sent to sensor amplifier SMA1 from the signal that the storage unit of sub-memory cell array SMA1 or sub-memory cell array SMA2 is read, thereby amplify at this.

Sensor amplifier SMA2 is arranged on the right-hand member of sub-memory cell array SMA4.The sensor amplifier SMA2 that will transmit from the signal that the storage unit of sub-memory cell array SMA3 or sub-memory cell array SMA4 is read, thus amplify at this.

The write circuit that will be used for sub-memory cell array SMA1 is arranged between sub-memory cell array SMA1 and the SMA3.The lead-out terminal of write circuit K1 is connected to SBn with sub-bit-line SB1 respectively.Write circuit K1 is used for according to being used to receive the write control circuit 3 that writes data message and 4 output signal D0 and E0 each bar sub-bit-line one of them with supply line or ground path being connected.

Write circuit K2 is separately positioned on the lower end of the lower end of sub-memory cell array SMA2, sub-memory cell array SMA3 and the lower end of memory cell array SMA4 to K4.K1 is similar to write circuit, and these write circuits K2 each in the K4 is used for according to writing data message, and each the bar sub-bit-line in the sub-memory cell array of correspondence is connected with in supply line or the ground path one of them.

The one BSL driver 1 is arranged on the position corresponding with the upper end of the left end of sub-memory cell array SMA1 and X demoder/write circuit X1.Can obtain being used for the digit selection line BSL1 of sub-memory cell array SMA1 and SMA2 from sub-memory cell array SMA1 and SMA2 to a BSL driver 1.When activating position line options line BSL1, a BSL driver 1 response Y address information is electrically connected the sub-bit-line of the correspondence of main bit line and sub-memory cell array SMA1 or SMA2 mutually.

The 2nd BSL driver 2 is arranged on the position corresponding with the upper end of the left end of sub-memory cell array SMA3 and X demoder/write circuit X2.Can obtain being used for the bit line selection wire BSL2 of sub-memory cell array SMA3 and SMA4 from sub-memory cell array SMA3 and SMA4 to the two BSL drivers 2.When activating position line options line BSL2, the 2nd BSL driver 2 response Y address information are electrically connected sub-bit-line corresponding among main bit line and sub-memory cell array SMA3 or the SMA4 mutually.

The one WSL/RSL driver 5 is a kind of circuit, and this circuit is when wanting the data write storage unit, by a strip word line corresponding among chooser memory cell array SMA1 and the SMA3, output signal WSL1; This circuit is when wanting from storage unit sense data, by a strip word line corresponding among chooser memory cell array SMA1 and the SMA3, output signal RSL1.The 2nd WSL/RSL driver 6 is a kind of circuit, and this circuit is when wanting the data write storage unit, by a strip word line corresponding among chooser memory cell array SMA2 and the SMA4, output signal WSL2; This circuit is when wanting from storage unit sense data, by a strip word line corresponding among chooser memory cell array SMA2 and the SMA4, output signal RSL2.Drive these WSL/RSL drivers 5 and 6 according to XADD and the writing/information of reading.

When wanting that data are write the storage unit C11 of sub-memory cell array SMA1, X demoder/write circuit X1 responds XADD, selects main word line W1, and Y demoder/write circuit Y1 respond YADD, selection main bit line B1.The one a BSL driver 1 and a WSL/RSL driver 5, response corresponding address signal activates bit line select signal BSL1 and word line selection signal WSL1 respectively.At this moment, un-activation word line read select signal RSL1 and RSL2.As a result, selected to have the sub-memory cell array SMA1 of the storage unit C11 that belongs to wherein.

In the present embodiment, configuration of the present invention is applied to word line, and traditional configuration is applied to bit line.Yet, in contrast, also can adopt configuration of the present invention is applied to bit line, and traditional configuration is applied to word line.

Owing to do not use channel current to be used for each bar current path that word line is selected transistor and bit line selection transistor, but utilized substrate current, therefore, can make bigger electric current flow through less transistor area, and irrelevant with the ratio of channel width W and channel length L.As a result, can reduce the area of memory cell array.

Fig. 6 is the synoptic diagram that illustrates according to the MRAM of the fourth embodiment of the present invention.

The MRAM of present embodiment comprises: the main word line MWL that is connected with X demoder/write circuit; The sub-word line SWL that is connected with main word line MWL; The word line that is connected with sub-word line SWL is selected transistor WT; Main bit line MBL; The sub-bit-line SBL that is connected with main bit line MBL; And, be arranged on the TMR storage unit between sub-bit-line SBL and the sub-word line SWL.That is to say that this disposes at all substantial not different with the configuration of MRAM shown in Figure 1.

In the present embodiment, by utilize main word line MWL (corresponding to main word line W1 shown in Figure 4 each bar in to Wm and Wg to Wk) and sub-word line (corresponding to sub-word line SW11 shown in Figure 4 to SW1m, SW21 to SW2m and SW3g each bar in the SW3k) the electrostatic capacitance Cmw and the Csw that have respectively, write data into storage unit C.At first, X demoder/write circuit is applied to main word line MWL and sub-word line SWL with predetermined voltage in advance, so that be accumulated in their electrostatic capacitance Cmw and the electric charge of Csw (positive charge and negative charge) respectively.After this, the electric charge of these accumulation is distinguished called after Qmw and Qsw.Similarly, the electrostatic capacitance of X demoder/write circuit by utilizing main bit line MBL and sub-bit-line SBL to have respectively, in advance the main bit line MBL that predetermined voltage is applied respectively (corresponding to main bit line Bl shown in Figure 4 to Bn and Bh to Bj in each bar) and sub-bit-line SBL (corresponding to sub-bit-line SB11 shown in Figure 4 to SB1n, SB21 to SB2n and SB31 each bar in the SB3n) so that be accumulated in electric charge in their electrostatic capacitance.

Then, predetermined input signal is put on the signal input grid Vg that selects transistor WT, wherein, select transistor WT be connected to continuous with the sub-word line SWL that wants selecteed storage unit to be connected, thereby make the transistor WT of selection enter the snap back state.Simultaneously, in the predetermined moment, with predetermined voltage put on be connected to the sub-bit-line SBL that wants selecteed storage unit C to be connected on, selection transistor (not shown).As a result, the electric charge of accumulation, discharges according to the form of discharge current (Fig. 6 only shows the discharge current Ic of sub-word line SWL) at once by the transistor of selection respectively in main word line MBL, sub-word line SWL, main bit line MBL and sub-bit-line SBL.Then, produce magnetic field,, thereby write data into storage unit C so that realize FR (magntic field inversion) to storage unit C by these discharge charge inductions.

Preferably, in order to prevent when writing data into storage unit C by two above-mentioned selection wires, storage unit on the intersection point between a selection wire and the non-selected line is damaged, the structure of selecting transistor WT is optimized, thereby makes snap back have drain voltage such as about 1V.By adopting this method, can current withstand voltage going up (approximately 1.5V) will almost be remained on according to the TMR element of the thickness of tunnel film withstand voltage.

More particularly, be set to about 1V with the drain electrode of the snap back of selection transistor WT shown in Figure 6 is withstand voltage.Use and about corresponding electric power (electricity) of 1V, sub-word line SWL of main word line MWL/ and the main bit line MBL/ sub-bit-line SBL to the storage unit C that wants to write data carries out precharge in advance.Make other main word line/other sub-word line and other main bit line/other sub-bit-line ground connection, perhaps these bit lines and word line are applied the voltage of about 0.5V.

Signal according to the expression write operation begins will make the snap back phenomenon needed voltage occur and be applied to word select line, and predetermined voltage is applied to digit selection line.Therefore, make and select transistor WT to enter the snap back state, so that select transistor BT conducting, thereby, at once the electric charge by the pre-charge process accumulation is discharged according to the form of discharge current.Thereby, by this discharge current, write data among the storage unit C.

According to this embodiment, owing to the form of carrying out according to electric charge discharging instantaneously, use discharge current to write data in the storage unit to interim charging, therefore do not need to use constant current source.Therefore, provide following effect, that is, when stable write current is for example flow through as the write current among first embodiment, compared, can reduce write current with the method that data are provided by the write current that utilizes constant current source to provide.

Though in the present embodiment, the situation that flows to a corresponding strip word line at a main word line that makes write current from correspondence is described,, also can make write current flow to a corresponding sub-bit-line from a main bit line of correspondence.

Should be noted that the present invention is not limited to the foregoing description, therefore, under the situation that does not change purport of the present invention, can carry out various changes and modification by the end personnel of this area.

Illustrated as described above, according to the present invention, can reduce area.

Claims (20)

1. a magnetic RAM (MRAM) comprising:

First distribution by this first distribution, makes write current flow according to a direction;

Select transistor, it is connected with first distribution, is used to control write current; And

A plurality of magnetic cells, each in a plurality of magnetic cells are arranged on respect to the upstream side that is provided with the position of selecting transistorized first distribution, and an end of a plurality of magnetic cells is connected with first distribution.

2. storer according to claim 1 is characterized in that:

Other ends of described a plurality of mram cells are connected with second distribution, by this second distribution, electric current are flowed according to both direction.

3. storer according to claim 2 is characterized in that: first distribution is the first sub-distribution, and the first sub-distribution directly is connected with first main wiring not by transistor; Second distribution is the second sub-distribution, and the second sub-distribution is connected with second main wiring by transistor.

4. MRAM comprises:

Main bit line;

Sub-bit-line, the one end is connected with described main bit line;

Main word line;

Sub-word line, the one end is connected with described main word line;

Mram cell, it is arranged between described sub-word line and the described sub-bit-line; And

Select transistor, it is connected with one of them the other end of described sub-word line and described sub-bit-line.

5. MRAM according to claim 4 is characterized in that: the transistorized substrate current of described selection becomes one of them write current of flow through sub-bit-line and sub-word line.

6. MRAM according to claim 5 is characterized in that: substrate current by voltage breakdown being applied to described selection transistor drain, can make described snap back phenomenon occur based on the snap back phenomenon.

7. MRAM according to claim 5 is characterized in that: write current is the electric current that the electric charge that accumulates in to one of them the electrostatic capacitance of following described main bit line and sub-bit-line and described main word line and sub-word line produces when discharging.

8. MRAM comprises:

Many first sub-lines along the first direction extension;

Many first sub-alignments along the second direction extension that is different from first direction;

First memory cell array, it comprises a plurality of first magnetic cells, each in a plurality of first magnetic cells is arranged on the intersection point between corresponding one described first sub-line and corresponding one the described first sub-alignment;

Many second sub-lines along the first direction extension;

Many second sub-alignments along the second direction extension;

Second memory cell array, it comprises a plurality of second magnetic cells, each in a plurality of second magnetic cells is arranged on the intersection point between corresponding one described second sub-line and corresponding one the described second sub-alignment;

Many articles the 3rd sub-lines according to the first direction extension;

Many articles the 3rd sub-alignments according to the second direction extension;

The 3rd memory cell array, it comprises a plurality of the 3rd magnetic cells, each in a plurality of the 3rd magnetic cells is arranged on the intersection point between corresponding one the described the 3rd sub-line and corresponding one the described the 3rd sub-alignment;

A plurality of main lines, it is set to by described first and second memory cell arrays common;

Many chief series lines, it is set to by the described first and the 3rd memory cell array common;

Wherein, each bar in the many strips line in first memory cell array has two ends, and one of them of two ends is connected with a main line, and the other end in two ends is connected with first row selecting transistor, and

Each bar in many strips alignment in first memory cell array has two ends, and one of them of two ends is connected with a chief series line by the column selection transistor, and the other end in two ends is connected with write circuit.

9. MRAM according to claim 8, it is characterized in that: the predetermined write current of the strip line of flowing through during write operation is when the row selection signal line that prearranged signal is offered row selecting transistor, one of them that makes row selecting transistor reaches conducting state, thereby when the electric charge of accumulation discharges in advance in the electrostatic capacitance of main line and sub-line and the electric current that produces.

10. MRAM according to claim 9 is characterized in that: the conducting state of row selecting transistor is to make electric current flow to state on the substrate from the drain electrode of row selecting transistor.

11. a method for writing data that is used for MRAM wherein, uses the snap back circuit, writes data into selected tunnel magnetoresistive (TMR) unit.

12. method for writing data according to claim 11 is characterized in that: each in a plurality of TMR unit is connected between the common sub-word line, and the write current corresponding with described snap back electric current is in the described sub-word line.

13. method for writing data according to claim 12, it is characterized in that: MOS transistor is with respect to the described TMR unit of having selected, be arranged on the downstream of described sub-word line, and MOS transistor is operated, so that produce described snap back electric current.

14. method for writing data according to claim 13 is characterized in that: the electric current that is used for described data are written to the described TMR unit of having selected flows to described sub-word line from main word line, and the transistor of not flowing through.

15. method for writing data according to claim 14 is characterized in that: before described write current flows in the TMR unit of selecting, stored charge in main word line at least.

16. method for writing data according to claim 15 is characterized in that: the described electric charge of accumulation in sub-word line.

17. a method for writing data that is used for MRAM comprises:

Electric charge is accumulated in one of them the electrostatic capacitance of word line and bit line; And

Charges accumulated is discharged,, thereby write data in the selected TMR unit so that produce discharge current.

18. method for writing data according to claim 17 is characterized in that: described electric charge is accumulated in main word line and the sub-word line.

19. method for writing data according to claim 18 is characterized in that: described electric charge is discharged by the snap back phenomenon.

20. method for writing data according to claim 19 is characterized in that: the voltage that will can not produce described snap back phenomenon offers unselected TMR unit.

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