CN1492313A

CN1492313A - Coordinate transformation method for digital scanning change-over device and processor

Info

Publication number: CN1492313A
Application number: CNA031400159A
Authority: CN
Inventors: 何绪金; 王文芳
Original assignee: Shenzhen Mindray Bio Medical Electronics Co Ltd
Current assignee: Shenzhen Mindray Bio Medical Electronics Co Ltd
Priority date: 2003-07-29
Filing date: 2003-07-29
Publication date: 2004-04-28
Anticipated expiration: 2023-07-29
Also published as: CN100386719C

Abstract

The coordinate transformation method and processor for digital scanning converter is used to transform the rectangular coordinate values (x0, y0) into polar coordinate values (r, p). The transformation method includes initialization; pre-treatment; CORDIC algorithm including a times of left-shift iterative operation and (N-a) times of right-shift iterative operation; radius correction and phase correction. The optimal implementation example of the processor includes input module, pre-treatment module, iterative operation module, radius correction module, phase correction module and output module. The coordinate transformation method and processor may be used in digital scanning converter of B-type ultrasonic imaging instrument for regulating precision, speed and other performance parameters flexibly.

Description

Coordinate conversion method and processor for digital scan converter

Technical Field

The present invention relates to a data processing method and device for performing operation according to the number of bits or content of data to be processed in the field of electrical digital data processing, and more particularly, to a coordinate conversion method and processor for use in a digital scan conversion device of a B-ultrasonic imaging apparatus.

Background

In the digital scan converter in B-ultrasonic imaging instrument, rectangular coordinate data for display is converted into polar coordinate data by table look-up, special coordinate conversion chip or circuit construction. The table look-up method has the defects of limited capacity and high cost; the special coordinate transformation chip is adopted, so that the defect of inflexible performance adjustment exists; by adopting the method for constructing the special circuit, because the rectangular Coordinate is converted into the polar Coordinate generally by a Coordinate rotation digital Computer (CORDIC) algorithm, and the conversion from the rectangular Coordinate to the polar Coordinate is realized by adopting the conventional CORDIC algorithm, the method is not enough for realizing the flexible adjustment of performance parameters such as precision, speed and the like and cannot meet the requirements on high precision, large capacity and real-time work of a developing instrument.

Disclosure of Invention

The invention aims to solve the technical problem of avoiding the defects of the prior art and provides a coordinate conversion method and a processor for a digital scanning conversion device in a B-ultrasonic imaging instrument.

The present invention adopts a technical solution for solving the above technical problems by providing a coordinate transformation method for a digital scan converter, for transforming rectangular coordinate values (x0, y0) into polar coordinate values (r, p), comprising the steps of:

(1) initialization processing: the phase decision variables Xs, Ys and the angle variable z (0) are assigned to 0, and the sign variable cout is assigned to 0_iThe value is assigned to 1;

(2) pretreatment: the phase decision variables Xs, Ys are assigned with rectangular coordinate values (x0, y0), and (x0, y0) are converted into unsigned numbers: if X0 < 0, Xs, 1; if Y0 < 0, Ys is 1;

and (x0, y0) ═ (| x0|, | y0 |);

(3) the CORIDIC algorithm operation is divided into two stages in sequence:

the first stage is as follows: a iterations of the CORDIC algorithm are performed with a left shift operation, i.e.:

i is increased by 1 step from 0 to a-1, and the calculation is cycled:

x(i+1)＝2ⁱ*x(i)+y(i)；y(i+1)＝|2ⁱ*y(i)-x(i)|；

z(i+1)＝z(i)+cout_i*tan^-12^-i；cout_i+1＝cout_i⊙sign(2ⁱ*y(i)-x(i))；

and a second stage: (N-a) iterations of the CORDIC algorithm are performed with a right shift operation, i.e.:

i is increased from a to N-1 by the step size of 1, and the calculation is circulated:

x(i+1)＝x(i)+2^-i*y(i)；y(i+1)＝|y(i)-2^-i*x(i)|；

z(i+1)＝z(i)+cout_i*tan^-12^-i；cout_i+1＝cout_i⊙sign(y(i)-2^-i*x(i))；

(4) radius correction:

(5) phase correction: p ═ z (N)/2^N，

If (Xs, Ys) ═ 0, the p value is not adjusted; if (Xs, Ys) ═ 1, 0, p ═ pi-p;

if (Xs, Ys) ═ 1, p ═ pi + p; if (Xs, Ys) ═ 0, 1, p ═ 2 pi-p.

The present invention also provides a coordinate transformation processor for a digital scan converter, for transforming an input of rectangular coordinate values (x0, y0) into an output of polar coordinate values (r, p), comprising:

(1) an input module

Receiving x0 and y0 from a front-end circuit, and assigning values to the used constants and initial variables: the phase decision variables Xs, Ys and the angle variable z (0) are assigned to 0 and the sign variable cout_iThe value is assigned to 1;

(2) pretreatment module

And (3) distinguishing quadrants x0 and y0, and performing assignment operation:

if X0 < 0, Xs ═ 1; if Y0 < 0, Ys is 1, and x0| x0|, Y0| Y0 |;

(3) an iterative operation module, which is divided into two modules in sequence:

a first module of iterative operations:

the left shift operation is used for realizing a times of iterative operation of the CORDIC algorithm,

namely: i is increased by 1 step from 0 to a-1, and the calculation is cycled:

x(i+1)＝2ⁱ*x(i)+y(i)；y(i+1)＝|2ⁱ*y(i)-x(i)|；

z(i+1)＝z(i)+cout_i*tan^-12^-i；cout_i+1＝cout_i⊙sign(2ⁱ*y(i)-x(i))；

a second module for iterative operation:

the (N-a) iterations of the CORDIC algorithm are implemented with a right shift operation,

namely: i is increased from a to N-1 by the step size of 1, and the calculation is circulated:

x(i+1)＝x(i)+2^-i*y(i)；y(i+1)＝|y(i)-2^-i*x(i)|；

z(i+1)＝z(i)+cout_i*tan^-12^-i；cout_i+1＝cout_i⊙sign(y(i)-2^-i*x(i))；

(4) radius correction module

And (3) carrying out operation:

(5) phase correction module

And (3) carrying out operation: p ═ z (N)/2^N，

If (Xs, Ys) ═ 0, p ═ p; if (Xs, Ys) ═ 1, 0, p ═ pi-p;

if (Xs, Ys) ═ 1, p ═ pi + p; if (Xs, Ys) ═ 0, 1, p ═ 2 pi-p;

(6) output module

And sending the r and p values to a back-end circuit for processing.

Compared with the prior art, the coordinate conversion method and the processor for the digital scanning conversion device can realize the flexible adjustment of performance parameters such as precision, speed and the like of the digital scanning conversion device in the B-ultrasonic imaging instrument and meet the requirements of high precision, large capacity and real-time work of the imaging instrument.

Drawings

FIG. 1 is a schematic block diagram of a preferred embodiment of the coordinate transformation method for a digital scan converter according to the present invention.

Fig. 2 is a schematic circuit diagram of an iterative operation in the iterative pre-stage operation module according to an embodiment of the present invention.

Fig. 3 is a schematic circuit diagram of an iterative operation in the iterative intermediate-stage operation module according to an embodiment of the present invention.

Fig. 4 is a schematic circuit diagram of an iterative operation in the post-iteration operation module according to the embodiment of the present invention.

Detailed Description

The following detailed description is to be read with reference to the best mode embodiment as shown in the drawings.

The coordinate conversion method for a digital scan converter of the present invention for converting rectangular coordinate values (x0, y0) into polar coordinate values (r, p) includes the steps of:

and (x0, y0) ═ (| x0|, | y0 |);

(3) CORDIC arithmetic, in turn divided into two stages:

i is increased by 1 step from 0 to a-1, and the calculation is cycled:

x(i+1)＝2ⁱ*x(i)+y(i)；y(i+1)＝|2ⁱ*y(i)-x(i)|；

z(i+1)＝z(i)+cout_i*tan^-12^-i；cout_i+1＝cout_i⊙sign(2ⁱ*y(i)-x(i))；

x(i+1)＝x(i)+2^-i*y(i)；y(i+1)＝|y(i)-2^-i*x(i)|；

z(i+1)＝z(i)+cout_i*tan^-12^-i；cout_i+1＝cout_i⊙sign(y(i)-2^-i*x(i))；

(4) radius correction:

(5) phase correction: p ═ z (N)/2^N，

if (Xs, Ys) ═ 1, p ═ pi + p; if (Xs, Ys) ═ 0, 1, p ═ 2 pi-p.

The coordinate transformation method for the digital scan converter of the present invention is further described as follows:

the CORDIC algorithm completes the rotation of a vector by an iterative method, thereby completing the operation of transcendental functions such as a trigonometric function, a hyperbolic function, an exponential function and an inverse function thereof. The general iterative formula of the algorithm is:

wherein:

the output of the algorithm after N iterations is:

if we say x₀And y₀The result x is obtained after N iterations when the coordinates are regarded as the abscissa and the ordinate in the rectangular coordinate system_NAnd z_NCorresponding to its square root (with a factor A) and its arctangent (with a constant z), respectively₀). If z is set₀0, and x_NMultiplied by 1/A, then x_NAnd z_NIs exactly with x₀And y₀Radius and phase in the corresponding polar coordinate system. The algorithm works by pursuing strongly the initial vector x₀ y₀]And the X-axis is approached to complete the transformation of rectangular coordinates and polar coordinates.

It is further noted that the initial vector x₀ y₀]Must be located in the first quadrant because

∑tan^-1(2^-i)＜100° (3)

Thus, if the initial vector is not in the first quadrant, the result of the algorithm iteration will not approach the X-axis. Therefore, if the initial vector is in the other quadrant, a corresponding correction to the algorithm must be made. The following study is limited to the case where the initial vector is in the first quadrant, and the case where the initial vector is in the other quadrants will be explained later.

The CORIC algorithm is carefully studied, for the first equation in the equation set (1), when y_iWhen d is greater than or equal to 0_iIs equal to-1 and has

x_i+1＝x_i+y_i2^-i＝x_i+|y_i|2^-i (4)

Can obtain x_i+1＞x_i. Also, in the same manner as above,when y is_iWhen < 0, d _i1 and has

x_i+1＝x_i-y_i2^-i＝x_i+|y_i|2^-i (5)

X can also be obtained_i+1＞x_i. So x_iIs an increasing sequence, taking into account x₀> 0, so x_iIs an increasing positive sequence of numbers.

For the second equation in equation set (1), when y_iWhen d is greater than or equal to 0_iCan be simplified to-1

y_i+1＝y_i-x_i2^-(i+1)＝|y_i|-x_i2^-(i+1) (6)

Due to x_iIs a sequence of positive numbers, so this can be considered as a subtraction of two positive numbers; when y is_iWhen < 0, d _i1, the formula is simplified to

y_i+1＝y_i+x_i2^-(i+1)＝x_i2^-(i+1)-|y_i| (7)

This can also be considered as a subtraction of two unsigned numbers. But at this time y_i+1Is not determined, and in order to make it easy to implement hardware and to keep the same as equation (6), equations (6, 7) are unified as:

y_i+1＝|y_i-x_i2^-(i+1)| (8)

at this time, equation set (1) becomes:

wherein,

by adopting the CORDIC algorithm of the equation set (9), the operation speed of the algorithm can be improved, and the following table shows software simulation (precision analysis) and hardware simulation results (resource consumption and operation speed analysis) during signed operation and unsigned operation:

	with a symbol	Without sign	Note
	with a symbol	Without sign	Note	Length of x, y, z	16Bits	16Bits	Note	1
Resource consumption	1754 logic unit (35%)	1737 logic units (34%)	Note 2	Length of x, y, z	16Bits	16Bits	Note	1
Resource consumption	1754 logic unit (35%)	1737 logic units (34%)	Note 2	Maximum frequency of realization	27.93MHZ	47.16MHZ	Note 2
Radius accuracy (LSB)	2.31(-2.55 7.38)	1.98(-3.98 0.0)	Note 3	Maximum frequency of realization	27.93MHZ	47.16MHZ	Note 2
Radius accuracy (LSB)	2.31(-2.55 7.38)	1.98(-3.98 0.0)	Note 3	Phase accuracy (LSB)	4.23(-77.78 88.73)	4.62(-88.59 88.73)	Note 3

Note 1: in the simulation process, the word length of x and y is extended to 18Bits (left-shifted by two Bits), and z includes a decimal place of 15 Bits.

Note 2: the simulation is implemented in the FPGA (field programmable gate array) of Altera corporation of america and employs a pipeline architecture.

Note 3: the absolute average error is the maximum negative error and the maximum positive error in parentheses respectively.

As can be seen from the above table, changing the signed operation to the unsigned operation does not significantly improve the resource consumption, the radius and the phase precision, but greatly improves the highest frequency of the operation.

Analysis of equation set (9) reveals that there is some value of b, y_bIs less than or equal to (b +1), then y_bShifted right by (b +1) bit and equals zero, at which time x_bRemain unchanged. In later iterations, since y_iFurther decrease and increase of i, x_iWill remain unchanged throughout, thereby eliminating the need to perform the operation of equation one in equation set (9). And the b value can be determined by software simulation.

Further studying the CORIC algorithm, we can find that the main sources of errors in the algorithm are: at x_i、y_iIn the iterative process, the right shift operation (x 2) exists^-i) Resulting in truncation errors fromAnd part of the precision is lost, so that the final result has larger error. Therefore, the precision can be improved by eliminating the truncation error by the following method: the right shift operation is replaced by a left shift operation, i.e. the equation set (9) is changed to the form:

wherein,

however, this greatly increases the required hardware resources, which results in a reduction in the computation speed of the algorithm.

Taken together, we can arrive at a solution to the problem: the system of equations (10) is used in the first iteration (a) and the system of equations (9) is used in the subsequent iterations.

It should be noted that, since the left shift operation is used, after the iteration is completed, the obtained radius must be corrected, as shown in the following formula:

the following two tables give the software simulation (precision analysis) and hardware simulation results (resource consumption, computation speed analysis) for different values of a in equation set (9) (without left shift operation) and equation set (10) (with left shift operation):

	without using a left-shift operation	By left-hand movement (a 1)	Note
	without using a left-shift operation	By left-hand movement (a 1)	Note	Length of x, y, z	16Bits	16Bits	Note	1
Resource consumption	1737 logic units (34%)	18541964 logic cell (37%)	Note 2	Length of x, y, z	16Bits	16Bits	Note	1
Resource consumption	1737 logic units (34%)	18541964 logic cell (37%)	Note 2	Maximum frequency of realization	47.16MHZ	45.45MHZ	Note 2
Radius accuracy (LSB)	1.98(-3.98 0.0)	1.14(-2.30 0)	Note 3	Maximum frequency of realization	47.16MHZ	45.45MHZ	Note 2
Radius accuracy (LSB)	1.98(-3.98 0.0)	1.14(-2.30 0)	Note 3	Phase accuracy (LSB)	4.62(-88.59 88.73)	2.40(-51.91 52.06)	Note 3

	By left-hand movement (a is 2)	By left-hand movement (a is 3)	Note
	By left-hand movement (a is 2)	By left-hand movement (a is 3)	Note	Length of x, y, z	16Bits	16Bits	Note	1
Resource consumption	1964 logic unit (39%)	2142 logic cell (42%)	Note 2	Length of x, y, z	16Bits	16Bits	Note	1
Resource consumption	1964 logic unit (39%)	2142 logic cell (42%)	Note 2	Maximum frequency of realization	43.85MHZ	42.73MHZ	Note 2
Radius accuracy (LSB)	-0.52(0 1.04)	-0.33(0 0.66)	Note 3	Maximum frequency of realization	43.85MHZ	42.73MHZ	Note 2
Radius accuracy (LSB)	-0.52(0 1.04)	-0.33(0 0.66)	Note 3	Phase accuracy (LSB)	1.03(-12.0 12.15)	0.81(-3.26 3.41)	Note 3

Note 1: in the simulation process, when the left shift operation is not adopted, the word length of x and y is expanded to 18Bits (left shift by 2 Bits); when a left shift operation is adopted and a is equal to 1, the word length of x and y is expanded to 19Bits (left shift by 3 Bits); when a is 2, the word length of x and y is expanded to 21Bits (left-shifted by 5 Bits); when a is 3, the word length of x and y is extended to 24Bits (left-shifted by 8 Bits). z comprises 15Bits decimal places.

Note 2: the simulation was implemented in an FPGA of Altera corporation of america and employed a pipeline architecture.

It can be seen from the above two tables that the higher the number of left shift operations, i.e. the higher the value of a, the higher the accuracy of the radius and phase, and accordingly the higher the resource consumption, the lower the highest frequency of operation.

The coordinate conversion processor for a digital scan converter of the present invention for converting an input of rectangular coordinate values (x0, y0) into an output of polar coordinate values (r, p) includes:

(1) an input module

(2) pretreatment module

if X0 < 0, Xs ═ 1; if Y0 < 0, Ys is 1, and x0| x0|, Y0| Y0 |;

a first module of iterative operations:

namely: i is increased by 1 step from 0 to a-1, and the calculation is cycled:

x(i+1)＝2ⁱ*x(i)+y(i)；y(i+1)＝|2ⁱ*y(i)-x(i)|；

z(i+1)＝z(i)+cout_i*tan^-12^-i；cout_i+1＝cout_i⊙sign(2ⁱ*y(i)-x(i))；

a second module for iterative operation:

x(i+1)＝x(i)+2^-i*y(i)；y(i+1)＝|y(i)-2^-i*x(i)|；

z(i+1)＝z(i)+cout_i*tan^-12^-i；cout_i+1＝cout_i⊙sign(y(i)-2^-i*x(i))；

(4) radius correction module

And (3) carrying out operation:

(5) phase correction module

And (3) carrying out operation: p ═ z (N)/2^N，

If (Xs, Ys) ═ 0, p ═ p; if (Xs, Ys) ═ 1, 0, p ═ pi-p;

if (Xs, Ys) ═ 1, p ═ pi + p; if (Xs, Ys) ═ 0, 1, p ═ 2 pi-p;

(6) output module

And sending the r and p values to a back-end circuit for processing.

The coordinate transformation processor for the digital scan converter of the present invention is further described as follows:

in order to increase the operation speed of the CORDIC algorithm, a one-stage pipeline structure is adopted for each iteration, so that although N cycles are needed for transforming a single datum, for a data stream, the transformation can be completed once every cycle (the result is delayed by N cycles as a whole), and a specific description is given to each module according to the schematic block diagram of the processor shown in fig. 1 as follows:

an input module: receiving a signal x from a front-end circuit₀、y₀And performing initialization work of iterative formula operation, and assigning values to the used constants and initial variables.

A preprocessing module: distinguishing Signal x₀、y₀And assigning the symbols to Xs and Ys, respectively.

An iterative operation module: the operation is carried out according to an iterative equation set, and the operation can be divided into three sub-modules:

an iteration front-end module: the operation is performed according to equation set (10), that is, the truncation error is eliminated in the iteration, the value of a can be considered in a trade-off manner according to the resource consumption and the implementation speed of the algorithm, and the specific circuit structure of each operation is shown in fig. 2, and includes:

for x (i +1), y (i +1) calculationTwo left shift operators, two unsigned addition operators and an absolute value operator; an unsigned adder for z (i +1) computation; for cout_i+1A logic controller for computing.

An iteration middle section module: operating according to equation (9), i.e. without canceling the truncation error in the iteration, the value of b can be obtained by software simulation, which means that if in the b-th iteration y is_bIs less than or equal to (b +1), then y_bShifted right by (b +1) bit and equals zero, at which time x_bRemain unchanged. In later iterations, since y_iFurther decrease and increase of i, x_iWill remain unchanged all the time, and the specific circuit structure of each operation thereof is shown in fig. 3, including:

two right shift operators for x (i +1), y (i +1) calculations, two unsigned addition operators and an absolute value operator; an unsigned adder for z (i +1) computation; for cout_i+1A logic controller for computing.

An iteration back-end module: during this period x_iThe formula is not changed any more, so that the iterative operation of the formula is not performed, and the other operations are performed according to the equation set (9), and the specific circuit structure of each operation is shown in fig. 4, and includes:

a latch for x (i +1) computation; a right shift operator, an unsigned addition operator and an absolute value operator for y (i +1) calculations; an unsigned adder for z (i +1) computation; for Cout_i+1A logic controller for computing.

A radius correction module: according to the equation set (2) and the equation (11), since the radius r obtained after iteration has a factor a and is shifted to the right, the radius r is corrected by a multiplier and a shift operator

A phase correction module: according to the value of Xs, Ys (i.e. x)₀、y₀Quadrant in which p is located) corrects p.

An output module: the corrected radius r and phase p are output to the back-end circuit.

Claims

1. A coordinate conversion method for a digital scan converter for converting rectangular coordinate values (x0, y0) into polar coordinate values (r, p), comprising the steps of:

(2) pretreatment: the phase decision variables Xs, Ys are assigned with rectangular coordinate values (x0, y0), and (x0, y0) are converted into unsigned numbers: if X0 < 0, Xs, 1; if Y0 < 0, Ys is 1; and (x0, y0) ═ (| x0|, | y0 |);

(3) CORDIC arithmetic, in turn divided into two stages:

i is increased by 1 step from 0 to a-1, and the calculation is cycled:

x(i+1)＝2ⁱ*x(i)+y(i)；y(i+1)＝|2ⁱ*y(i)-x(i)|；

z(i+1)＝z(i)+cout_i*tan^-12^-i；cout_i+1＝cout_i⊙sign(2ⁱ*y(i)-x(i))；

x(i+1)＝x(i)+2^-i*y(i)；y(i+1)＝|y(i)-2^-i*x(i)|；

z(i+1)＝z(i)+cout_i*tan^-12^-i；cout_i+1＝cout_i⊙sign(y(i)-2^-i*x(i))；

(4) radius correction:

(5) phase correction: p ═ z (N)/2^N，

if (Xs, Ys) ═ 1, p ═ pi + p; if (Xs, Ys) ═ 0, 1, p ═ 2 pi-p.

2. The coordinate conversion method for a digital scan conversion apparatus according to claim 1, wherein: the second stage in the step (3) can be further divided into two stages in sequence:

b value pre-stage: (b-a) iterations of the CORDIC algorithm are performed with a right shift operation, i.e.:

i is increased by 1 step from a to b-1, and the calculation is circulated:

x(i+1)＝x(i)+2^-i*y(i)；y(i+1)＝|y(i)-2^-i*x(i)|；

z(i+1)＝z(i)+cout_i*tan^-12^-i；cout_i+1＝cout_i⊙sign(y(i)-2^-i*x(i))；

b value post stage: (N-b) iterations of CORDIC algorithm with right shift operation, but stopping on x variable

Iterative operations, namely:

i is increased from b to N-1 by the step size of 1, and the calculation is circulated:

x(i+1)＝x(i)；y(i+1)＝|y(i)-2^-i*x(i)|；

z(i+1)＝z(i)+cout_i*tan^-12^-i；cout_i+1＝cout_i⊙sign(y(i)-2^-i*x(i))。

3. the coordinate conversion method for a digital scan conversion apparatus according to claim 1 or 2, wherein: the preferred value of a in the step (3) is 3.

4. A coordinate conversion processor for a digital scan conversion device for converting an orthogonal coordinate value (x0, y0) input into a polar coordinate value (r, p) output, comprising:

(1) an input module

(2) pretreatment module

if X0 < 0, Xs ═ 1; if Y0 < 0, Ys is 1, and x0| x0|, Y0| Y0 |;

a first module of iterative operations:

namely: i is increased by 1 step from 0 to a-1, and the calculation is cycled:

x(i+1)＝2ⁱ*x(i)+y(i)；y(i+1)＝|2ⁱ*y(i)-x(i)|；

z(i+1)＝z(i)+cout_i*tan^-12^-i；cout_i+1＝cout_i⊙sign(2ⁱ*y(i)-x(i))；

a second module for iterative operation:

x(i+1)＝x(i)+2^-i*y(i)；y(i+1)＝|y(i)-2^-i*x(i)|；

z(i+1)＝z(i)+cout_i*tan^-12^-i；cout_i+1＝cout_i⊙sign(y(i)-2^-i*x(i))；

(4) radius correction module

And (3) carrying out operation:

(5) phase correction module

And (3) carrying out operation: p ═ z (N)/2^N，

If (Xs, Ys) ═ 0, p ═ p; if (Xs, Ys) ═ 1, 0, p ═ pi-p;

if (Xs, Ys) ═ 1, p ═ pi + p; if (Xs, Ys) ═ 0, 1, p ═ 2 pi-p;

(6) output module

And sending the r and p values to a back-end circuit for processing.

5. The coordinate conversion processor for a digital scan conversion device according to claim 4, wherein: the iterative operation second module in the iterative operation module can be further divided into two modules in sequence:

b value front module: the (b-a) iteration of the CORDIC algorithm is implemented with a right shift operation,

x(i+1)＝x(i)+2^-i*y(i)；y(i+1)＝|y(i)-2^-i*x(i)|；

z(i+1)＝z(i)+cout_i*tan^-12^-i；cout_i+1＝cout_i⊙sign(y(i)-2^-i*x(i))；

b value post module: implementing (N-b) iterations of the CORDIC algorithm with a right shift operation, but stopping on the x variable

Iterative operations, namely: i is increased from b to N-1 by the step size of 1, and the calculation is circulated:

x(i+1)＝x(i)；y(i+1)＝|y(i)-2^-i*x(i)|；

z(i+1)＝z(i)+cout_i*tan^-12^-i；cout_i+1＝cout_i⊙sign(y(i)-2^-i*x(i))。

6. the coordinate conversion processor for a digital scan conversion device according to claim 4, wherein: the circuit used for one iteration operation in the iteration operation first module comprises: for x (i +1), y (i +1)) Two left shift operators, two unsigned addition operators and an absolute value operator; an unsigned adder for z (i +1) computation; for cout_i+1A logic controller for computing; the circuit used for one iteration operation in the second module of the iteration operation comprises: two right shift operators, two unsigned addition operators and an absolute value operator for x (i +1), y (i +1) calculations; an unsigned adder for z (i +1) computation; for cout_i+1A logic controller for computing.

7. The coordinate conversion processor for a digital scan conversion device according to claim 5, wherein: the circuit used for one iteration operation in the iteration operation first module comprises: two left shift operators, two unsigned addition operators and an absolute value operator for x (i +1), y (i +1) calculations; an unsigned adder for z (i +1) computation; for cout_i+1A logic controller for computing; the circuit used for one iteration operation in the b value pre-module of the second iteration operation module comprises: two right shift operators, two unsigned addition operators and an absolute value operator for x (i +1), y (i +1) calculations; an unsigned adder for z (i +1) computation; for cout_i+1A logic controller for computing; the circuit used for one iteration operation in the module after the b value of the second module is iterated operation comprises: a right shift operator, an unsigned addition operator and an absolute value operator for y (i +1) calculations; an unsigned adder for z (i +1) computation; for cout_i+1A logic controller for computing.

8. A coordinate conversion processor for a digital scan conversion device as defined in any one of claims 4 to 7, wherein: the radius correction module includes: a multiplication operator and a right shift operator.

9. A coordinate conversion processor for a digital scan conversion device as defined in any one of claims 4 to 7, wherein: and a first-stage pipeline structure is adopted for each iteration in the iterative operation module.

10. A coordinate conversion processor for a digital scan conversion device as defined in any one of claims 4 to 7, wherein: the preferred value of a in the iterative operation module is 3.