CN1489050A - IDE channel measuring apparatus and method - Google Patents
IDE channel measuring apparatus and method Download PDFInfo
- Publication number
- CN1489050A CN1489050A CNA021349487A CN02134948A CN1489050A CN 1489050 A CN1489050 A CN 1489050A CN A021349487 A CNA021349487 A CN A021349487A CN 02134948 A CN02134948 A CN 02134948A CN 1489050 A CN1489050 A CN 1489050A
- Authority
- CN
- China
- Prior art keywords
- ide
- data
- board
- test
- under test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The testing device comprises IDE testing board, the board with IDE controller to be tested, and connection line between IDE testing board and board to be tested. There is firmware stored in the board to be tested, and there are several IDE connectors, decoders and buffering circuits on IDE testing board. The testing method includes following steps. After starting the board to be tested, the firmware in the board to be tested sends out IDE command, writing data to IDE channel to be tested. IDE testing board receives the command, and writes data to buffered circuit. The firmware sends out IDE command to read data in IDE channel. After IDE command being received, the IDE testing board sends out data. The firmware compares written data and read data. If both are identical, successful testing is displayed; otherwise, failed testing as well as failed data is displayed. Testing flow is finished.
Description
[technical field]
The present invention relates to a kind of hard-disk interface channel measuring apparatus and method, relate in particular to a kind of I DE channel measuring apparatus and method.
[background technology]
Hard disk is a computer memory device the most used in our daily life, current seagate just develops towards high capacity, high-speed direction, therefore the interface rate between computing machine and the hard disk also must be continually strengthened, in order to avoid the problem of data stream bottleneck link occurs, the IDE hard disk is subjected to using widely because of higher performance.
Prior art related to the present invention please refer to United States Patent (USP) the 5th, 644, No. 705,5,832, No. 418,6,006, No. 166 and 6,076, shown in No. 180, these prior aries generally are connected on the board under test with hard disk, and come archives on the access hard disk with software, when the content of reading back is consistent with the content that is write, represent that then the IDE function on the board under test is no problem.Board under test is meant the surface-mounted integrated circuit that contains IDE controller and connector, as motherboard etc.But these tests all need hard disk and operating system, and cost is higher, inconvenient operation.
[summary of the invention]
The object of the present invention is to provide a kind of cost IDE channel measuring apparatus and method lower, simple to operate.
The objective of the invention is to be achieved through the following technical solutions: IDE channel measuring apparatus of the present invention comprises the IDE test board, is provided with the board under test of IDE controller and the cable of connection ID E test board and board under test, wherein store firmware in the board under test, then be provided with some IDE connectors, code translator and cache lines on the IDE test board.
IDE lane testing method of the present invention comprises the steps:
After starting board under test, the firmware in the board under test sends the IDE order, and the data of writing out is in the IDE passage that will test;
The IDE test board is received this order, and by " writing " order effect of control bus control code translator, so data is written in the cache lines by data bus by an IDE connector;
Firmware in the board under test sends the IDE order, read the data in the IDE passage, the IDE test board is received this IDE order, and by " reading " order effect of control bus control code translator, the data that makes cache lines just to have deposited in is sent board under test back to by data bus and another IDE connector;
The data that firmware in the board under test relatively writes and reads;
If both are identical, show then and test successfully that testing process finishes;
If both are inequality, then show test crash, and demonstrate the data of failure that testing process finishes.
Compared to prior art, IDE channel measuring apparatus of the present invention and method only need test board is connected on the board under test by cable, starting board under test then can test, and utilize cache lines to replace hard disk and test, save hard disk needed in the art and operating system, therefore saved cost, simple to operate.
[description of drawings]
Fig. 1 is test board part block hardware diagram in the IDE channel measuring apparatus of the present invention.
Fig. 2 is the process flow diagram of IDE lane testing method of the present invention.
[embodiment]
Please refer to Figure 1 and Figure 2, IDE channel measuring apparatus of the present invention comprises the cable (not shown) of IDE test board 1, board under test and connection ID E test board 1 and board under test.Wherein store firmware in the board under test, then be provided with some IDE connectors on the IDE test board 1 and (be four in the present embodiment, be respectively first, second IDE connector 61,62 and the 3rd, the 4th IDE connector), two code translators 12 and two first-in first-out (FIFO) cache lines 13, and per two IDE connectors are corresponding to a code translator and a first-in first-out cache lines, and Fig. 2 only illustrates wherein the electrical connection of two IDE connectors 61,62 and a corresponding code translator 12 and a first-in first-out cache lines 13.
Board under test be meant be provided with the IDE controller and with the IDE test board on corresponding some IDE connectors (be four in the present embodiment, be respectively the 5th, the 6th, the 7th and the 8th IDE connector) the computer integrate circuit plate, as motherboard etc., the IDE controller then comprises two IDE passages.By four cables the first, second, third and the 4th IDE connector on the IDE test board 1 is linked to each other with the 5th, the 6th, the 7th and the 8th IDE connector on the board under test respectively before the IDE channel measuring apparatus of the present invention test, thereby IDE test board 1 is connected with board under test, and starting board under test then can test.
Please refer to shown in Figure 2ly, IDE lane testing method of the present invention may further comprise the steps:
Step 70: after starting board under test, the firmware in the board under test sends the IDE order, and the data of writing out is in the IDE passage that will test;
Step 71:IDE test board 1 is received this order, write data in first-in first-out cache lines 13 by an IDE connector 61, this moment is by " writing " order effect of control bus 43 control code translators 12, so data is input in the first-in first-out cache lines 13 by data bus 41 by an IDE connector 61;
Step 72: the firmware in the board under test sends the IDE order, read the data in the IDE passage, the IDE test board is received this IDE order, from first-in first-out cache lines 13, read data by the 2nd IDE connector 62, this moment, the data that makes first-in first-out cache lines 13 just to have deposited in was sent board under test back to by data bus 42 and the 2nd IDE connector 62 by " reading " order effect of control bus 44 control code translators 12;
Step 73: the data that the firmware in the board under test relatively writes and reads;
Step 74:, show then and test successfully that testing process finishes if both are identical;
Step 75: if both are inequality, then show test crash, and demonstrate the data of failure that testing process finishes.
The above only is the method for testing of an IDE passage, and the method for testing of another I DE passage is identical therewith, so repeat no more.
In IDE lane testing method of the present invention, if detect failure,, can analyze the bad point of IDE on the board under test according to the data of failure, specifically be divided into following three kinds of situations:
First kind of situation: if fail when sending the first stroke data, then may address bus or data bus or control signal bad, need this moment do electric circuit inspection to board under test, the reason that locates errors.
Second kind of situation: if error in address, address bus has eight, and therefore which bar address bus is bad as can be known by the address value that shows.
The third situation: if error in data, data bus is from 0000 to FFFF, and it is bad to analyze which bar data bus by the data that show failure.
Claims (6)
1. IDE channel measuring apparatus, comprise the IDE test board, be provided with the board under test of IDE controller and the cable of connection ID E test board and board under test, wherein store firmware in the board under test, the IDE test board is provided with some IDE connectors, code translator and cache lines, this IDE channel measuring apparatus mechanism is: the firmware in the board under test sends the IDE order, the data of writing out is in the IDE passage that will test, the IDE test board is received this order, " writing " order effect of code translator, data is written in the cache lines by an IDE connector; Firmware in the board under test sends the IDE order, reads the data in the IDE passage, and the IDE test board is received this IDE order, " reading " order effect of code translator, and the data that makes cache lines just to have deposited in is sent board under test back to by another IDE connector; The data that firmware in the board under test relatively writes and reads if both are identical, shows then and tests successfully that testing process finishes; If both are inequality, then show test crash, and demonstrate the data of failure that testing process finishes.
2. IDE channel measuring apparatus according to claim 1 is characterized in that: described cache lines is the first-in first-out cache lines.
3. IDE channel measuring apparatus according to claim 2 is characterized in that: the read write command of described code translator is controlled by control bus.
4. IDE channel measuring apparatus according to claim 3 is characterized in that: described I DE connector is by data bus access data in the first-in first-out cache lines.
5. an IDE lane testing method comprises the steps:
After starting board under test, the firmware in the board under test sends the IDE order, and the data of writing out is in the IDE passage that will test;
The IDE test board is received this order, and by " writing " order effect of control bus control code translator, so data is written in the cache lines by data bus by an IDE connector;
Firmware in the board under test sends the IDE order, read the data in the IDE passage, the IDE test board is received this IDE order, and by " reading " order effect of control bus control code translator, the data that makes cache lines just to have deposited in is sent board under test back to by data bus and another IDE connector;
The data that firmware in the board under test relatively writes and reads;
If both are identical, show then and test successfully that testing process finishes;
If both are inequality, then show test crash, and demonstrate the data of failure that testing process finishes.
6. IDE lane testing method according to claim 5 is characterized in that: described cache lines is the first-in first-out cache lines.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021349487A CN1328665C (en) | 2002-10-11 | 2002-10-11 | IDE channel measuring apparatus and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021349487A CN1328665C (en) | 2002-10-11 | 2002-10-11 | IDE channel measuring apparatus and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1489050A true CN1489050A (en) | 2004-04-14 |
| CN1328665C CN1328665C (en) | 2007-07-25 |
Family
ID=34146020
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021349487A Expired - Fee Related CN1328665C (en) | 2002-10-11 | 2002-10-11 | IDE channel measuring apparatus and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1328665C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930392B (en) * | 2009-06-19 | 2012-08-29 | 富港电子(昆山)有限公司 | Device for testing mobile hard disk |
| CN101455009B (en) * | 2006-04-14 | 2014-03-26 | 莱特普茵特公司 | Method for testing embedded wireless transceiver with minimal interaction between wireless transceiver and host processor during testing |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5909592A (en) * | 1994-09-07 | 1999-06-01 | Intel Corporation | Method in a basic input-output system (BIOS) of detecting and configuring integrated device electronics (IDE) devices |
| US5644705A (en) * | 1995-01-11 | 1997-07-01 | International Business Machines Corporation | Method and apparatus for addressing and testing more than two ATA/IDE disk drive assemblies using an ISA bus |
| US5832418A (en) * | 1997-06-23 | 1998-11-03 | Micron Electronics | Apparatus for testing a controller with random contraints |
| JP2000285036A (en) * | 1999-03-30 | 2000-10-13 | Fujitsu Ltd | Interface test device |
-
2002
- 2002-10-11 CN CNB021349487A patent/CN1328665C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101455009B (en) * | 2006-04-14 | 2014-03-26 | 莱特普茵特公司 | Method for testing embedded wireless transceiver with minimal interaction between wireless transceiver and host processor during testing |
| CN101930392B (en) * | 2009-06-19 | 2012-08-29 | 富港电子(昆山)有限公司 | Device for testing mobile hard disk |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1328665C (en) | 2007-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1245687C (en) | Method and device for testing USB port | |
| US6055653A (en) | Method and apparatus for testing gang memory modules | |
| CN1675625A (en) | Memory hub with internal cache and/or memory access prediction | |
| JPH08234879A (en) | Combination structure of desk-top computer with adaptor and manufacture | |
| CN1869943A (en) | Method for detecting audio connection function of audio receiver and computer mainframe board | |
| CN1223053C (en) | Plate card position inspecting method | |
| CN200944233Y (en) | Universal serial bus testing device | |
| CN1317846C (en) | Method of realizing internal external network physical partition and its device | |
| CN1489050A (en) | IDE channel measuring apparatus and method | |
| CN101046760A (en) | Storage device, data arrangement method and program | |
| CN1924844A (en) | Method and device for automatically adjusting bus width | |
| CN1955942A (en) | IEEE1394 interface function detection device and method | |
| CN1542839A (en) | Memory system mounted directly on board and associated method | |
| CN2874629Y (en) | Error insert analogue device of computer test | |
| CN101059769A (en) | Universal serial bus device test system and its method | |
| CN1315050C (en) | A method for detecting PC Card interface data wire and address wire | |
| CN200959120Y (en) | Copy path selector | |
| CN1682194A (en) | Method for event synchronisation, especially for processors of fault-tolerant systems | |
| CN1892634A (en) | PCI Express expanding-slot circuit and design method | |
| CN1195254C (en) | Interface circuit of peripheral interface-small computer system interface | |
| CN1221152A (en) | Bus control system | |
| CN1983208A (en) | System and method for constructing virtual testing environment | |
| TWI230856B (en) | An apparatus for IDE channel testing | |
| CN1725190A (en) | Detection method for failure of address bus | |
| CN1658178A (en) | Method for deciding bit allocation ofbridge chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070725 Termination date: 20131011 |